JP3055563B2 - How to change filter coefficient of digital filter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for changing a filter coefficient of a digital filter.

Thanks to the emergence of digital signal processors (hereinafter referred to as DSPs) that can execute multiply-accumulate operations at high speed,
Digital signal processing by a digital filter or the like realized by software processing has become a reality, and has become widespread in the fields of communication equipment, audio equipment, and the like.

The present invention refers to a method of changing the filter coefficients to change the characteristics of the digital filter.

[Conventional technology]

For example, there is a device including a digital filter capable of giving a cutoff frequency, a gain, and a sharpness Q of the filter as parameters, such as a parametric equalizer of an audio device. When the characteristics are changed by giving parameters to such a filter, an operation requiring a relatively long operation time including an operation of a trigonometric function is required as described in detail below.

FIG. 5 shows a secondary filter 10 as an example of a digital filter. The transfer function of this filter is Given by Then, the filter difference equation y [n] = a ₀ x [n] + a ₁ x [n-1] + a ₂ x [n-2] + b ₁ y [n-1] + b ₂ y [n- 2] It is realized by executing the operation represented by (2). Here, x [i] (i = 1... N) is the value of the input signal in each sampling cycle, and y [i] (i = 1... N) is the value of the output signal. The coefficients a ₀ , a ₁ , a ₂ , b ₁ , b ₂ are constants that determine the characteristics of the filter, and by changing these,
The characteristics of the filter are changed.

As a simple example of a filter provided in a parametric equalizer, a filter capable of changing only the cutoff frequency of the filter will be considered below. In this case, the aforementioned a ₀ , a ₁ , a ₂ , b ₁ , b ₂ are a ₀ = 1 / (1 + 1 / ω ₀ ) (3) a ₁ = a ₀ b ₁ = (− 1 + 1 / ω ₀ ) / ((1 + 1 / ω ₀ ) (4) a ₂ = b ₂ = 0 (5) ω ₀ = tan (π · f _d / f _s ) (6) where f _d is calculated by the filter The cutoff frequency is fs, and f _s is the reciprocal of the operation cycle of the digital filter.As shown in equation (6), the filter coefficient calculation processing for a filter whose characteristic can be changed using the cutoff frequency of the filter as a parameter includes: Includes trigonometric operations that require significantly longer operation times.

As means for performing the operations of the expressions (3) to (6), DSP
The control may be executed by a control device such as a microcomputer which is usually provided, or by the DSP itself.

In the former case, since the processing is performed on the side of the apparatus not directly involved in the filter operation, the configuration is relatively easy. However, the necessary memory capacity increases because an unnecessary floating-point arithmetic package must be added for the processing of the ordinary microcomputer for DSP control in order to realize in the microcomputer normally provided. In addition, since the calculation time is on the order of seconds, the response becomes slow and is not practical. Also, when transferring a plurality of calculated filter coefficients from the control microcomputer to the DSP, it takes about ten times as long as the operation cycle to transfer one coefficient. A filter operation is performed with an unexpected combination of coefficients, which may cause pop noise or oscillation.

In the latter case, there is no problem in terms of calculation speed because the DSP has a function of calculating floating-point numbers as hardware in the first place. Further, since all the filter coefficients can be replaced within one cycle of the filter operation, there is no possibility of occurrence of the above-described pop noise or oscillation.

FIG. 6 is a timing chart when the above-described calculation of the filter coefficient is performed in the DSP. In the figure, A represents the input of input data x [i], executing a filter operation as represented by equation (2), and executing a process of outputting the result, and B represents, for example, (3) to (6). Represents the execution of a coefficient calculation process as represented by. Further, T represents one cycle of the operation, and usually, in audio signal processing,
It is required that the number of steps is about 20 microseconds or less, that is, about 200 steps or less.

Therefore, in the method as shown in FIG. 6, the filter operation processing A and the filter coefficient operation processing B must be accommodated within one cycle T. It is a target.

In addition, since the A section must be shortened by the length of the B section, the amount of filter operation that can be realized within the time limit of the period T decreases, and the processing must be divided into another DSP. There is also the problem of not being able to do so.

FIG. 7 is a timing chart in a system in which this problem is improved. In the calculation cycle in which the filter coefficient calculation process B is performed, a simplified process A 'is performed instead of the filter calculation process A. In this process A ', the calculation of the difference equation (2) is not performed, and the same result as that calculated in the previous calculation cycle is output as the calculation result. By doing so, it becomes possible to perform the filter operation by fully using the operation period T in the operation period in which the filter coefficient processing B is not performed, and the DSP can be used efficiently.

[Problems to be solved by the invention]

If the filter coefficient calculation processing is as simple as represented by the equations (3) to (6), no problem occurs in the above-described method. However, as the number of types of parameters increases and the order of the filter increases, the calculation process becomes complicated, and the calculation time also increases, sometimes reaching several times the calculation period. in this case,
In the above-described method, a constant value is output over several operation cycles, and the signal distortion becomes large enough to be ignored.

FIG. 8 is a diagram showing this state. In the figure, a sinusoidal curve represents an analog signal before analog-to-digital (A / D) conversion, and a white circle and a step-like line connecting them represent a discrete signal after analog-to-digital conversion of the analog signal. It represents. If it is assumed that the filter coefficient calculation process requires four calculation cycles, the step-like line segment is partially deformed as shown by a two-dot chain line in the figure, resulting in a distortion of an area shown by oblique lines.

Therefore, an object of the present invention is to propose a filter coefficient changing method that does not cause a large signal distortion even when a filter coefficient calculation process in a DSP is several times or more of a calculation cycle.

[Means for solving the problem]

In view of the above, the filter coefficient changing method according to the present invention, which is devised in view of the above, divides a calculation process for calculating a filter coefficient into a predetermined number (k ₁ ) and executes each divided process a predetermined number of times (k ₀ ). In addition to the above, the present invention is characterized in that the output signal is sequentially executed every time, and an output signal calculated based on the calculation result obtained in the previous calculation cycle is output in a calculation cycle in which the divided processing is executed.

(Operation)

As will be described in detail in the following embodiments, by dividing the filter coefficient calculation processing and executing each divided processing in a distributed manner, the output of a constant value is not continued,
The overall amount of signal distortion is reduced.

〔Example〕

FIG. 1 is a diagram showing an example in which the present invention is applied to an FM / AM radio having a sound quality adjusting function by digital signal processing.

In the figure, an audio signal obtained by tuning, detecting, and amplifying a radio wave received by an antenna in an FM / AM tuner is converted into a digital signal in an analog-to-digital (A / D) converter 702, and various signals are processed in a DSP 610. Digital signal processing, digital-analog (D / A) converter 7
At 04, the signal is returned to an analog signal, the power is amplified by the amplifier 706, and the speaker 708 sounds. The microcomputer 710 has a well-known configuration using a CPU, a ROM, a RAM, and an input / output interface connected to a bus.
A constant for inputting the information of 712 and controlling the sound quality and volume according to the information is transmitted to the DSP 610. The DSP 610 contains various filters and attenuators realized by software processing, and performs arithmetic processing to adjust the sound quality and volume of the input digital signal based on various constants sent from the microcomputer 710. .

A secondary digital filter is shown in the box of the DSP 610 as one of them. This configuration is also well-known. A delay unit 606 that delays an input signal by one sampling period and outputs a primary delay signal, a delay unit 608 that further delays the output and outputs a secondary delay signal, A delay unit 400 for delaying and outputting as a primary feedback signal, a delay unit 402 for further delaying and outputting as a secondary feedback signal, a multiplier 600 for multiplying an input signal by a predetermined coefficient a ₀ and outputting the same, a primary delay A predetermined coefficient a ₁ for the signal
Multiplier 602 and outputting the multiplying secondary delay multiplier 604 the signal output by multiplying a predetermined coefficient a ₂ with respect to the primary feedback signal multiplied by multiplier for outputting a predetermined coefficient b ₁ against vessel 404, the multiplier 406 and outputs the multiplied by a predetermined coefficient b ₂ to the secondary feedback signal, and a multiplier 404,4
It comprises an adder 420 which adds all the outputs of 06, 600, 602 and 604 to produce an output signal.

FIG. 1 shows one digital filter as a representative, but in reality, a plurality of digital filters as shown are connected in parallel or cascade, and the cut-off frequency is , Gain and sharpness Q as parameters.

FIG. 2 is a block diagram showing a hardware configuration of the DSP 610 of FIG. 1 and peripheral circuits attached thereto. The sequence control unit 612 outputs various control signals such as an operation command and a data input / output command according to a software command written in a ROM belonging to the sequence control unit 612. A serial input interface 616 samples and stores serial data 628 input from the A / D converter 702 (FIG. 1) in synchronization with an input / output clock 630, and stores the stored data in a sequence control unit.
The data is transferred to an internal register 614 or the like in accordance with a control signal from the 612, subjected to various types of arithmetic processing, and output as serial data 632 to a D / A converter 704 (FIG. 1) via a serial output interface 624. Is done. The serial input interface 618 is a microcomputer 710 (Fig. 1)
The various data sent from the CPU are taken in as serial data 634 synchronized with the clock 636 and stored in a predetermined address of the RAM 613, and the serial output interface 620
Outputs various data to be sent to the microcomputer 710 as serial data 638 synchronized with the clock 636. Parallel input / output interface 622 has output line 6
1-bit data is output from 42, and 1-bit data is input from an input line 644. A reset input R of a flip-flop 626 external to the DSP 610 is connected to an output line 642, a set input S is connected to a microcomputer via a line 640, and a data output Q is connected to an input line 644. .

FIG. 3 is a flowchart of software for realizing filter operation processing and filter coefficient operation processing in the DSP 610. Among them, the column (1) shows a main routine, and the column (2) shows a subroutine for filter coefficient calculation processing.

First, a reset signal is output through the parallel input / output interface 622 and the line 642 to set the output of the flip-flop 626, that is, CF, to 0 as initial processing,
The constant k ₀ example 10 substituting constant k ₁ for example 4 to CP variable CC (step a). Here, the variable CC is a variable for controlling the interval of the divided processing, and the CP is a variable for controlling the order of the divided processing. Then uptake input data x [i] from the A / D converter 702, for example, performs a filtering operation represented by the formula (2), substituting the y [i] of the result in the variable y ₀ (step b ). Flip-flop 626
If output or CF of 0 (step c), and outputs a y ₀ is terminated (Step d) 1 single calculation cycle.

When an operation of changing the parameter of the parametric equalizer is performed in the key matrix 712 (FIG. 1), the microcomputer 710 (FIG. 1) detects the operation and transfers the parameter to the DSP 610 via the line 643 (FIG. 2). Then, the flip-flop 626 is set via the line 640 as a filter coefficient change request. When it is detected in step b that the flip-flop 626 is set, the variable CC is decremented (step e), and the variable CC is decremented.
Is not negative or 0 (step f) flip-flop
Joins the process when 626 is not set. When a negative or 0, calls a subroutine for the coefficient changing processing (step g), and outputs the value of the variable y ₀ (step h), it returns the value of the variable CC to k ₀ (step i). That CF processing in steps g and h are performed for each calculation cycle k ₀ times if 1, otherwise normal filtering operation is executed. Subsequent to step i, the value of the variable CP is decremented (step j).
Returns the value for k ₁ (Step 1), line 642 (FIG. 2)
(Step m), and a series of filter coefficient calculation processing ends. Thus, the variable CP is assigned the initial value k _1, is decremented subroutine of coefficient updating process for each call. That is, the variable CP represents the stage of the operation to be executed in the coefficient updating means subroutine, and a value of 0 or a negative signifies the end of a series of operations.

When the (2) explaining the processing of the coefficient changing process subroutine shown in the column, the process branches to ₁ kinds k in accordance with the value of the variable CP in first step t. When the value of CP is k1, the _first processing of the coefficient calculation processing is executed. That is, a coefficient calculation process is executed (step n), and the progress of the calculation is stored in the work area (step o). CP value
When k ₁ −1, the coefficient calculation processing subsequent to the coefficient calculation processing is executed (step p), and the result is stored in the work area (step q). When the value of CP becomes 1, the last processing is executed. Then, each coefficient of the filter is rewritten with the operation result (step s).

FIG. 4 is a diagram showing the state of signal processing when k ₀ is 10 and k ₁ is 4. Similarly to FIG. 8, a curve represents an analog signal before A / D conversion, a white circle and a step-like line segment connecting them represent a discrete signal after A / D conversion, and a two-dot chain line represents a filter coefficient calculation. This represents the state of the discrete signal when the processing is executed. Comparing the area of the hatched portion representing the distortion of the signal with FIG. 8, it is understood that the distortion is remarkably small in the system of the present invention.

〔The invention's effect〕

As described above, according to the present invention, a filter capable of reducing signal distortion even when the time required for a filter coefficient calculation process executed inside a DSP is significantly longer than an operation cycle. A coefficient changing method is provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a hardware configuration of the DSP 610 in FIG. 1 and its peripheral circuits, FIG. 3 is a flowchart of software processing in the DSP 610, FIG. FIG. 5 is a schematic diagram showing a state of signal processing in the method of the present invention, FIG. 5 is a diagram showing a secondary digital filter, FIG. 6 is a timing chart showing a first conventional system, and FIG. FIG. 8 is a timing chart showing a conventional system, and FIG. 8 is a schematic diagram showing a state of signal processing in the system of FIG. In the figure, 404,406,600,602,604... Multipliers, 400,402,606,608... Delayers, 420... Adders.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatsugu Uemura Fujitsu Ten Co., Ltd. 1-2-28, Goshodori, Hyogo-ku, Kobe-shi, Hyogo Prefecture (56) References JP-A-64-69115 (JP, A) JP-A-64-8558 (JP, A) JP-A-63-272217 (JP, A) JP-A-59-186414 (JP, A) JP-A-61-193201 (JP, A) JP-A-63-238710 (JP, A) JP, A) JP-A-63-222510 (JP, A) JP-A-61-131910 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 17/00-17/08

Claims (1)

(57) [Claims] 1. A method for changing a filter coefficient of a digital filter for performing a filter operation on an input signal in each of successive operation periods and outputting a result of the operation as an output signal, wherein the filter coefficient is calculated. Is divided into a predetermined number (k ₁ ), and the divided processes are sequentially executed in a predetermined number of (k ₀ ) operation cycles, and in the operation cycle in which the divided processing is executed, A method of changing a filter coefficient of a digital filter, comprising outputting a calculation result obtained in a calculation cycle before the calculation cycle instead of the filter calculation.