JPH05314656A - Over sampling digital filter - Google Patents

Abstract

PURPOSE:To provide an over sampling digital filter unnecessary for raising an operation speed even at a double speed mode time. CONSTITUTION:In the case of a normal speed mode, programs A, B, C are executed successively. Thus, the over sampling of 2X2X2=8 times is realized. In the case of the double speed mode (where 2 times speed), a system clock is not revised and only the programs A, B are executed. Since the execution time of a first program is 1/2 of the sum execution time of the first, a second programs, is executed at a double speed. Then, the over sampling equal to 8 times is executed substantially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to oversampling digital audio used for digital audio and the like.
The present invention relates to a filter, and particularly to simplification of its configuration.

[0002]

2. Description of the Related Art In digital signal processing such as CD, in order to convert an analog signal and a digital signal,
An A / D conversion circuit and a D / A conversion circuit are required. Figure 5
The configuration of the D / A conversion circuit is shown in FIG. This D / A conversion circuit includes a D / A converter 2 and an analog LPF 4.
When the digital signal sampled at the frequency F _S is given to the D / A converter 2, an analog signal is output. The spectrum of this analog signal is shown in FIG. 6, and harmonics are generated around the frequency n times F _S.
An analog LPF 4 is provided to remove these harmonics. The characteristic of this analog LPF4 is F _S /
It is necessary to make a sharp fall near 2 (see α in FIG. 6).

By the way, it is difficult to obtain the analog LPF 4 having the characteristics shown by α in FIG. Therefore, as shown in FIG. 7, the oversampling filter 6 (digital filter) is provided before the D / A converter 2. The oversampling filter 6 performs sampling at a frequency eight times F _S (oversampling). Therefore,
As shown in FIG. 8, no harmonic appears until the frequency of 8F _S. Therefore, the characteristics of the analog LPF 4 can be made gentle as shown by β in FIG. That is, the characteristics required for the analog LPF 4 can be made gentle.

As described above, the load on the analog LPF 4 is reduced by using the oversampling filter 6.

Some digital audio devices such as CDs have a function of reproducing at a speed twice as high as the normal speed (called a double speed mode). When reproducing in such a double speed mode, the frequency of the system clock is doubled so that the entire device operates at double speed. Therefore, the operating speed of the above oversampling filter 6 is also doubled.

[0006]

However, the above-described conventional oversampling digital filter has the following problems.

Since the oversampling digital filter performs oversampling operation,
High-speed operation is required as compared with other parts. Furthermore, in the double speed mode, an operating speed twice as high as that is required, which is even more so. High-speed operation oversampling digital filters are difficult to design and manufacture, and have hindered cost reduction of equipment.

An object of the present invention is to solve the above problems and to provide an oversampling digital filter which does not need to increase the operating speed even in the double speed mode.

[0009]

An oversampling digital filter according to the present invention divides a program for controlling the operation into a first program for basic multiple oversampling and a second program for predetermined multiple oversampling. By making the ratio of the execution time of the first program to the total execution time of the first program and the second program 1 / predetermined times, and by executing the first program and the second program continuously in the normal speed mode, In the double speed mode, oversampling of basic times x predetermined times is performed, and in the double speed mode, only the first program for performing basic sampling oversampling is executed by the operation clock having the same frequency as in the normal speed mode, thereby substantially reducing It is characterized in that oversampling of a predetermined number of times is performed.

[0010]

In the normal speed mode, the first program and the second program are continuously executed. Since the first program performs oversampling at the basic multiple, and the second program performs oversampling at a predetermined multiple, the basic multiple ×
A predetermined multiple of oversampling will be performed.

In the double speed mode, only the first program is executed by the operation clock having the same frequency as in the normal speed mode. The first program is to perform oversampling of the basic multiple. The execution time of the first program is 1 / predetermined times of the total execution time of the first program and the second program. Therefore, the sampling is performed at a predetermined multiple of the sampling performed in the normal speed mode. In other words, the oversampling of the basic multiple × the predetermined multiple is substantially realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the principle of a general oversampling digital filter. A digital input is applied to the terminal 10. This digital data is sequentially delayed by the delay circuits Z _{0 to} Z _n-1 . The delay time of each delay circuit Z _{0 to} Z _n-1 is determined by the sampling frequency. The outputs from the delay circuits Z _{0 to} Z _n-1 are multiplied by the coefficients by the multipliers H _{0 to} H _n , respectively. The multiplication results are added in the adder 12 and output from the terminal 14 as a digital output.

For example, when 8 times oversampling is performed, three circuits as shown in FIG. 2 for performing 2 times oversampling are prepared. These are connected in series to realize 8 times oversampling.

An example of realizing the circuit of FIG. 2 is shown in FIG.
In this example, by the program of the control circuit 34,
Each part is controlled. Digital data is given from the terminal 10. This is a command from the control circuit 34.
It is stored at a predetermined address in the RAM 20. Next, the control circuit 34 reads the input data from the RAM 20 and gives it to the multiplier 28. At the same time, the coefficient is read from the ROM 26 and given to the multiplier 28. The multiplier 28 multiplies both data and gives it to the adder 30.

Next, the control circuit 34 reads the previous input data stored in the RAM 20, and the multiplier 28
Give to. At the same time, the coefficient is read from the ROM 26 and given to the multiplier 28. The multiplier 28 multiplies both data and gives it to the adder 30.

After repeating the above operation, the adder 3
Output data is obtained from 0 through the latch 32.
That is, the same operation as the principle diagram of FIG. 2 is performed.

When 8 times oversampling is performed, it is realized by repeating 2 times oversampling three times.

In this embodiment, the program of the control circuit 34 is constructed as shown in FIG. That is, the first program, program A and program B
And a program C which is a second program. The execution times of the first program (programs A and B) are
The number of steps and the like are adjusted so that the total execution time of (B, C) is 1/2. The first program performs oversampling of 4 times, which is a basic multiple, and the second program performs oversampling of 2 times, which is a predetermined multiple.

In the normal speed mode, the programs A, B and C are executed in sequence. Therefore, 2 × 2 × 2 =
Eight times oversampling can be realized.

In the case of the double speed mode (double speed in this case), the system clock is not changed and the program A,
Execute only B. Therefore, in terms of the program, 2 ×
2 = 4 times oversampling is performed. However, since the execution time of the first program is ½ of the total execution time of the first and second programs, it will be executed at twice the speed. For this reason, it is substantially equal to 8 times oversampling.

With the above arrangement, the double speed mode can be realized without increasing the system clock speed.

In the above embodiment, the case of the double speed mode of double speed has been described, but the present invention can also be applied to the double speed mode of K double speed. In the K-speed mode, as shown in FIG. 4, the execution time of the first program F is 1 / of the total execution time of the first and second programs.
You can set it to K.

In the above embodiment, the circuit as shown in FIG. 3 is used, but it may be realized by software.

[0024]

In the oversampling digital filter according to the present invention, the program for controlling the operation is divided into the first program of basic multiple oversampling and the second program of predetermined multiple oversampling.
The ratio of the execution time of the first program to the total execution time of the program and the second program is set to 1 / predetermined times, and in the normal speed mode, the first program and the second program are executed.
Only the first program that performs oversampling of the basic multiple by executing the program continuously and performing oversampling of the basic multiple × a predetermined multiple, and in the double speed mode, using the operating clock of the same frequency as in the normal speed mode. I'm trying to do. Therefore, the double speed mode can be realized without increasing the operation clock.

That is, according to the present invention, it is possible to provide an oversampling digital filter which does not require an increase in operating speed even in the double speed mode.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a control program for an oversampling digital filter according to an embodiment of the present invention.

FIG. 2 is a diagram showing the principle of an oversampling digital filter.

FIG. 3 is a diagram showing a hardware configuration of an oversampling digital filter.

FIG. 4 is a diagram showing the configuration of a control program for an oversampling digital filter according to another embodiment.

FIG. 5 is a diagram showing an example of a D / A conversion circuit.

FIG. 6 is a diagram showing characteristics of the circuit of FIG.

FIG. 7: D / with oversampling filter 6
It is a figure which shows an example of an A conversion circuit.

FIG. 8 is a diagram showing characteristics of the circuit of FIG. 7.

[Explanation of symbols]

 A, B ... First program C ... Second program

Claims (1)

[Claims] 1. A program-controlled oversampling digital filter for use in a recording or reproducing device having a normal speed mode and a double speed mode which is a predetermined multiple of the normal speed. The program and a second program with a predetermined multiple oversampling are divided, and the ratio of the execution time of the first program to the total execution time of the first program and the second program is 1 /
In addition to the predetermined speed, in the normal speed mode, the first program and the second program are continuously executed to perform oversampling of basic times × predetermined times. An oversampling digital signal characterized by performing substantially a basic multiple × a predetermined multiple of oversampling by executing only a first program that performs basic multiple oversampling with an operating clock of the same frequency.
filter.