JPS63103509A - Digital filter - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the dynamic range due to re- quantization by expanding the data word length at the data transfer from the pre-stage to the post-stage of oversampling filters connected in cascade more than input/output data word length. CONSTITUTION:The data word length of a 1st oversampling filter 6a output is expanded by several bits in comparison with the data word length fed to the input of the 1st oversampling filter 6a of the pre-stage and the word length of the output data of a 2nd oversampling filter 6b is made equal to the data word length inputted to the 1st oversampling filter 6a. Thus, the deterioration in the dynamic range caused at re-quantization at the transfer of the word length from the sampling filter 6a of the pre-stage to the sampling filter 6b of the post-stage is reduced very economically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter, and particularly to an improvement of a filter in which oversampling filters are connected in cascade.

[Summary of the invention]

In a digital filter formed by cascading a plurality of oversampling filters, the present invention extends the data word length when passing data from the previous stage to the subsequent stage of the cascaded oversampling filters from the human output data word length. This is to prevent the Dynamin Cleaner from deteriorating due to the use of centenarians.

[Conventional technology]

In audio circuits used in conventional CD (compact disc) players, when playing back PCM (pulse code modified M) data from a CD, a digital signal processing system performs processing such as data demodulation and error correction. Add the digital signal with the sampling frequency fs = 44.1Kl + 7° to the digital filter, and double or 4 fs.
Oversampled twice, 2fS=88.2KII
z, 4fs = 176.4KIIz digital signal, in addition to D/A (digital-analog conversion 'a),
The signal is output to a decritch circuit, an LPF (low-pass filter), and a de-emphasis circuit 112 via an amplifier. Such a digital filter is provided in the front stage of the D/A, and the analog 1. , P
A configuration designed to lighten the burden on F was published in Japanese Patent Application Laid-Open No. 59-17.
It is disclosed in Japanese Patent No. 4018 and was publicly known one day before the filing of the present application.

The basic configuration of an oversampling filter for constructing a digital filter will be explained with reference to FIG.

The oversampling filter changes the sampling frequency to 04& based on digital processing, and its circuit configuration is a J1 cyclic type in which the impulse response lasts for 1q.
<Finny +1 Impulse L Sponse>:P
IR) filter and a cyclic type (1nNniLe 1lllpulse respo) whose impulse response is infinite length.
nse <Infinite Impulse Response>
:IIR) Be classified into filters.

The first edge shows an oversampling filter of the f'lR type filter. Digital manual data from the digital processing circuit is input to the input terminal (1), and a switch consisting of fixed contacts S and C and a movable contact A is input. (2) Fixed contact a
added to. Fixed contact C has a “0” data generation circuit (
7) is given. The switch (2)'s contact a is connected to a plurality of cascaded slow 5G devices, for example,
The digital data taken out from the respective output lines of the cascaded delay devices (3) connected to the V shift register (3) are added to a plurality of multipliers (4) respectively, and JV is calculated by a constant coefficient K.
The output of this multiplier (4) is added to the adder (5).

Input Mgi f (11, for example, set "0" of (n-1)l1711 to "0" in the middle of the playback data transferred at a rate of sampling frequency fs = 44.1KIlz)
The nfs output data is extracted from the adder (5) by inserting it at the data generation time 1/1lff7) and multiplying the sampling frequency by one. FIG. 5 shows, for example, a first oversampling filter (6a) that doubles the sampling frequency fs to 2fs and a second oversampling filter (6a) that doubles the sampling frequency fs to 4fs in a sampling filter configured as described above. It shows a system diagram of a digital filter (8) in which a sampling filter (6b) is connected in cascade.

The digital data word length M applied to the input terminal (11) is normally M = 16 bits, which is input to the first oversampling filter (6a), which changes the sampling frequency fs = 44.1KHz to 2fs = 88.2KHz. The signal is doubled and passed to the second oversampling link filter (6b) with a word length of M = 16 bits, and the second oversampling filter (6b) has a word length of 2fs = 88.2K.
The Hz is doubled to 4fs = 176.4KHz, and outputted to the next stage D/A (91) with a word length of M = Hi-Bift. ] After this L P F
T-filtered.

[Problem that the invention seeks to solve]

The conventional digital filter shown in Fig. 5 of Ototo is effective in that it can reduce the number of calculations;
f & from the first sampling filter (6a) in the previous stage
When data having a word length of 16 bits is transferred to the second sampling filter (6b) of h'l, there is a problem in that the dynamic range deteriorates due to the effect of requantization.

As shown in Figure 5, the dynamic range degradation in the case of a 4fs digital filter with n-4 is 3.5 dB.
)/ko.

The present invention has been made in view of the above-mentioned drawbacks, and its object is to provide a digital filter that does not cause deterioration in dynamic range.

(Means for Solving the Problems) The present invention provides a digital filter means in which a plurality of oversampling filters are connected in cascade, and the data S% lit at the time of data transfer from the previous stage to the subsequent stage is extended from the human output data word length. It provides:

(Function) The digital filter of the present invention expands the data word length of the first oversampling filter output by several bits compared to the data word length added to the human power of the first oversampling filter (6a) in the previous stage, and In addition to the oversampling filter (6b), the length of the output data of the second oversampling filter (6b) to a is made equal to the data word length manually input to the first oversampling filter (6a), thereby increasing the dynamic range. Deterioration can be reduced economically.

〔Example〕

Hereinafter, one embodiment of the digital filter of the present invention will be described in detail with reference to FIGS. 1 to 3. FIG. 1 shows a practical embodiment of a digital filter according to the present invention, which will be described below. In FIG. 1, the circuit configurations of the first and second oversampling filters (6a) and (6b) are approximately the same as the oversampling filter shown in FIG. M=16-bit digital data (sampling frequency fs=44.1KIIy) outputted from a digital signal processing circuit or the like is manually input to terminal (1). When digital audio data consisting of left and right channels of stereo L/O is sampled with fs = 44.1 revision 1y, as shown in Figure 3A, in addition to the original signal (IO), fs, 2fs, 3fs,
Fundamental wave centered at 4fs=. and odd and even harmonics (11), (12), (13), (14)...
occurs. These harmonics (11), (12), (1
3) In order to filter the (eyes), as shown in Figure 3B, an 83rd-order first oversampling filter (
6a) creates the fundamental wave (44,1K117: ) (
11) and the third harmonic (44,]K)! ZX 3)
It eliminates the odd-order IN'Ii IfH1 wave of (13) and is connected to the previous [y's first step]\sampling filter (6a) with a dark blue ribbon. & When passing the digital data to the 20th oversampling filter (6b) in the & stage, M + N, t, and a? Expand iKt. In the 4fs digital filter for CD, M-16 bits, N = 2 bits, a total of 18 bits, and the second oversampling filter (6h) of 2.21st order,
2nd harmonic (44.1KHz x 2
) Even-order crystal δI of (12)! , to eliminate leakage. Here, the fourth harmonic (44,1KI (zX4)
(14) is digital-to-analog converted and is added later as shown by the broken line (15) in the third diagram. L for 1g
Since it is eliminated by the frequency characteristics of PF, it is not removed here.

That is, the first and second oversampling filters (6
8) and (6b), the fundamental wave and the second and third harmonics are attenuated or eliminated as shown in the third diagram, and from the second oversampling filter, M=1
D/A (input to 01) with a word length of 6 bits.

As mentioned above, the amount of deterioration in the dynamic range when N = 2 bits and 18 bits for human data M-16 bits is 2 dB, compared to when N = 0. An improvement of 2.3 dR was achieved. When two stages of sampling filters are connected in cascade and the word length extension bit is increased by 1 bit with N=1 (7), the amount of deterioration of the dynamic range is 1.8 dB, which is an improvement of 1.7 dB compared to when N=O. , and the receiving and passing data word jHN is 3
Even if the number of bits is expanded, the degree of improvement is small, and the degree of improvement is small even though the scale of the hardware is increased.N-2 is preferable for two-stage cascade connection. In general, the ratio of quantization noise to the maximum sound of a signal, that is, the maximum dynamic range D
If the number of nine children is M bits, then D = 6 x M + 1.76dB and M = 16
If the number of bits is 97.76dB, increasing the number of bits will improve the dynamic range, but what kind of expansion '6? The choice of fR depends on the economic effect required for the filter's hard rule of 1ψ, and it has been found that N=2 is most preferable for an RIF type filter in which two stages of oversampling filters are connected in cascade. In the example of Figure 1, the first and second oversampling filters (
6a) and (6b) are connected in cascade in two stages, or
It is also possible to vertically connect three stages of oversampling filters with Vt, and in this case, it is preferable that the extended word length is N>3 bits.If E L < N = 2, N in the case of two stages cascade connection is possible. = 1, the degree of improvement in the deterioration m of the dynamic range D is small.In the extended word length, the data transfer from the first to the 20th oversampling filter is extended by 1 bit, and Although it is possible to extend the data by 2 bits when passing the data to the filter, it is possible to extend the data by 3 bits when passing the data from the second to the 30th oversampling filters.

FIG. 2 shows another embodiment of the digital filter IC (16) according to the present invention, which will be described below.

In Figure 2, T1 to Ty indicate the input/output terminals of the IC. Digital data is serially input from the input terminal T1 to the input circuit (17), and the serial data is converted into parallel data through a serial-parallel conversion circuit. It is converted into data and applied to the fixed contacts of the switching means (18). The switching means (1B) includes a fixed contact (c) and a movable contact (a), but this switching means may be an electronic switch, and a memory (RAM) for storing data through one switching path b-a. ) (19) is done manually. This data RAM (19) is the data RAM for the 83rd order.
(19;i) and a data RAM (19b) for the 21st order, and the outputs of these data RAMs are applied to a multiplier/achiemulator (24) similar to that described in FIG. This multiplier/accumulator (24) has a coefficient ROM (20
) to the coefficient from! , K2 are input to an accumulator in the multiplier (24). The coefficient ROM (20) also includes coefficient ROMs (20a) and (20b) for the 83rd order and the 21st order. The coefficient ROM (20) has a frequency dispersion of 11 [rdi
1, K? for the coefficient of the second type 1n depending on whether it is positive or not. Row is Jrl
Coefficient switching signals (20c,
The multiplier/accumulator (24) has input terminals T s and TG, and the coefficient is stored in the ROM (20) to change the number of threads. An offset signal (4a) for offset y) is input manually, and a zero level ±1% offset signal (4b) is applied to the input terminal rT.

The output of the multiplication circuit/accumulator (24) is applied as a parallel output to an overload limiter (21), overshoot is suppressed, and the output is applied to an output circuit (22).

The output of the overload limiter (21) is the line (23
) through the other switching path c of the switching means (18)
-e It is connected to the data RAM (19) via a.

The input terminal T7 of the output circuit (22) has M bits/M+N.
A bit cut signal (22a) is added.

The output terminal of the output circuit (22) has a terminal to which, in addition to M-bit data, a pit clock, a word clock, a left/right signal clock, a left/right aperture clock, etc. are output (not shown).

In the cooking configuration, when performing the function as a digital filter, the switching means (18) is in contact with one switching path a-b side, and M-bit digital (actually 16-bit) data is multiplied. The data RA has been corrected in the previous process using the
In order to perform 83rd-order filtering on the data stored in M(19), the output of the 83rd-order RAM (19a) is multiplied by ``a(24)'' and the coefficient 1? 83 of OM(20)
Multiply one column of coefficients from the next ROM (20a) by this data column, and multiply the left and right (22 times each for No. 3 l7 and R, 44 times in total), and convert this output into M bits (16 bits).
For the human data of
Add to 1).

As a result, filtering as shown in FIG. 3B is performed.

The result of such multiplication is sent to data RA through the line (23) and other switching channels i/3cma of each switch hand (18).
In addition to M(19), the 21st order RAM (19a) output is added to the multiplier/accumulator (24) to obtain the coefficient I? O
Multiplication is performed again with the coefficient string stored in the 21st order coefficient ROM (21b) of M(20). This multiplication is performed 22 times for each R data signal, a total of 44 times. At this time, the output of the multiplier/accumulator (24) is that for the input of M+N bits (18 bits), the upper M bits of the M+N bits are output as M bits (16 bits).
It is output to the output terminal T2 through the overload limiter (21) and the output circuit (22). However, output terminal (T7)
M bit to / M +N bit switching signal (22a)
M bez) < 16 bits) or M+N bits (
(18 bits) can be output.

M+W ′a for cooking and accumulator (24) are “
0” Data generation circuit (7) function and word length extension function a
9 during 22p3, which is one cycle of CD data.
Six multiplications are also possible.

As a result, filtering as shown in FIG. 3C is performed, and data having characteristics as shown in FIG. 3 is output from the output circuit (22). # is received. The output terminal T is then passed through the overload limiter (21) and the output circuit (22).
Data is output to 2, and the D/A (converted from 91 to analog stage and 5υ) in Figure 1 is 1, P
The fourth frequency harmonic component (1
4) is removed.

Although the present invention has been described in detail regarding the FIR type filter in cooking, it is also possible to use an IIR type filter. RAM, ROM, history! It is clear that the present invention can be used in a digital equalizer using a filter using a calculator, an echo device, or the like.

〔Effect of the invention〕

Since the present invention is constructed in a similar manner, the transfer of the word length from the sampling filter in the preceding stage to the sampling filter in the succeeding stage has the effect of extremely economically reducing the deterioration of the dynamic range caused by requantization at the time of transfer. .

[Brief explanation of the drawing]

FIG. 1 is a system diagram of one embodiment of the digital filter according to the present invention, FIG. 2 is a system diagram of another embodiment of the digital filter according to the present invention; FIG. 4 is a basic configuration diagram of a conventional oversampling filter, and FIG. 5 is a system diagram of a conventional digital filter. (68) and (6b) are the first and second oversampling filters, (8) is the digital filter, and (9) is the D/
A, (19) is data RAM, (20) is coefficient ROM,
(24) is a multiplier/accumulator.

Claims (1)

[Claims] In a digital filter consisting of a plurality of oversampling filters connected in cascade, the data word length when passing data from the preceding stage to the succeeding stage of the cascaded oversampling filters is extended from the input/output data word length. A digital filter that is characterized by: