JPH02149011A - Sampling frequency converting device - Google Patents

Abstract

PURPOSE:To attain the frequency conversion of a high degrees of freedom by providing a coefficient storage device to store a coefficient group to be given to each multiplier, an adder to add multiplied result and a device to change a coefficient to be given to each multiplier according to the contents of the coefficient storage device, and changing periodically the coefficient of the multiplier. CONSTITUTION:Signals x(n) inputted from an input terminal are held in a D- latch 2 by turns. The coefficients K0, K1, K2...K6 are given to a multiplier group 3 respectively by a multiplication coefficient table 8. The coefficients as shown in a figure are prepared in the multiplication coefficient table 8. The coefficients h( ) of each vertical row are set in the respective multipliers 3. A counter 7 is up-counted by an input clock xck, and outputs an address signal to the multiplication coefficient table 8, and simultaneously, outputs a clock wck for setting the multiplied result in the D latch 5. The clock yck is the read clock of 37.8KHz, and calculated result is read out by turns, and x'(n') is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a sampling frequency conversion device that converts the sampling frequency of a digital signal such as a PCM signal.

(Prior Art) Digital audio has become popular in recent years. The mainstream is PCM (Pulse Code Modula
tion)' method. In this method, if the sampling frequencies are different, the data will not be compatible and the pitch of the music will change. Therefore, it is often the case that the A/D conversion is performed again after the signal is once returned to an analog signal within the film. Although this method is easy and causes relatively little deterioration in sound quality, it is difficult to control noise, waveform distortion, etc.

Therefore, it is conceivable to convert the sampling frequency of the digital signal as it is. The following will explain based on the drawings.

For example, from 44.1KHz to 6/7 of that, 37.8KI
Consider the conversion of the sampling frequency to Iz. Since aliasing noise may occur in this conversion, it is clear that frequency components of 37.8 KIIz or higher must be removed by a filter. The frequency characteristics of this filter H(ω) are shown in FIG. Let h (n) be the impulse response of this filter H(ω), that is, the response representation in the time domain (FIG. 11).

The PCM data (44,1KHz) that becomes the original signal is x (
n) (Figure 12). FIG. 12 shows the expression X(ω) of this PCM data x (n) in the frequency domain.

As can be seen from FIG. 13, it includes components up to around 22 KHz. Insert 5 zero data between this original signal and increase the sampling frequency x (m) by 6 times (14th
figure). By this operation, the spectrum of both signals, that is, the expression X(ω) in the frequency domain, becomes the first
As shown in FIGS. 3 and 15, they are completely the same and do not change. This sequence X(m) has a sampling frequency of 44.1x
B-264,8 (Kl12〉) Also, x (m)
It can be understood from FIG. 14 that is all zero except when m-61 (i is an integer).

If we continue to create data by thinning out x (m) every 7 times and forcibly sampling it at 37.8 Kllz, aliasing components will occur and the signal will be very different from the original signal as shown in Figure 19, resulting in a normal signal. It can't be the sound quality. Therefore, in order to eliminate this aliasing, x (m
) is passed through the above-mentioned filter H(ω) (FIG. 9) whose band is limited to 37.8 KHz. This filter calculation is performed at a frequency of 284.8 KHz, which is six times the original frequency.

The impulse response h (t) of this H(ω) is 284.8
If h (m) is sampled at KHz, then (
(Fig. 11), the signal x' (m) after passing through the filter becomes as shown in Fig. 16.

This signal x' (m) is given by the following equation.

x'(m)sw Σ h (i) ・ x (
m-i)1- + (3) In other words, it is given by the sum of the products of two numerical sequences. This signal x
'(m)'s frequency domain representation X'(ω) is the 17th
As shown in the figure, it does not contain components of 37.8Kllz or higher. Further, as shown in FIG. 20, a component appears near an integral multiple of 2[i4.0KIIZ. Since the target signal has a sampling frequency of 37.8KHz, it can be easily obtained by resampling the data of x' (m) with a sampling frequency of 284.6KHz every 7 times (resampling at 37.8K)lz). (Figure 18).

The frequency domain representation of this signal is as shown in FIG. 21, and it can be seen that no aliasing occurs. As a result, 44
．． This means that the conversion of the sampling frequency from 1 KHz to 37.8 KHz has been completed.

That is, after oversampling to a common multiple of the two sampling frequencies, the signal can be converted to any frequency by passing it through a filter to prevent aliasing noise. However, if the two sampling frequencies are relatively prime, the least common multiple becomes extremely large, which is not realistic.

FIG. 9 is a block diagram of the configuration for realizing the above-described operation.

A PCM signal is input from the input terminal 21. A 264.8 KHz clock is also input from the clock input terminal.

The latch group 23 generates a delay of 2B4.6KIlzl clocks. The input data string is sent to the multiplier group 24
After each coefficient KO~ is multiplied by 7, adder 2
5 and stored in the latch 26 for output. on the other hand,
Output clock yck (7) Data y is read at a cycle of 37.8Kllz, resulting in the desired 37.8Klz
PCM data of lz is obtained.

(Problems to be Solved by the Invention) As is clear from the above-described example, in the conventional sampling frequency conversion device, the product-sum operation must be performed at a frequency that is the least common multiple of the frequencies before and after conversion. Therefore, there were problems in that a high-speed multiplier was required and there were large restrictions on input and output frequencies.

An object of the present invention is to provide a sampling frequency conversion device that achieves frequency conversion with a high degree of freedom using a relatively low-speed multiplier.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the sampling frequency conversion device of the present invention includes a plurality of devices that store input data, and a method for multiplying the input data by a predetermined coefficient. a plurality of multipliers, a coefficient storage device that stores a group of coefficients to be given to the multiplier, an adder that adds the multiplication results, and a coefficient given to each multiplier that is changed by the contents of the coefficient storage device. and a device for periodically changing the coefficients of the multiplier.

(Function) The coefficients are changed every time the product-sum operation is performed, and as a result, only the data after resampling is finally calculated. Therefore, there is no waste, and the frequency of the product-sum operation is at most the sampling frequency of the original signal.

(Example) FIG. 1 shows six times oversampled data obtained by interpolating 0 data to data (original data) with a sampling frequency of 44.1 KHz. Let this be x (n). For this data x (n), the original data is x (6i)
(i is an integer).

This data is passed through a filter H(ω) before lowering the sampling frequency to 37.8 KIIz.

In FIG. 2, h (n) is the representation of the filter H(ω) in the time domain, that is, the impulse response of H(ω). When a signal x (n) is input to this filter H(ω) and the output is x' (n) (FIG. 3), the following equation holds true.

x' (n) −x (n) *h (n
) dawn Σ x (t) ・ h(n-1)1°--
...(1) Here, * indicates a convolution operation, and i indicates an integer.

By the way, it is clear from the m1 diagram that X (n) = fO (n≠6i, i is an integer), so x' (n) −Σ
(2) 1-1 ■ holds true.

Furthermore, in order to ultimately thin out to 37.8Kllz, the necessary data is every 7 pieces, where n-7j j is an integer, x' (7j) - Σx (6i) ・h (7, 1-6i) 1 -1 A flash of inspiration takes place.

This x' (7j) is the required 37.8 KHz data (Figure 4).

The term x(6i) in equation (3) is the 44.1KHz data itself, and h(7j-6i) is h(n
) is the data for every 6 samples. It is clear that X'(7j) is the sum of the products of both.

In general, h (n) truncates data at a finite length, and n>IM
Since I h(n)-0, x' (7j) 1 Σ x (6i) ・ h (7j 6
1) l"-H...(4)

A block diagram of a sampling frequency conversion device that realizes the above operation is shown in FIG.

In the figure, 1 is an input terminal, 2 is a D latch, and 7 is a latch.
is a counter, 8 is a multiplication coefficient table, and 9 is an output terminal.

D latch 2 receives a signal x (n
) are held sequentially. The multiplier group 3 is given coefficients KO, Kl, 2...K6 from the multiplication coefficient table 8, respectively.

The multiplication coefficient table 8 includes coefficients as shown in FIG. The coefficient h U of each column is set in the respective multiplier 3 .

The counter 7 is counted up by the input clock xck and outputs an address signal to the multiplication coefficient table 8, and at the same time outputs a clock wck for setting the multiplication result in the D latch 5.

yck is a read clock of 37.8Kilz,
The calculation results are sequentially read out to obtain X'(n').

FIG. 6 is a timing chart of xckSwck and yck.

The operation of this embodiment will be explained below based on FIGS. 5 to 8.

Now, latch 2 has x (0), x (1
), x (2), x (3), x (4), x
(5) is held.

At this time, KO, K1 . 2. 3. 4.
5. and 8 are the coefficients h(
0), h (6), h (12), h (18)
, h (24), h (30), and h (36) are set, respectively. This coefficient h U is the numerical sequence in Fig. 2, that is, the time domain representation h (
n).

When data x(6) is input from input terminal 1 at clock xck of 44.1K)lz, multiplier 3 and adder 4 perform sum-of-products calculation, and data x is input to D latch 5 for output at clock wck. ' (0) is set. That is, x' (
0) is x' (0) −K(l x (0)+Ki x (1)+Ki x
(2) 3・x to 10 (3) 4−x to + (4) 5・x to + (5) +k13φx(6) −h (0) ・X +h(12) +h (24) +h (36) (0) +h (6) ・X (1)・x
(2) +h (18) ・X (3)-x
(4) +h (30) ・x (5)
・ x (6) ■ Σ x IL) ・ h(6i).

This is expressed as (n<0 6
It can be seen that h (n) - 0 for <n). (Note that x(i) is 44.1 KHz data).

Next, when x (7) is input, KO of multiplier group 3,
1. 2. 3. 4. 5. and 6 and 7 respectively.
The value in the second column of the diagram is set. Then, a sum-of-products calculation is performed. x' (1) is (blank below) x' (1) -h (1) ・x (1) +h (7)
・x (2)+h (1B) ・x (3) 10h (19) ・x (4)+h (25) ・
x (5) + h (31) x (6) 10 h (37) x (7).

After performing the above operation 6 times, at the 7th column in Figure 7,
Data X(6) is set in latch 2 by clock xck, but wck is not output at this time. Therefore, the data in the output latch retains the previous value.

Next, when data x (8) is input, multiplier 3KO receives 1. 2. 3. 4. 5. and 6 respectively h (
0) , h (6) , h (12) , h (18)
, h (24), h (30) and h (36) are set, returning to the initial state and repeating the above operation.

In this way, x' (n) is calculated sequentially and the output D
Since it is set to latch 5, this result is 37.8KH.
Data is obtained by periodically relatching with the clock yak of z.

A flowchart describing the above operation is shown in FIG.

[Effects of the Invention] As explained above, the sampling frequency conversion device of the present invention includes a coefficient storage device that stores a group of coefficients to be given to the multiplier, and a coefficient storage device that changes the coefficients given to each multiplier by the contents of the coefficient storage device. By periodically changing the coefficients of the multiplier, the number of product-sum calculations can be reduced to 1/7 compared to conventional devices, so a high-speed multiplier is not required.

Furthermore, even if the least common multiple of the sampling frequencies of the input/output data becomes larger, the cycle in which calculations are executed will not become shorter than the sampling cycle of the input/output signals. The only increase is the coefficient table required for filter calculations, which is no longer a big burden these days as RAMSROMs have become larger in capacity.

Therefore, free sampling frequency conversion can be achieved using a relatively slow multiplier.

[Brief explanation of the drawing]

Figures 1 and 14 show data obtained by increasing the sampling frequency by 6 times, Figures 2 and 11 show the impulse response of the filter, and Figures 3 and 16 show data after passing through the filter. FIG. 4 and FIG. 18 are diagrams showing the target sampling frequency signal, FIG. 5 is a block diagram of a sampling frequency conversion device according to an embodiment of the present invention, and FIG. 6 explains the operation. Timing chart diagram, Figure 8 shows a coefficient table, Figure 7 is a flowchart of arithmetic processing of sampling frequency conversion, Figure 9 is a block diagram of a conventional sampling frequency conversion device, and Figure 10 shows filter characteristics. Figure 12 shows the input original data, Figure 13 shows the spectrum of the original data, Figure 15 shows the spectrum of the data shown in Figure 14, Figures 17 and 20. is a diagram showing the spectrum of the data shown in Figure 16, Figure 19 is a diagram showing the spectrum when the data shown in Figure 14 is sampled again, and Figure 21 is a diagram showing the spectrum of the data shown in Figure 18. be. 1... Input terminal, 2... Latch, 3... Multiplier,
4... Adder, 5... Latch, 6... Counter,
7... Coefficient memory, 8... Output terminal.

Claims (1)

[Claims] A plurality of devices that store input data, a plurality of multipliers that multiply the input data by predetermined coefficients, and a coefficient storage device that stores a group of coefficients to be applied to each multiplier. and an adder for adding the multiplication results, and a device for changing the coefficients given to each multiplier by the contents of the coefficient storage device, characterized in that the coefficients of the multipliers are changed periodically. Sampling frequency conversion device.