JPS62105518A - Digital filter - Google Patents

Abstract

PURPOSE:To perform a double-precision arithmetic with the coefficient of single precision and to perform a fast arithmetic with a small-scale circuit constitution by dividing a multiplier coefficient sequence corresponding to the impulse response of a filter into a large-coefficient and small-coefficient parts, and performing the double-precision arithmetic for only the large-coefficient part by partial product arithmetic. CONSTITUTION:The clock of a multiplier between the number N of filters and the frequency of a sample sequence is counted by the counter 6 of a digital filter and applied as an address to a ROM 2, and a series of coefficients is read out and applied to a multiplier 3. Further, a counter 8 counts the clock of frequency fs and applies it to an adder 7 together with the address of the ROM 2, and a data sequence corresponding to the processing of each delay stage is readout with its output and applied to the multiplier 3. The multiplication result of this multiplier 3 is accumulated by accumulator 5 through an adder 4. A part of the accumulation result is fed back to an adder 4 through a shifter 9 and the sum of products is calculated by convolution, etc., to simplifying the circuit constitution, thereby performing fast arithmetic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital filters, particularly acyclic type (FIR) filters.
This is a type of digital filter that can efficiently perform double-precision arithmetic.

[Summary of the invention]

Double-precision arithmetic is performed only on the part where the coefficient value of the multiplication coefficient sequence corresponding to the impulse response of the filter is large, thereby reducing the capacity of the coefficient memory and reducing the size of the multiplier to increase processing speed and achieve high precision. This enables highly efficient digital signal processing.

[Conventional technology]

In digital signal processing systems, the sampling rate of PCM data handled by the system is increased several times before D/A
Or A/D may be used, which is called oversampling. In such processing systems, FIR type digital filters having low-pass characteristics are often used for interpolation or thinning data processing. In general, in an FIR digital filter, the larger the next stage (number of stages), the better the cutoff characteristic (steepness), the attenuation amount in the stop band, and the ripple characteristic. However, in actual digital filter calculation hardware, the word length of the multiplication coefficient is limited, so it is difficult to achieve theoretical values such as the amount of attenuation.

FIG. 9 is a characteristic diagram of the amount of attenuation for the next stage of the filter, which exhibits a drooping characteristic in which the amount of attenuation increases as the order is amplified. For example, in a 96th order 2x oversampling filter,
Theoretically, an attenuation of 90 dB can be obtained. However, if the coefficient word length is rounded to 16 bits, only 80 dB of attenuation is obtained. To obtain 90 dB requires 18 bits of accuracy.

[Problem that the invention seeks to solve]

The circuit scale of a multiplier used in a digital filter is approximately proportional to the product X-Y of the word length Y of the PCM data to be handled and the word length X of the coefficients. If the circuit scale of the multiplier is large, the cost of the LSI increases and the multiplication speed also decreases. Therefore, the filter order may be limited in order to obtain the required processing speed.

Also, when using a general-purpose ROM connected outside the multiplier as a coefficient memory, if the word length is 8.16.24 bits, R
Although the OM address space can be used efficiently, the usage efficiency decreases for word lengths other than this.

In view of the above-mentioned problems, it is an object of the present invention to enable highly accurate calculations without increasing the circuit scale, and to improve the cost/performance ratio by improving the utilization efficiency of the coefficient ROM.

[Means for solving problems]

As shown in the embodiment of FIG. 1, there is a memory (ROM2) that stores multiplication coefficients, a multiplier that multiplies the multiplication coefficient read from this memory by an input sample sequence, and an adder that receives the multiplication output as input. 4, an accumulator 5 that accumulates the addition output, and a digit shifter 9 that digit-shifts the accumulator output and then adds it to other inputs of the adder.

In the memory, multiplication coefficients related to the impulse response of the filter are stored in double precision for the part A where the coefficient value is large, and in single precision for the part A where the coefficient value is small. The double-precision coefficient is configured to be multiplied by the input sample string separately into upper and lower digits, and after the digit shifter 9 aligns the digits of each partial product, cumulative addition is performed.

〔Example〕

FIG. 1 is a circuit block showing an embodiment of the digital filter of the present invention. As is well known, this digital filter includes a RAMI for storing PCM data (16 bits),
It includes a ROM 2 for storing multiplication coefficients, an adder 3, and an accumulator 4.

This circuit is similar to the well-known FI signal flow diagram shown in Figure 2.
The signal processing of the R-type digital filter will be concretely executed.

In FIG. 1, when the number of filter stages is N (next), the counter 6 counts clocks of Nf (fs is the sampling frequency of the human sample sequence) to generate an address, and based on this address, the counter 6 generates an address from the ROM 2. 0 to 8 are sequentially read out as a series of coefficients corresponding to each multiplication stage in FIG. The address output of the counter 6 is also sent to the RAMI via the adder 7, and the input data string corresponding to each delay stage z-1 in FIG. 2 is read out. Note that in order to execute delay processing for each sample in each delay stage Z-1 in the RAM 1, the output of a counter 8 that counts clocks at a sampling frequency f is given to the other input of the adder 7, and the address of the RAMI is is stepped at the sampling period.

A series of coefficients and input data read from the ROM 2 and RAMI are applied to the multipliers 3, X and Y, and product outputs of the multiplication results are sequentially derived. The product output is accumulated in an accumulator 5 through an adder 4. By feeding back the cumulative output to the other input of the adder 4, a product-sum calculation such as a convolution operation is executed.

FIG. 3 is a typical low-pass characteristic diagram of the FIR filter shown in FIG. 2. A series of coefficient values to be stored in the ROM 2 can be determined using the discrete amplitude values of the impulse response waveform shown in FIG. 4, which correspond to this characteristic. can.

Impulse response of low-pass filter characteristic is 5inx/x
It is only in the center that the amplitude is close to the curve of , and the amplitude is large as shown in FIG. Therefore, the impulse response waveform shown in FIG. 4 is divided into a central part A and a peripheral part B, and double precision calculation is performed for the central part. For example, the coefficient word length is set to 14 bits in single precision, and the coefficients for the peripheral part B are created using this, and for the central part A, a word length of 2 is used, for example, 14 bits more.
Create coefficients using 8 bits. Although the central part requires twice the calculation time due to double-length calculation, the overall calculation accuracy equivalent to 18 bits is obtained, and when the input is 16 bits, it is approximately 9.
An attenuation of 0 dB is obtained.

The effective word length of the coefficient is 14 bits.

Specifically, in the center area A, the 18-bit coefficient k n (n = o-N) shown in FIG. 5A is changed to the upper digits as shown in FIG. and 7 in the lower digit
'(b, 3 to bo) and create a coefficient table. For the lower digits, the data is multiplied by 2" (in this example, W = 4) in advance, and both the upper and lower digits are made up of 14 bits. Multiplication is performed twice for the upper and lower digits, and The multiplication results for the digits are amplified to the right as shown in Figure 5C and are
Multiply by 1 and add with the multiplication result of the upper digit. As a result, 14
For a coefficient word length X of bits, an effective precision of X+W is obtained.

In the peripheral part B of the impulse response, 20 times the coefficient data (14 bits) is prepared in the same way as for the lower digits to the center part, and the multiplication result is subjected to 21 times the processing.

The result is the same as without multiplying by 2''.

In the circuit shown in FIG. 1, the output of accumulator 5 is transferred to shifter 9.
(arithmetic right shift circuit ASR), performs 2-times digit alignment, calculates to adder 4, adds it to the output of multiplier 3, and accumulates in accumulator 5 again.

FIG. 6 shows the addressing method of RAMI and ROM2 in this case. In the ROM 2, 0 to kN are written in the order of regions B, A, and H in the coefficient time series corresponding to the impulse response shown in FIG. At this time, for the center part A, the lower digit k of the coefficient. ′
Write only. For the upper digits of area A, RO
Write by adding an appendix to the end of the M address space.

When multiplying, RAMI address 0 in one sample interval
The address of ROM2 is changed from O to N as the value changes from ~N. Note that ROM addresses (L) to (M)' for lower digits are generated for RAM address LM of area A. The shifter 9 receives a shift/non-shift control signal S/
At this time, the output of the accumulator 5 is transferred to the adder 4 without shifting the digits as a non-shift.

At the end of address N, the product-sum cumulative value is stored in accumulator 5. Next, the address LM of area A is given again as the RAMI address. On the other hand, the addresses of ROM2 are addresses (L) to (M)# for upper digits. RAMI initially specified by addresses L and (L)#, respectively.
A multiplication output is derived from the t multiplier 3 for each output of the ROM 2 and the ROM 2. At this time, the mode of the shifter 9 is switched to shift, and as shown by ■ in FIG. be done. Note that the lower W bits are truncated. Thereafter, the shifter 9 is returned to the non-shift mode, and sum-of-products calculations are performed for the upper digits that do not require shifting.

Next, Figure 7 is a circuit block diagram (main part) showing another embodiment.
So, Figure 8 shows RAMI, ROM? 7) 7) 'Res method is shown. In this example, the output of multiplier 3 is applied to 21 shifters 9 (A
SR) is provided. As shown in Figure 8, for the central part A of the impulse response, 7' is placed in the lower digits and 7' is placed in the upper digits.
'' are written alternately to a series of addresses in ROM2. Therefore, the address of RAMI is 0.1.2-- in peripheral part B.
−−−−・−・・・・N are generated sequentially, and in the center A, the same address is generated, L, l, +l, L +
It is generated twice each time, such as 1------1・---1111・-. And in response to this, ROM2
The addresses for lower digits and upper digits are (L)' and (L)
", (L+1)', (L+1)"...----
They are generated alternately like - and -. As shown by ■ in FIG. 8, the shifter 9 is alternately switched so that it is in a shift mode when calculating lower digits, and into a non-shift mode when calculating upper digits. The results are the same as in FIG.

Note that in the embodiment shown in FIG. 7, the LSB W bit (4 bits) is truncated for each calculation of the lower digits, so in order to obtain the required calculation precision, it is necessary to provide an allowance for the accumulator length of 50 words. . On the other hand, in the embodiment shown in FIG. 1, the noise for the first SBI bits of the data to be cumulatively added is reduced by W bits by shifting the cumulative value by 2-', so the lower bit margin of the accumulator 5 is It can be small. For example, in the example in Figure 7, the accumulator word length is 2.
In the case of 0 bits, 18 bits are sufficient in the example of FIG.

〔Effect of the invention〕

As described above, the present invention divides the multiplier coefficient sequence corresponding to the impulse response of the filter into a part with a large coefficient value and a part with a small coefficient value, and performs double-precision calculation by partial product operation only on the large part. Therefore, it is possible to perform double-precision calculations using single-precision coefficients. Therefore, the coefficient memory is very efficiently used and has a small capacity, and the number of bits handled by the multiplier is small for high-precision calculations. Since the number is small, the circuit scale is small and high-speed calculation is possible.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram of a digital filter showing an embodiment of the present invention, Fig. 2 is a signal flow diagram of an FIR filter, Fig. 3 is a frequency characteristic graph showing an example of LPF characteristics, and Fig. 4 is a low-pass filter. FIG. 5 is a diagram showing an example of the operation word length, FIG. 6 is an address diagram of the RAM and ROM in FIG. 1, and FIG. 7 is a main block diagram showing another embodiment. , Figure 8 shows R in the case of Figure 7.
The address diagram of AM and ROM, FIG. 9, is a graph of the amount of attenuation versus the order of the digital filter. In addition, in the symbols used in the drawings, 1.
−・−111・−−−−・−ROM3−・・−・・−
・・・Multiplier 4−−−−−−・−・−−−1−・・−Adder 5−・−
・−−−−−−−−−−1−Accumulator 9−・−・
--111--・-1--- It is a shifter.

Claims (1)

[Claims] A memory that stores a multiplication coefficient, a multiplier that multiplies the multiplication coefficient read from this memory by an input sample sequence, an adder that receives the multiplication output as input, an accumulator that accumulates the addition output, and a digit representation of the accumulator output. and a digit shifter that shifts the multiplication coefficients and then adds them to the other inputs of the adder, and stores the multiplication coefficients related to the impulse response of the filter in double precision for parts with large coefficient values and in single precision for parts with small coefficients. A digital filter that stores the double-precision coefficients in the upper and lower digits and multiplies them with the input sample string, then adjusts the digits of the partial products using a digit shifter, and then performs cumulative addition.