JP2003298398A - Digital filter arithmetic processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit area including a counter for an address signal generating circuit and enable its application to a symmetric arithmetic structure by using RAMs in a data storage circuit. <P>SOLUTION: The circuit is provided with a data storage unit consisting of RAMs 11-14, selectors 6, 7 for switching input signals of each of the RAMs 11, 14, selectors 8, 9 for switching output signals of each of the RAMs 11, 12 and 13, 14, and latches 4, 5 for holding output data of each of the RAMs 14, 11 by one step. When the RAMs 11, 13 are in a data reading period, the RAMs 12, 14 write the data, and when the RAMs 11, 13 are in a data writing period, the RAMs 12, 14 read the data. When the output data of the RAM 14 are written into the RAM 11, the output data are written after being held by one step in the latch 5, and when the data of the RAM 11 are written into the RAM 14, the data are written after being held by one step in the latch 4. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter arithmetic processing circuit, and more particularly to a digital filter arithmetic processing circuit in an FIR digital filter (hereinafter referred to as FIR filter).

[0002]

2. Description of the Related Art Conventionally, in this type of digital filter, when the number of taps is small, a memory circuit for storing data is often composed of a register.

Number of taps 2N (N = 1, 2, 3, ...)
Referring to FIG. 10 (A), which is a symbol diagram showing the FIR filter of FIG.
It has a delay device group 101 having −1 delay device 102, a coefficient multiplier 103 that multiplies the coefficient of each tap, and an adder 104 that adds the output of each tap and outputs the output Dout.

The input data Din holds 2N-1 delay devices for holding a period of one clock (not shown) (hereinafter, one step) in the order of A _{2n-1 to} A ₀ from new data to old data. It is stored in the delay group 101 composed of 102 and used in the calculation until it passes through 2N−1 delays 102.

The conventional first digital filter arithmetic processing circuit, which is a general configuration for implementing the FIR filter of FIG. 10 (A) by hardware, is common to the components common to FIG. 10 (A). Referring to FIG. 10 (B), which is shown in blocks with reference letters / numbers, the FIR shown in this figure
The filter includes a data storage unit 201 corresponding to the delay unit group 101 in (A), a coefficient multiplier 103, and an adder 104.
And an accumulator 202 that accumulates the output of the adder 104.

The data storage unit 201 has a write enable signal WE and a read enable signal R for controlling data storage.
E and the address ADR for accessing the data storage unit are supplied.

The outline of the arithmetic operation of this digital filter will be described with reference to FIG. 10B. The data stored in the data storage unit 201 is read out in order from the oldest data and arithmetically executed.

An example of the case in which the data storage unit 201 is configured by a register is shown in the same block as FIG. 10B with common reference characters / numerals attached to common components.
Referring to (C), the data storage unit 201 shown in this figure
Input data Din by the write enable signal WE
And a plurality of registers 21 that store the
4, a register group 211 composed of four, a tap changeover switch 212 controlled by an address signal ADR, and a data read switch 213 controlled by a read enable signal RE and outputting read data Do. The data read switch 213 is not always necessary.

Next, with reference to FIGS. 10A, 10B, and 10C, the operation of the first conventional digital filter arithmetic processing circuit will be described. Data stored in the register group 211 will be described. , The data is read out and the read data Do is output by switching the tap switches in order from the oldest data. The coefficient multiplier 103 multiplies the read data Do by the coefficient of the tap and supplies the result to the adder 104. The adder 104 and the accumulator 202 accumulate the supplied coefficient multiplication data and generate / output the output data Dout.

However, when the number of taps increases, it is disadvantageous in terms of circuit area to form a data storage circuit with a register. Therefore, when the number of taps is large, a RAM which is advantageous in area is used for the data storage unit.

When a RAM is used as the data storage unit 201, there is a method of shifting the address of the RAM and reading the data in order from the oldest data.

Addresses 1-2N- of the data storage unit 201
Referring to FIG. 11 (A) which is a schematic explanatory view showing a state where 2N-1 pieces of data are stored in the oldest order in 1 in FIG. 11, the data D _{0 at the} address 1 shown in this figure is the oldest data, will read the data from the data _{D 0} of the address 1 in order, address 2N-1 of data _{D 2N- 1}
After reading, the latest data D _{0 of the} input data Din
Is directly output as the output data DO, and at the same time, is written in the address 1.

Immediately after D ₀ is written to address 1,
As shown in FIG. 11B, the data D at the address 2
_2N-2 is the oldest data. Next, the data of the address 2 is sequentially read out, the data of the address 0 is read out, and then the latest input data D ₁ of the next input data Din is directly output as the output data DO and simultaneously written in the address 2. Immediately after the latest data D ₁ is written in the address 2, the result is as shown in FIG.

Referring to FIG. 12 which is a block diagram showing a data storage section and an address generation section of a second conventional digital filter arithmetic processing circuit for realizing the above operation, a data storage section 301 shown in this figure includes a RAM 311 and an address. A switch 304 for switching output data controlled by the signal ADR is provided.

Further, the address generation unit is a counter 302.
And the output of the counter 302 to decode the data storage unit 3
01 and a decoder 303 for generating an address signal ADR.

When the number of taps = 2N, the counter 302
Is, ^{(2N) 2} = 4N 2 binary counters are required, the circuit scale of the counter increases. Despite the use of RAM, which is advantageous in area, if the counter portion becomes large, a large effect on area cannot be obtained. Therefore, it is required to use the RAM and reduce the area.

In order to meet this demand, for example, a memory control circuit disclosed in Japanese Patent Publication No. 7-72876 (reference 1) is a data shift for reading / writing data in one step only by dividing the RAM into two. I am proposing a circuit. A conventional third digital filter arithmetic processing circuit in which an FIR filter is realized by hardware using the method described in Reference 1 is similarly blocked by attaching common reference characters / numerals to components common to FIG. 13, the third conventional digital filter arithmetic processing circuit shown in this figure has a coefficient multiplier 103, an adder 104, and an accumulator 202 which are common to the first conventional digital filter arithmetic processing circuit. In addition to the data storage unit 201, the address signal ADR and the write enable signals WE1 and W
A data storage unit 401 that is controlled by E2 and outputs output data DO, a counter 402 that outputs an address signal ADR, and a switch 403 that conducts / blocks the input data Din in response to the supply of the address signal ADR.

Referring to FIG. 14, which shows a block diagram of the structure of data storage unit 401, data read is controlled by read enable signals RE1 and RE2, and data write is controlled by write enable signals W1 and W2.
First and second Rs accessed by each of R1 and ADR2
AM 411 and 412, an inverter 413 that inverts the address signal ADR0, and a mask signal generation circuit 41 that generates the mask signal M in response to the supply of the address signal ADR.
4 and the inverted value of the address signal ADR0 and the mask signal are ANDed to generate a read enable signal RE2 A
And an ND circuit 415.

For convenience of explanation, assuming that the operation of the third conventional digital filter arithmetic processing circuit is 8 taps,
The counter 402 is an octal counter. This counter 4
The address signal ADR output by 02 becomes 3-bit address signals ADR2, ADR1, ADR0.

Next, the operation of the third conventional digital filter arithmetic processing circuit will be described with reference to FIGS. 13 and 14 and FIG. 15 showing the waveforms of the respective parts in a time chart. The input data Din is used for the arithmetic operation. In that case, the switch 403 is turned on. Address signal ADR2, ADR1
Are address signals of RAMs 411 and 412 (indicated as RAM1 and RAM2 in the figure). The address signal ADR0 is used as the read enable signal RE1 for the RAM 411, and the inverted value of the address signal ADR0 is stored in the RAM.
It is used as a read enable signal for 412. However, when inputting the input data Din, the RAMs 411, 41
No data is read out in either of the two cases, and the input data Din
Is output as output data DO on the DO output signal line.
Therefore, the read enable signal must be disabled.

The mask signal generation circuit 414 generates a mask signal M that disables the read enable signal. The AND circuit 415 calculates the logical product of the inverted value of the address signal ADR0 and the mask signal to generate the read enable signal RE2.

As shown in the time chart of FIG. 15, this third conventional digital filter arithmetic processing circuit is
The data shift is realized in steps.

However, in the third conventional digital filter arithmetic processing circuit, when the coefficients of the FIR filter are symmetrical, the sum of the data to be multiplied by the same coefficient is calculated in advance, and the coefficient is added to the addition result. There is a problem that it cannot be applied to a symmetrical operation configuration that can reduce the number of operations by half by multiplying by.

FIG. 10 shows an FIR filter having a tap number of 2N and a symmetrical operation configuration in which the coefficients of the FIR filter are symmetrical.
Referring to FIG. 2, which is also a symbol diagram in which common reference characters / numerals are attached to common components to (A), the FIR filter shown in this diagram has cascaded 2N−1 delays. Output of each coefficient multiplier 103, a delay group 101 having a multiplier 102, a coefficient multiplier 103 that calculates in advance the sum of data to be multiplied by the same coefficient of each tap, and multiplies the addition result by a coefficient And an adder 104 that outputs the output Dout.

With reference to FIGS. 2, 13 and 14, a FIR filter having a symmetric arithmetic configuration is used as the data storage unit 401 corresponding to the delay group 101 when the technique of the third conventional digital filter arithmetic processing circuit is used. The operation will be described. First, consider the case where the latest data of the input data Din is input and the data is read from the address 2N-1. First, regarding the reading and writing of the older data, the data is sequentially read in such a manner that the data at address 2N-1 is read → the data at address 2N-2 is read and the data at address 2N-2 is written to 2N−1 → .... It is possible to shift, and therefore the third conventional technique can be applied.

However, in inputting / reading the newer data, since the data at the address 0 is not read in the process of inputting the latest data of the input data Din → data reading of the address 0, the latest data of the input data Din is read. However, there is a problem that processing cannot proceed because the address 0 cannot be written.

Therefore, the technique of the conventional third digital filter arithmetic processing circuit cannot be applied, and the next data must be written after waiting for the old data to be read out. The same calculation time as in the case of the asymmetrical calculation configuration which is not left-right symmetric, that is, twice as long as the symmetrical calculation configuration is required.

[0028]

Since the first conventional digital filter arithmetic processing circuit described above uses a register for the data storage circuit, it is not possible to configure the data storage circuit with the register when the number of taps increases. There was a disadvantage that it was disadvantageous.

In the second conventional digital filter arithmetic processing circuit whose circuit area is reduced by using the RAM for the data storage circuit, the circuit area of the counter section which is the address signal generating circuit increases as the number of taps increases. , R
There is a drawback that the area reduction effect of AM is reduced.

The second conventional digital filter arithmetic processing circuit for solving the drawbacks of the second conventional technology is F
When the coefficients of the IR filter are bilaterally symmetric, it cannot be applied to a symmetrical operation configuration that halves the operation time, and there is a drawback that the operation time cannot be reduced.

An object of the present invention is to use a RAM in a data storage circuit.
It is an object of the present invention to provide a digital filter arithmetic processing circuit which uses the above, reduces the circuit area including the counter of the address signal generation circuit, and is applicable to a symmetrical arithmetic configuration.

[0032]

According to the digital filter arithmetic processing circuit of the present invention, the coefficient in the FIR type digital filter having the tap number 2N (N is a positive integer) is h ₀ = h _2N−1 , h. _{1 = h 2N-2, ···} , h m
= H _2N-1-m (N = 0, 1, 2, ..., M = 0,
1, 2, ..., 2N-1) and a symmetrical operation in which the data storage circuit is composed of RAM and the data is shifted during the filter operation to reduce the operation time during the filter operation processing by half. In the digital filter arithmetic processing circuit applied to the configuration, the first, second, third, fourth
A data storage unit including a RAM, and the second and fourth R
First and second selectors for switching respective input signals of AM, a third selector for switching outputs of the first and second RAMs, and outputs for switching outputs of the third and fourth RAMs. A fourth selector and first and second latches that hold the output data of the fourth and first RAMs for a period of one step, respectively, and include the first and third RAMs and the third RAM. The second and fourth RAMs are connected to each other so as to form a pair, and when the first and third RAMs are in a data reading period, the second and fourth RAMs write data, and When the first and third RAMs are in the data writing period, the second and fourth RAMs read data, and the first to third
The fourth RAM is controlled when the output data of the fourth RAM is written into the first RAM by controlling the fourth selector.
Output data of the first RAM is held by the second latch for a period of one step, and then the writing is performed. When the data of the first RAM is written to the fourth RAM, the data of the first RAM is It is characterized in that the writing is carried out after holding for one step period by two latches.

According to a second aspect of the present invention, in the digital filter arithmetic processing circuit according to the first aspect, the latest data used in the arithmetic operation is stored in the data storage section, and the latest data is stored in the data storage section during the arithmetic operation. It is characterized in that data is read from the.

According to a third aspect of the present invention, in the digital filter arithmetic processing circuit according to the first aspect, the first address signal for designating an address of each of the first and third RAMs and the second and the second address signals. An address generation circuit for outputting a second address signal designating each address of the fourth RAM is provided.

According to a fourth aspect of the present invention, in the digital filter arithmetic processing circuit according to the third aspect, the address generating circuit generates a counter signal for generating the first address signal, and the first address signal. And a delay circuit for generating the second address signal by delaying for 1 step.

According to a fifth aspect of the present invention, in the digital filter arithmetic processing circuit according to the fourth aspect, the counter circuit includes an N / binary counter, and the delay circuit outputs the first address signal to 1 It is configured to include a flip-flop circuit that holds a step.

According to a sixth aspect of the present invention, there is provided a digital filter arithmetic processing circuit in which the FI has a tap number of 2N (N is a positive integer).
The coefficient in the R-type digital filter is h ₀ = h
_{2N-1, h 1 = h} 2N-2, ···, h m = h
_2N-1-m (N = 0, 1, 2, ..., m = 0, 1,
2, ..., 2N-1), and a symmetrical operation configuration in which the data storage circuit is configured by RAM and data is shifted during filter operation to reduce the operation time during filter operation processing by half. In the applied digital filter arithmetic processing circuit, the first, second, third and fourth R
A data storage unit including an AM and the second and fourth RAMs
, A first selector for switching input signals of each of the first and second selectors, a third selector for switching outputs of the first and second RAMs, and a third selector for switching outputs of the third and fourth RAMs. 4 selectors, 1st and 2nd latches that hold the output data of each of the 4th and 1st RAMs for a period of one step, and addresses of each of the 1st and 3rd RAMs A first address signal for outputting a second address signal for designating an address of each of the second and fourth RAMs, and the first, second, third,
Each of the fourth RAMs includes an address terminal, a data input terminal, a write enable terminal, a read enable terminal, and a data output terminal, and the address terminal of each of the first and third RAMs has the first terminal. The address signal, the first write enable signal at the write enable terminal,
A read enable signal is supplied to the read enable terminal, the second address signal is supplied to the address terminals of the second and fourth RAMs, and a second write enable signal is supplied to the write enable terminal. An inverted read enable signal is supplied to each of the read enable terminals, and the data input terminal of the first RAM serves as an output terminal of the first latch and the second RA.
The data input terminal of M is the output terminal of the first selector, and the data input terminal of the third RAM is the second R.
The data input terminal of the fourth RAM is connected to the data output terminal of the AM, and the data output terminal of the first RAM is connected to the output terminal of the second selector. The data output terminal of the first RAM is the second input of the third selector. A data output terminal of the second RAM, a third input terminal of the third selector and a data input terminal of the second RAM, and a third RAM. Data output terminal of the fourth selector is the first input terminal and the second input terminal of the first selector, and the data output terminal of the fourth RAM is the second input of the fourth selector. Terminal, the input terminal of the first latch, and the second input terminal of the first selector, respectively, and the first input terminal of the third selector and the second input terminal of the second selector. Supply input data to each When the first and third RAMs are in the data reading period, the second and fourth RAMs are writing data, and the first and the third RAMs are in the data writing period. , The second and fourth RAMs read data, and control the first to fourth selectors by a selector control signal to transfer the fourth RAM to the first RAM.
When writing the output data of the first RAM, the output data of the fourth RAM is held in the second latch for a period of one step, and then the writing is performed to write the first RAM to the fourth RAM.
When writing the data of, the data of this first RAM is
The writing is performed after the latch of 1 holds for a period of one step.

According to a seventh aspect of the present invention, there is provided a digital filter arithmetic processing circuit in which the FI has a tap number of 2N (N is a positive integer).
The coefficient in the R-type digital filter is h ₀ = h
_{2N-1, h 1 = h} 2N-2, ···, h m = h
_2N-1-m (N = 0, 1, 2, ..., m = 0, 1,
2, ..., 2N-1), and a symmetrical operation configuration in which the data storage circuit is configured by RAM and data is shifted during filter operation to reduce the operation time during filter operation processing by half. In the applied digital filter arithmetic processing circuit, the first, second, third and fourth R
A data storage unit including an AM and the second and fourth RAMs
, A first selector for switching input signals of each of the first and second selectors, a third selector for switching outputs of the first and second RAMs, and a third selector for switching outputs of the third and fourth RAMs. 4 selectors, 1st and 2nd latches that hold the output data of each of the 4th and 1st RAMs for a period of one step, and addresses of each of the 1st and 3rd RAMs A first address signal for outputting a second address signal for designating an address of each of the second and fourth RAMs, and the first, second, third,
Each of the fourth RAMs includes an address terminal, a data input terminal, a write enable terminal, a read enable terminal, and a data output terminal, and the address terminal of each of the first and third RAMs has the first terminal. The address signal, the first write enable signal at the write enable terminal,
A read enable signal is supplied to the read enable terminal, the second address signal is supplied to the address terminals of the second and fourth RAMs, and a second write enable signal is supplied to the write enable terminal. An inverted read enable signal is supplied to each of the read enable terminals, and the data input terminal of the first RAM serves as an output terminal of the first latch and the second RA.
The data input terminal of M is the output terminal of the first selector, and the data input terminal of the third RAM is the second R.
The data output terminal of the fourth RAM is connected to the data output terminal of the AM, and the data input terminal of the fourth RAM is connected to the output terminal of the second selector. The data output terminal of the first RAM is the first input of the third selector. A data output terminal of the second RAM to a second input terminal of the third selector and a data input terminal of the second RAM to the third RAM. Data output terminal of the fourth selector is the first input terminal and the second input terminal of the first selector, and the data output terminal of the fourth RAM is the second input of the fourth selector. Terminal, the input terminal of the first latch, and the second input terminal of the first selector, respectively. The second input terminal of the second selector is supplied with input data, Third R
When AM is a data read period, the second and fourth RA
M writes data, and when the first and third RAMs are in a data write period, the second and fourth RAMs read data and the selector control signal causes the first to the first RAMs to read. 4 selectors to control the fourth RAM to the first RAM.
When writing the output data of the RAM, the output data of the fourth RAM is held in the second latch for a period of one step, and then the writing is performed, and the first data is written into the fourth RAM.
When writing the data in the RAM, the writing is performed after the data in the first RAM is held by the second latch for a period of one step.

The invention according to claim 8 is the digital filter arithmetic processing circuit according to claim 6 or 7,
It is characterized in that the selector control signal is the first and second address signals.

The invention according to claim 9 is the digital filter arithmetic processing circuit according to claim 6 or 7, wherein:
The address generation circuit includes a counter circuit that generates the first address signal, and a delay circuit that delays the first address signal for a period of one step to generate the second address signal. Has been done.

The invention according to claim 10 is the same as that of claim 9
In the digital filter arithmetic processing circuit described above, the counter circuit includes an N / binary counter, and the delay circuit includes a flip-flop circuit that holds the first address signal for one step.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the digital filter arithmetic processing circuit of this embodiment, the coefficients in the FIR type digital filter (hereinafter referred to as FIR filter) are h ₀ = h _2N−1 , h ₁ = h.
_{2N -2, ···, h m =} h 2N-1-m (N = 0,
1,2, ..., m = 0,1,2, ..., 2N-1)
This is a case where the data storage circuit for storing data is composed of RAM, and the data can be shifted at the time of filter calculation to reduce the calculation time during calculation processing by half. In the filter arithmetic processing circuit, a data storage section including first to fourth RAMs, first and second selectors for switching input signals of each RAM, and third and fourth selectors for switching outputs of each RAM. Of the first to fourth RAMs that form a data storage unit, each of which has a selector and first and second latches for holding data for one step, first, third and second RAMs. , And the fourth RAMs 14 form a pair to read / write data. That is, when the first and third RAMs are in the data reading period, the second and fourth RAMs are writing data, and when the first and the third RAMs are in the data writing period, the second and , The fourth RAM reads data. However, when the first RAM writes the output data of the fourth RAM and when the fourth RAM writes the data of the first RAM, the data is held by the latch circuits 4 and 5 for one step, and then the data is stored. Write.

Therefore, since the data can be read and written at the same time, the RAM can be used and the operation time can be reduced by half.

FIR with a tap number of 2N (N = 1, 2, 3, ...) In the symmetrical operation configuration to which the present embodiment is applied
Referring to FIG. 3, which shows the filter in a symbolic diagram, this F
The IR filter is composed of 2N-1 delay units 1 connected in cascade.
A delay group 101 having 02, and an adder 10 that calculates in advance the sum of data to be multiplied by the same coefficient of each tap,
It includes a coefficient multiplier 103 for multiplying the coefficients on the addition results of the adders 10, and an adder 104 for outputting an output Dout by adding outputs of the coefficient multipliers 103, coefficients h _{0
= H 2N-1, h 1} = h 2N-2, ···, h m = h
_2N-1-m (N = 0, 1, 2, ..., m = 0, 1,
2, ..., 2N-1) are symmetrical.

Next, the delay group 1 of the FIR filter shown in FIG.
01, which is a block diagram of the first embodiment of the present invention in which 01 and the adder 10 are realized by hardware, the digital filter arithmetic processing circuit of the present embodiment shown in this figure RAMs 11, 12, 1 which are RAMs divided into four for storing data used in calculation
A data storage unit 1 composed of 3, 14 and an address signal A
1, an address generation circuit 2 for generating A2, and an inverted write enable signal RE by inverting the write enable signal RE.
Inverter 3 for generating B, latches 4 and 5 for holding data for one step, and address signal A
1, RAM 2 and 14 of the data storage unit 1 controlled by A2
Input data switching selectors 6 and 7, and selectors switching to output either the input data Din controlled by the address signals A1 and A2 and the output data from the RAMs 11 and 12 of the data storage unit 1. 8 and RAM
A selector 9 that switches to output either one of the output data of 13 and 14 and an adder corresponding to the adder 10 of the above symbol diagram that adds the outputs of the selectors 8 and 9 to generate added data DA And a container 10.

RAMs 11, 12, 1 which are the same RAM
Describing the input / output terminals of the RAM 11 on behalf of the RAMs 3 and 14, the RAM 11 has an input terminal of an address A, a data input DI, a write enable WE, a read enable RE, and a data output DO terminal. Have.

As will be described later, the RAM 11 uses only the storage area corresponding to address 1, and each of the RAMs 12, 13, 14 uses two storage areas corresponding to addresses 0 and 1.

The address signals A1 are supplied to the address A terminals of the RAMs 11 and 13, the write enable signal WE1 is supplied to the write enable WE terminals, and the read enable signal RE is supplied to the read enable RE terminals.
The address signal A2 is applied to the address A terminals of AM12 and AM14.
However, the write enable signal WE2 is supplied to the write enable WE terminal, and the inverted read enable signal REB is supplied to the read enable RE terminal.

The data input DI of the RAM 11 is an output terminal of the latch 4, and the data input DI of the RAM 12 is a selector 6.
The data input DI of RAM13 is connected to RAM1
The second data output DO and the data input DI of the RAM 14 are connected to the output terminal of the selector 7, respectively.

The data output DO of the RAM 11 is the selector 8
Of the RAM 12 to the input terminal C of the selector 8 and the data input DI of the RAM 12, and the data output DO of the RAM 13 to the input terminal A of the selector 9 and the input terminal of the selector 6. RA on B
The data output DO of M14 is connected to the input terminal B of the selector 9, the input terminal of the latch 4 and the input terminal B of the selector 6, respectively.

The input data Din is supplied to the input terminal A of the selector 8 and the input terminal B of the selector 7, respectively.

Referring to FIG. 2, which shows a block diagram of the structure of the address generation circuit 2, the address generation circuit 2 outputs the address signal A2 by delaying the counter 21 for outputting the address signal A1 and the address signal A1 by one step. And a delay circuit 22 for generating.

Next, the outline of the operation of the present embodiment will be described with reference to FIGS. 1, 2 and 3. First, in the data read, the address generation circuit 2 causes the address signal A to be read.
1 and A2 are output. The selectors 8 and 9 are controlled by the address signals A1 and A2, and the RAMs 11, 12, 1
Select the read data to be read from each of 3 and 14,
It is supplied to the adder 10. When representing the signals related to each RAM in the figure, each of the RAMs 11, 12, 13, and 14 is represented by each of A, B, C, and D.

For data writing, when data writing is performed after waiting for the reading of the write destination data, the period for waiting the data reading is one step period (hereinafter referred to as one step), and the latch circuit is used. Data is held at 4 and 5. RAM1
Input data of 2 and 14 is selected by selectors 6 and 7 controlled by address signals A1 and A2.

RAMs 11, 12, 1 of the data storage unit 1
Of four RAMs 3, 14, RAM 11 and RAM 1
3, and the RAM 12 and the RAM 14 are paired to read / write data. That is, RAM 11 and R
When the AM 13 is in the data reading period, the RAM 12 and RA
M14 writes data, and RAM11 and RAM13
During the data writing period, the RAM 12 and the RAM 14 read the data.

However, when the RAM 11 writes the output data of the RAM 14 and when the RAM 14 writes the data of the RAM 13, the data is written after the latch circuits 4 and 5 hold the data for one step.

Therefore, since reading and writing of data can be performed at the same time, the circuit area can be reduced by using the RAM and the operation time can be cut in half, and the circuit area of the counter can be reduced as described later. It can be greatly reduced.

Further, the digital filter arithmetic processing circuit of this embodiment is symmetrical, and the RAM 11 and
The same address can be used for data read / write at the same timing among 12, 13, and 14. Since the data is written to the address immediately after reading the data, the counter 21 An N / binary counter that changes every two steps may be used. Therefore, compared with the conventionally required the 4N ² binary counter, it is possible to significantly reduce the circuit area. For example, in the case of 8 taps according to the present embodiment, N = 4, so that a 64-bit counter is required in the conventional technique, whereas a binary counter may be used in the present embodiment.

The address signal A1 is sent to the counter 21.
Is used as it is, and the address signal A2 is a signal obtained by delaying the address signal A1 by one step. Therefore, the delay circuit 22 is a circuit for delaying one step,
It can be realized by a flip-flop or the like that operates with a clock of 1 cycle = 1 step.

Since the selectors 6, 7, 8, 9 and the counter 21 are well known to those skilled in the art and are not directly related to the present invention, a detailed description of their structure will be omitted.

Next, FIG. 4 schematically showing a data flow in a symbol diagram, FIG. 5 schematically showing a state of each part of the filter in each step in a symbol diagram and FIG. 6 showing each signal waveform in a time chart. The details of the operation of the present embodiment will be described with reference to FIG.
An example in which the number of taps of the IR filter is 8 will be described.

At a certain time, the data D _{7 to} D ₀ are
As shown in FIG. 4A, it is assumed that they are arranged side by side, D ₇ is directly input to the adder 10, and data D _{6 to} D ₀ are D, 0, A, 1, D, 1 as shown in the figure. , B, 1, C, 1, B,
It is assumed that the RAMs are stored in the order 0, C, 0.
The data D ₇ is the latest data of the input data Din, and the data D ₀ is the oldest data. Further, the above A, B, C and D are the RAMs 11, 12, 1 as described above.
3 and 14, respectively, 0 and 1 are these RAMs 11,
Each address of 12, 13, 14 (A, B, C, D) is shown. For example, D, 0 represents the address 0 of the RAM 14.

First, as the first step, RA
Data D ₀ stored at address 0 of M13 (C)
Then, the latest data D ₇ of the input data Din is output to the adder 10 (FIG. 5 (A)). As described above, in the first step, the RAM 13 is in the data reading period.

In the second step, the second newest data D stored at address 0 of RAM 12 (B)
₆ and the second oldest data D ₁ stored at address 0 of the RAM 14 (D) are output to the adder 10. R
While AM12 and RAM14 are reading data,
The data D ₁ currently being read is written to the address 0 of the RAM 13 where the reading of the data has already been completed (FIG. 5).
(B)). As described above, in the second step, the RAM1
2. The RAM 14 serves as a data reading period and the RAM 13 serves as a data writing period.

In the third step, the third newest data D stored at address 1 of RAM 11 (A)
₅ and the third oldest data D ₂ stored in the address 1 of the RAM 13 are output to the adder. While the RAM 11 and the RAM 13 are reading the data, the data D ₂ currently being read is written to the address 0 of the RAM 12, which has already finished reading the data. RAM14
The latest data D ₇ is written to the address 0 of. (Fig. 5
(C)). As described above, in the third step, the RAM1
1, RAM 13 is a data reading period, RAM 12, RA
M14 is a data writing period.

In the fourth step, the address of RAM 14
4th newest data D stored in 1_FourAnd RA
4th oldest data stored at address 1 of M12
TA D _ThreeIs output to the adder 10. RAM12 and RAM
While the 14 is reading the data, the data is already read
Is currently being read at address 1 of RAM 13
Data D_ThreeIs written. In addition, the RAM11 add
Data D to Res1₆Is written. (FIG. 5 (D)).
Data D₆R after being read from RAM14
It takes 3 steps to write to AM11
It Therefore, data D₆Is one step
After that, the data is written in the RAM 11. Since
As described above, in the fourth step, RAM12, RAM14
Is the data read period, and RAM11 and RAM13 are the data
Is the writing period.

In the fifth step, the next latest data D
₈At this time, stored at address 0 of RAM 13
Old data in points D₁Is output to the adder 10. D₈When
D₁While reading the
Data D at address 1 of the RAM 14₅Write in
To do. In addition, at the address 1 of the RAM 12, the data D_FourBook of
Include. (FIG. 5 (E)). Data D₅Is RAM
Until it is read from 11 and then written in RAM 14.
It takes 3 steps. Therefore, data D
₆Latch 1 step in latch 5 and then RAM1
Written to 4.

A selector is provided to switch the data to be read to the adder 10 for each step. In the present embodiment, the data X read to the adder 10
Is one of the latest data of the RAM 11 and RAM 12 or the input data Din, and the selector 8 selects this data. Similarly, the data Y read to the adder 10
Is data from the RAM 13 or RAM 14, and the selector 9 selects this data.

Further, it is necessary to switch the data input to the RAM 12 and the RAM 14. The RAM12 of DI, and data _{D C} read from RAM 13, RAM
The data D _D read from 14 may be input. The selector 6 switches the data input to the DI of the RAM 12. Similarly, the DI of the RAM 14, there is a case where the input data Din, and the data _{D A} read from RAM11 is input. By the selector 7,
The data input to the DI of the RAM 14 is switched. Each of the selectors 6, 7, 8 and 9 has an address A1,
Switching is performed according to the value of A2.

As described above, the counter 21 of the address generation circuit 2 is an N / binary counter when the number of taps is 2N. In this example, the number of taps is 8, that is, N = 4. Becomes Therefore, the counter 21 changes in a 2-step cycle, and the address A1 changes to the counter 2
The count result of 1 is output as it is. Also address A
2 generates the address A1 with one step delayed.

Referring also to FIG. 6, the data shift is performed according to a time chart. As shown in this figure, in a FIR filter having a characteristic of a symmetrical operation configuration in which coefficients are folded left and right, when a RAM is used as a data storage unit to configure hardware, a half of the normal operation processing is performed. Calculation can be performed in time.

Next, referring to FIG. 7, which is a block diagram of the second embodiment of the digital filter arithmetic processing circuit according to the present invention, the same components as those in FIG. 1 are designated by common reference characters / numerals. Then, the difference between this embodiment shown in this figure and the first embodiment described above is that the input data Din is RA
It is input only to M14, and instead of the selector 8, the output D _A of the RAM 11 and the output D _{B of the} RAM 12 of the data storage unit 1
Selector 8A that selects either one of
Is to prepare.

The arrangement of the data at a certain time according to the present embodiment is shown in FIG. 8 in which a common reference character / number is attached to the same constituent element as in FIG. The difference of the present embodiment from the above-described first embodiment is that the method of reading data to the adder is further devised, and the latest data used in the operation is also stored in the RAM of the data storage unit. R is used during calculation
This is the point where data is read from the AM.

In the first embodiment, the RAM 11 uses only the address 1 and does not use the address 0, while the remaining three RAM 12, RAM 13, RAM 14 are used.
Uses addresses 0 and 1.

Generally, when designing an FIR filter circuit of this kind, only the RAM 11 is used, not the RAM in which the address 0 does not exist, but four RAMs in which the addresses 0 and 1 exist. Address 0
Do not read / write data to / from. Therefore, the data can be easily controlled by reading all the data used in the calculation from the RAM.

Referring to FIG. 9 showing the waveform of each signal of this embodiment in a time chart, the data D ₇ is stored in the RAM 11
It is the same as the above-described first embodiment except that the address 0 is read. However, when the data D ₇ and D ₀ are read, the next new data D ₈ is input as the input data Din, and the data D ₇ is the next RAM.
When the writing to the address 0 of 11 is completed, the data D
₈ is written in the address 0 of the RAM 14.

[0078]

As described above, the digital filter arithmetic processing circuit of the present invention includes a data storage section including first, second, third and fourth RAMs and second and fourth RAMs. Input signal switching first and second selectors, first and second RAM output switching third selectors, and third and fourth RAM output switching fourth selectors , And a first and a second latch that hold the output data of each of the fourth and first RAMs for a period of one step, respectively, and the first, third and second RAMs respectively. When the first and third RAMs are connected so as to form a pair, and the first and third RAMs are in the data reading period, the second and fourth RAMs write data, and the first and third RAMs write data. During the loading period, the second and fourth RAMs read data and
The fourth RA to the first RAM by controlling the fourth selector
At the time of writing the output data of M, the output data of the fourth RAM is held by the second latch for a period of one step and then written, and the data of the first RAM is written to the fourth RAM. Sometimes the data in the first RAM is held in the second latch for a period of one step and then written, so that the data can be read and written at the same time. In addition, the RAM can be used to reduce the circuit area, and the counter circuit area can be reduced, so that the entire circuit area can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a digital filter arithmetic processing circuit of the present invention.

FIG. 2 is a block diagram showing a configuration example of an address generation circuit in FIG.

FIG. 3 is a symbol diagram showing an FIR filter having a symmetrical arithmetic configuration with a tap number of 2N (N = 1, 2, 3, ...).

FIG. 4 is a symbol diagram showing an arrangement of data in the FIR filter of this embodiment having eight taps.

FIG. 5 is a symbol diagram illustrating an example of the operation of the digital filter arithmetic processing circuit according to the present embodiment.

FIG. 6 is a time chart showing an example of the operation of the digital filter arithmetic processing circuit according to the present embodiment.

FIG. 7 is a block diagram showing a second embodiment of a digital filter arithmetic processing circuit of the present invention.

FIG. 8 is a symbol diagram showing an arrangement of data in the FIR filter of the present embodiment.

FIG. 9 is a time chart showing an example of the operation of the digital filter arithmetic processing circuit according to the present embodiment.

FIG. 10 is a symbol diagram showing a conventional first digital filter arithmetic processing circuit, a block diagram showing hardware,
FIG. 3 is a block diagram of a data storage unit when it is configured with a register and a register.

11 is an explanatory diagram schematically showing how 2N-1 pieces of data are stored in the data storage unit of FIG.

FIG. 12 is a block diagram showing an example of a second conventional digital filter arithmetic processing circuit.

FIG. 13 is a block diagram showing an example of a third conventional digital filter arithmetic processing circuit.

14 is a block diagram showing a configuration of a data storage unit in FIG.

FIG. 15 is a time chart showing an example of an operation in a third conventional digital filter arithmetic processing circuit.

[Explanation of symbols]

1, 201, 301, 401 Data storage unit 2 Address generation circuit 3, 413 Inverter 4,5 Latch 6, 7, 8, 9, 8A Selector 10, 104 Adder 11, 12, 13, 14, 311, 411, 412
RAM 21, 302, 402 Counter 22 Delay circuit 101 Delay device group 102 Delay device 103 Multiplier 202 Accumulator 211 Register group 212 Tap change switch 213 Read switch 214 register 303 Decoder 304, 403 switch 414 Mask signal generation circuit 415 AND circuit

Claims (10)

[Claims] 1. A FIR having 2N taps (N is a positive integer)
The coefficient in a digital filter is h ₀ =
_{h 2N-1, h 1 =} h 2N-2, ···, h m = h 2N
_-1-m (N = 0,1,2, ..., m = 0,1,2,
, 2N-1), and the present invention is applied to a symmetrical operation configuration in which the data storage circuit is composed of RAM and the operation time in the filter operation processing is reduced by half by shifting data in the filter operation. In a digital filter arithmetic processing circuit, a data storage section including first, second, third and fourth RAMs, and first and second selectors for switching input signals of the second and fourth RAMs. A third selector for switching the outputs of the first and second RAMs, a fourth selector for switching the outputs of the third and fourth RAMs, and each of the fourth and first RAMs And a first and a second latch for respectively holding the output data of 1 step for one step, and the first, the third RAM and the second, the fourth RAM are connected to form a pair respectively. , The first and third RAMs During the data reading period, the second and fourth RAMs write data, and when the first and third RAMs during the data writing period, the second and fourth RAMs Data is read and the first to fourth selectors are controlled to control the first RAM.
At the time of writing the output data of the fourth RAM to the fourth RAM, the output data of the fourth RAM is held in the second latch for a period of one step, and then the writing is performed.
A digital filter arithmetic processing circuit, characterized in that, at the time of writing the data of the first RAM to, the data of the first RAM is held by a second latch for a period of one step and then the writing is performed. 2. The digital filter arithmetic processing circuit according to claim 1, wherein the latest data used in the operation is stored in the data storage unit, and the latest data is read from the data storage unit during the operation. 3. A first address signal for designating an address of each of the first and third RAMs and the second and fourth Rs.
2. The digital filter arithmetic processing circuit according to claim 1, further comprising an address generation circuit for outputting a second address signal designating each address of AM. 4. A counter circuit, wherein the address generation circuit generates the first address signal, and a delay circuit which delays the first address signal for a period of one step to generate the second address signal. The digital filter arithmetic processing circuit according to claim 3, further comprising: 5. The digital circuit according to claim 4, wherein the counter circuit includes an N / binary counter, and the delay circuit includes a flip-flop circuit that holds the first address signal for one step. Filter arithmetic processing circuit. 6. FIR with 2N taps (N is a positive integer)
The coefficient in a digital filter is h ₀ =
_{h 2N-1, h 1 =} h 2N-2, ···, h m = h 2N
_-1-m (N = 0,1,2, ..., m = 0,1,2,
, 2N-1), and the present invention is applied to a symmetrical operation configuration in which the data storage circuit is composed of RAM and the operation time in the filter operation processing is reduced by half by shifting data in the filter operation. In a digital filter arithmetic processing circuit, a data storage section including first, second, third and fourth RAMs, and first and second selectors for switching input signals of the second and fourth RAMs. A third selector for switching the outputs of the first and second RAMs, a fourth selector for switching the outputs of the third and fourth RAMs, and each of the fourth and first RAMs First and second latches for respectively holding the output data of 1st step for a period of one step, a first address signal for designating respective addresses of the first and third RAMs, and the second and fourth RAMs. Specify each address of And an address generation circuit for outputting a second address signal, wherein each of the first, second, third, and fourth RAMs has an address terminal, a data input terminal, a write enable terminal, and a read enable terminal. A data output terminal, wherein the first address signal is applied to the address terminal of each of the first and third RAMs, the first write enable signal is applied to the write enable terminal, and the read enable terminal is applied to the read enable terminal. A read enable signal is supplied to the address terminals of the second and fourth RAMs, the second address signal is supplied to the write enable terminal, and the second write enable signal is supplied to the read enable terminal. An inverted read enable signal is supplied to each of the first RAM and the data input terminal of the first RAM is connected to an output terminal of the first latch. , The data input terminal of the second RAM is the output terminal of the first selector, the third RAM
Is connected to the data output terminal of the second RAM, the data input terminal of the fourth RAM is connected to the output terminal of the second selector, and the data output terminal of the first RAM is connected to the data output terminal of the second RAM. The second input terminal of the third selector and the input terminal of the second latch,
The data output terminal of the second RAM is the third input terminal of the third selector and the data input terminal of the second RAM, and the data output terminal of the third RAM is the fourth input terminal of the fourth selector. 1 input terminal and the second of the first selector
The data output terminal of the fourth RAM is connected to the second input terminal of the fourth selector, the input terminal of the first latch, and the second input terminal of the first selector. When input data is supplied to each of the first input terminal of the third selector and the second input terminal of the second selector, and the first and third RAMs are in a data read period. , The second and fourth RAMs write data, and when the first and third RAMs are in the data write period, the second and fourth RAMs read data, When the output data of the fourth RAM is written in the first RAM by controlling the first to fourth selectors by the control signal, the output data of the fourth RAM is changed to the second output data.
The writing is performed after holding for one step period by the latch of No. 1 and the data of the first RAM is written by one step by the second latch when writing the data of the first RAM to the fourth RAM. A digital filter arithmetic processing circuit, wherein the writing is performed after holding for a period of minutes. 7. FIR with 2N taps (N is a positive integer)
The coefficient in a digital filter is h ₀ =
_{h 2N-1, h 1 =} h 2N-2, ···, h m = h 2N
_-1-m (N = 0,1,2, ..., m = 0,1,2,
, 2N-1), and the present invention is applied to a symmetrical operation configuration in which the data storage circuit is composed of RAM and the operation time in the filter operation processing is reduced by half by shifting data in the filter operation. In a digital filter arithmetic processing circuit, a data storage section including first, second, third and fourth RAMs, and first and second selectors for switching input signals of the second and fourth RAMs. A third selector for switching the outputs of the first and second RAMs, a fourth selector for switching the outputs of the third and fourth RAMs, and each of the fourth and first RAMs First and second latches for respectively holding the output data of 1st step for a period of one step, a first address signal for designating respective addresses of the first and third RAMs, and the second and fourth RAMs. Specify each address of And an address generation circuit for outputting a second address signal, wherein each of the first, second, third, and fourth RAMs has an address terminal, a data input terminal, a write enable terminal, and a read enable terminal. A data output terminal, wherein the first address signal is applied to the address terminal of each of the first and third RAMs, the first write enable signal is applied to the write enable terminal, and the read enable terminal is applied to the read enable terminal. A read enable signal is supplied to the address terminals of the second and fourth RAMs, the second address signal is supplied to the write enable terminal, and the second write enable signal is supplied to the read enable terminal. An inverted read enable signal is supplied to each of the first RAM and the data input terminal of the first RAM is connected to an output terminal of the first latch. , The data input terminal of the second RAM is the output terminal of the first selector, the third RAM
Is connected to the data output terminal of the second RAM, the data input terminal of the fourth RAM is connected to the output terminal of the second selector, and the data output terminal of the first RAM is connected to the data output terminal of the second RAM. The first input terminal of the third selector and the input terminal of the second latch,
The data output terminal of the second RAM is the second input terminal of the third selector and the data input terminal of the second RAM, and the data output terminal of the third RAM is the fourth input terminal of the fourth selector. 1 input terminal and the second of the first selector
The data output terminal of the fourth RAM is connected to the second input terminal of the fourth selector, the input terminal of the first latch, and the second input terminal of the first selector. When input data is supplied to the second input terminal of the second selector and the first and third RAMs are in a data read period, the second and fourth RAMs write data. When the first and third RAMs are in a data writing period, the second and fourth RAMs read data, and the selector control signal controls the first to fourth selectors. When the output data of the fourth RAM is written to the first RAM, the output data of the fourth RAM is transferred to the second RAM.
The writing is performed after holding for one step period by the latch of No. 1 and the data of the first RAM is written by one step by the second latch when writing the data of the first RAM to the fourth RAM. A digital filter arithmetic processing circuit, wherein the writing is performed after holding for a period of minutes. 8. The digital filter arithmetic processing circuit according to claim 6, wherein the selector control signal is the first and second address signals. 9. A counter circuit, wherein the address generation circuit generates the first address signal, and a delay circuit which delays the first address signal for a period of one step to generate the second address signal. The digital filter arithmetic processing circuit according to claim 6 or 7, further comprising: 10. The digital circuit according to claim 9, wherein the counter circuit includes an N / binary counter, and the delay circuit includes a flip-flop circuit that holds the first address signal for one step. Filter arithmetic processing circuit.