JP2000091886A - Adaptive filter device and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an adaptive filter device and a signal processing method for realizing a highly precise movement adaptive processing by suppressing the increase of a circuit scale. SOLUTION: An adaptive filter device 10 writes supplied data in a memory part 14 under the control of a memory control part 16, and reads the data under the reading control of the memory control part 16 so that the reading start position DS of the data is shifted at each number of 4 taps and a data block DB divided at each number of 8 taps of an FIR filter part 12 is delayed. The reading speed is set two times as fast as the writing speed, and data corresponding to each delay element circuit 12b-12h of a delay circuit 12 are provided to each delay stage of a tap part 12B. Also, reading under the consideration of movement detection amounts (for example, vectors or the like) is operated in the memory part 14. The memory control part 16 controls the output of a multiplication coefficient from a multiplication coefficient outputting part 18 to the tap part 12B so that only the number of coefficients corresponding to the number of 4 taps can be outputted, and the arithmetic results are totaled by an adder 20 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting a feature contained in supplied data, delaying the data in consideration of the feature, multiplying the delayed data by a plurality of taps, and multiplying the data by a plurality of taps. The present invention relates to an adaptive filter device and a signal processing method for performing an adaptive filter process by summing sums,
For example, it is suitable for use in a motion adaptive filter or the like that performs signal processing adapted to the motion of an image target.

[0002]

2. Description of the Related Art With the development of digital technology in recent years, it has become common to digitize television signals and perform various signal processing. One example of digital processing for the television signal is processing by a digital filter. The filter processing includes a low-pass filter used for interpolation processing such as pixel or horizontal line thinning or horizontal line interpolation processing. Filters are also used for processing such as correction by contour enhancement of an image and removal of noise included in an image signal.

[0003] In the above-described processing, a finite impulse response (hereinafter, referred to as FIR) is generally used.
Filters are often used. The speed of the arithmetic processing can be further improved by using a method called pipeline processing in which the FIR filters are processed in parallel at the same time. An FIR filter is a delay element (for example,
Shift register), a multiplier and an adder to simplify the configuration of the device in signal processing using an LSI such as a general-purpose DSP (Digital Signal Processor: hereinafter referred to as DSP), The signal processing function is improved from the conventional one.

On the other hand, in high-efficiency coding for compressing the amount of information of a television signal and transmitting the same, and in TV system conversion processing for converting the number of fields of a television signal, encoding efficiency is improved, In order to reduce distortion due to insertion processing, motion adaptive processing is generally used in digital signal processing. In this motion adaptation processing, for example, a numerical value called a motion vector is detected as an amount obtained by combining a movement amount of the target and a moving direction of the target in a video. The detection method is
There are a gradient method for obtaining a moving amount based on an image gradient and a block matching method for checking the coincidence of a two-dimensional pattern in block units. As described above, the television signal is subjected to motion compensation, field interpolation, and the like using the motion vector detected in the digital signal processing.

In general, the motion adaptation process processes an image represented by a television signal in units of blocks. In this block, 8 pixels × 8 lines or 16 pixels × 16 lines are often used as one block unit.

[0006]

As described above, an object (pixel) in an image often changes according to a motion vector. Therefore, if motion adaptation processing is performed on an image in a field unit or a frame unit for each block unit, for example, a block including a target becomes a block not including a target due to movement of the target. In other words, a block that does not include surrounding objects becomes a block that includes a new object. In some cases, data of a block to be read is shifted in data to be read across a plurality of blocks, and if the data is read as it is, the data is read due to a discontinuity in area. It can be seen that even if signal processing is performed on each block, the result of this signal processing loses signal continuity at block boundaries. In the FIR filter processing, which is a filter processing for an input signal having a finite length such as 8 pixels or 16 pixels in block units, when motion is involved, the signal becomes discontinuous at the block boundaries as described above. As a result, pipeline processing for signals in the DSP cannot be performed due to such discontinuities in signals. That is, when performing the motion adaptation process on the data, the configuration of the normal FIR filter cannot be applied.

[0007] The filter for the motion adaptive processing is adapted to the number of taps of the filter so as to enable parallel processing.
It has a structure of RAM (Random Access Memory: RAM), a multiplier, and an adder. However, in this case, the motion adaptive filter is used in proportion to the number of taps.
The number of RAM increases. As a result, the circuit scale of the motion adaptive filter increases, and in reality, only a simple filter of about two taps can be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an adaptive filter device and a signal processing method capable of solving such a drawback of the prior art and suppressing an increase in circuit scale and performing accurate motion adaptive processing.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention divides supplied data into blocks and detects a quantitative feature to be adapted from data in the divided blocks. A memory means for storing data in an adaptive filter device for performing adaptive filter processing by delaying and multiplying data in consideration of this feature amount by a plurality of taps and summing up the sum of these data; A write control unit for sequentially writing data and a data read start position are shifted for each of the number of taps formed by the device, and a memory is set while delaying a set of data blocks separated by the number of actual taps used in the device. When reading data from the means, the feature quantity is determined by the reading speed obtained from the relationship between the number of taps formed by this device and the number of taps actually used. Memory control means for performing read control for reading data corresponding to each delay stage from the memory means by the number of taps formed in consideration of the number of taps to be formed, and a delay element for delaying an output read in accordance with the read control for the memory means. A plurality of delay means, a coefficient supply means for supplying a respective multiplication coefficient to each output of the delay element of the delay means, and the number of taps for forming the number of multiplication coefficients output from the coefficient supply means by this apparatus And a coefficient output control means for controlling the output of a multiplication coefficient in consideration of the characteristic amount for each number, a tap means for multiplying each output of the delay element by a coefficient from the coefficient supply means, And an adding means for summing the outputs.

Here, the memory control means reads the data at a speed twice as fast as the data writing speed, and the coefficient output control means controls the coefficient supply means every time each output is outputted from the delay element of the delay means. It is preferable to perform control for switching the output. In this case, for example, if the block size is 4
When the number of taps of the filter is 4 taps,
A hardware eight-tap filter is configured on the hardware to read eight consecutive data at double speed in one block of time to enable continuous output.
By switching, for each delay element output, one sample data for supplying a multiplication coefficient considering a motion amount to a tap as a feature amount in a pixel unit, for example, random processing for each block according to the movement amount and the accompanying Parallel processing.

The memory control means includes write / read selection means for supplying common address information to each of the plurality of memory means in response to a control signal for switching data write / read control at predetermined timing. The memory means, the coefficient supply means and the delay means among the memory means, the coefficient supply means and the delay means which are divided into a plurality of sets, respectively control the memory means and the coefficient supply means in accordance with a predetermined timing, and further read out from the memory means at twice the writing speed Is preferably read at a speed corresponding to a predetermined timing, and the output of the coefficient supply means is switched each time each output is output from the delay element. This also prevents discontinuity that occurs when the data supply is viewed in block units, and enables continuous output.

In the adaptive filter device, the delay means, the tap means and the adding means may use an FIR filter.

In the adaptive filter device according to the present invention, the memory control means writes data supplied to the memory means in response to the write control signal, and reads out data from the memory means for each of the number of taps formed by the device when reading from the memory means. A set of data blocks is shifted by shifting the reading start position and separated by the number of taps formed by this device and the number of taps actually used, and the relationship between the number of taps formed and the number of taps actually used. The read control is performed at the read speed based on. By this data read control, data corresponding to each delay stage is provided to each delay stage of the tap means by the number of taps to be formed. In addition, the memory means performs read control in consideration of a feature amount such as a motion detection amount (or a motion vector or the like). The read data is delayed stepwise by the delay means and supplied to the tap means. Further, the coefficient output control means controls the coefficient supply means to output the coefficient considered including the characteristic amount to the tap means. At this time, a number of coefficients corresponding to the number of taps to be configured are output, but no coefficients are supplied to other parts. When the sum of the multiplication results obtained by the tap means is output by the addition means, the data used for the adaptive processing is not included in both adjacent data blocks. Therefore, the filter processing is performed while maintaining the continuity of the supplied data. Can be done.

Further, according to the present invention, the supplied data is divided into block units, a quantitative characteristic amount to be adapted is detected from the data in the divided blocks, and a delay is applied to the data in consideration of the characteristic amount. In a signal processing method of performing adaptive filtering by multiplying by a plurality of taps and summing up the sum of these data, a data preparation step of preparing data according to a supplied write control signal;
The data read position is shifted for each number of taps formed for the data prepared in the data preparation step, and a set of data blocks divided by the actual number of prepared taps are formed while delaying. A read signal generating step of generating a read control signal for reading data corresponding to each tap at a read speed obtained from a relationship between the number of taps and the number of taps actually used in consideration of a characteristic amount; A data providing step of providing data to each tap in data block units according to a read control signal;
A delay step of delaying the data provided by the data providing step by step, and taps to supply and supply only the number of taps forming a multiplication coefficient respectively supplied to the output obtained step by step in the delay step A coefficient output control step of performing control in consideration of the feature amount of the position, a coefficient providing step of outputting a multiplication coefficient to each tap in accordance with the control of the coefficient output control step, and a multiplication coefficient from the coefficient provision step. A multiplication step of multiplying each output from the delay step,
And an addition step of summing the outputs of the multiplication step.

Here, the data providing step reads out data at a speed twice as fast as the data writing speed, and the coefficient output controlling step includes the steps of starting the coefficient providing step every time each output is output from the delay element in the delay step. It is preferable to perform a control for switching the output of the control. As a result, continuous data provision is ensured, and the multiplication coefficient changes in accordance with the feature value each time the data is output from the delay element, so that the so-called adaptive filter processing in which the feature value is considered can be performed. .

Also, the signal processing method includes an input selection step of selecting a data supply destination before the data storage step, and after this input selection step, each of the data branch destinations in the input selection step is used. The data providing step, the delay step, the coefficient output control step, the coefficient providing step and the corresponding step of the multiplying step are performed simultaneously, and further, in the data providing step,
The read data speed, which is twice as fast as the write speed, is divided by the number of branches to each data supply destination. The coefficient providing step is performed every time each output is output from the delay element in the delay step. It is preferable to switch the multiplication coefficient to be used. As a result, it is possible to operate with a reduced reading speed without changing the total capacity of the memory used for processing.

According to the signal processing method of the present invention, the supplied data is used as write data to be written according to a write control signal, and the write data is prepared as read data. Then, the read control signal is generated so as to be divided into a set of data blocks while delaying data according to the number of taps to be formed and the number of actual taps to be prepared. The read control signal has a read speed corresponding to the relationship between the number of taps and the actual number of taps with respect to the written data, and reads out data corresponding to each delay stage in consideration of the characteristic amount. Generated to be
Therefore, the write data is read in accordance with the read control signal. By reading this data,
For example, it is possible to avoid a possibility that the read data may fall into a so-called data discontinuity that extends over adjacent blocks. Each of the data obtained by performing the delay processing stepwise is supplied with a multiplication coefficient in consideration of the corresponding feature amount, and the calculation is performed using the multiplication coefficient and the data. The signal processing adapted to the characteristic amount is continuously performed by taking the sum of these multiplication results.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an adaptive filter device and a signal processing method according to the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a finite impulse response (FIR) filter is used for data read at random from the memory in block units, and a multiplication coefficient supplied to the FIR filter is supplied from each delay stage. It is characterized in that the signal processing is performed by switching every one output. In this embodiment, the signal processing method is described with reference to FIGS.
This will be described with reference to FIG.

The adaptive filter device 10 includes an FIR filter unit.
12, a memory 14, a memory control unit 16, a multiplication coefficient output unit 18, and a delay element 20 are provided. As the FIR filter 12, for example, a commercially available 8-tap filter having a configuration enabling pipeline processing is used. As shown in FIG. 1, the FIR filter 12 includes a delay unit 12A, a tap unit 12B, and an adder 12q. Delay unit 12A
Includes delay element circuits (DL) 12a to 12h that generate eight stages of delays so as to form an 8-tap FIR filter. In addition, a shift register in which delay stages are provided collectively may be used. The tap section 12B is connected to the supplied multiplication coefficients Ka,..., Kh and the respective delay element circuits (D
L) Eight multipliers 12i that multiply the outputs from 12a to 12h
Includes ~ 12p. The adder 12q adds all eight data supplied from the tap unit 12B.

The memory 14 uses a RAM, and writes data by a write control of a memory control unit 16 described later. The read control controls four pixels of image data with respect to a reference address at the time of writing in units of one block. Is output in which the correction by the motion vector value is considered. In the memory 14, although not shown in detail in FIG.
A data reading period is set. Further, a write address / read address is supplied to the memory 14 from the memory control unit 16 via the terminal A.

The memory control unit 16 includes a changeover switch SW and an adder 16a. Terminal a of the changeover switch SW
Is supplied with a write address via an input terminal 5. The read address supplied via the input terminal 7 is added to one end of the adder 16a. The motion vector value detected from the image is supplied to the adder 16 via the input terminal 9 to the other end of the adder 16. The adder 16 supplies this addition result to the terminal b of the switch SW. The changeover switch SW outputs the write address and the read address supplied to the terminals a and b to the memory 14 and the multiplication coefficient output unit 18 using the enable signal as a changeover control signal. The memory control unit 16 also controls the multiplication coefficient output unit 18 to control the output of the multiplication coefficient.

The multiplication coefficient is previously written in the multiplication coefficient output section 18 so that the multiplication coefficient is output in accordance with the read address supplied from the memory control section 16. However, the part where the multiplication coefficient is actually written as data is written only in four of the eight multiplication coefficients (see FIG. 2 (c)). This is due to the fact that motion detection is performed in units of four pixels and one block with respect to the reference address as described above, and that this adaptive filter device is specified to be used as a four-tap filter.

The delay element circuit (DL) 20 is provided so as not to include components such as noise contained in the supplied signal processing result. The delay element circuit (DL) 20 outputs the supplied data via the output terminal 2. By the way, the delay element circuits (DL) 12a to 12h and the delay element circuits (DL) 20
Are supplied with a common clock signal (not shown). Signals and data supplied through the input terminals 3 to 9 are supplied from a system control unit (not shown). As described above, the configuration of the apparatus can be simplified with a configuration using an FIR filter which is not used in the configuration of one memory and the adaptive filter adapted to the motion than the conventional adaptive filter.

The signal processing of the adaptive filter device 10 will be briefly described with reference to FIG. The input data is supplied to the delay unit 12A via the input terminal 1. FIG. 2A shows the data at the position indicated by reference numeral a in FIG. Delay element circuit
The input data that has passed through the (DL) 12a constitutes an 8-tap filter on hardware according to the write address supplied through the input terminal 5 and the changeover switch SW (terminal b) of the memory control unit 16. , 8 to support 8 taps
The two data are written to the memory 14 after a delay of one delay. The block size in this case is 4 pixels for the written data. In this filter configuration, when the number of taps of the filter to be actually configured is 4 taps, the read speed is 8 continuous in one block time.
The two data are read at double speed and output continuously. In addition, a multiplication coefficient in consideration of a motion amount, for example, is supplied to the tap as a feature amount in units of four pixels in accordance with the four taps.

The data written in the memory 14 after such a relationship is established is read out at the time of reading, as eight data are shifted by one delay so as to correspond to eight taps, and furthermore, the data is stored in the reference address. On the other hand, four pixels that are the same number as the number of taps of the filter to be configured are defined as one block. This block unit is also a block for motion vector detection. By matching the number of data to be read (block size) with the number of data to be used for motion vector detection, that is, by reading every four pixels, a plurality of adjacent blocks can be obtained by taking into account the motion vector that has conventionally occurred. To ensure that no data enters. Here, assuming that the start position of the data block DB is DS for eight consecutive data, the start position is
DS has a relationship of (4n + 1). Here, n is an integer indicating the number of the data block DB. That is, for example, n = 0: DS = 1; n = 1: DS = 5; n = 2: DS = 9; n = 3:
DS = 13; (see FIG. 2 (b)). In order to perform the 4-tap filter processing in this manner, data of two pixels before and after are used in processing of one pixel data.
A data block must be composed of pixel data. The step-like thick line in FIG. 2B indicates the boundary of the data block DB.

The above relationship will be described more specifically.
To the memory 14, a read address from the input terminal 7 and a motion vector value from the input terminal 9 are combined, and a read address corresponding to motion (hereinafter, simply referred to as a read address) is supplied. Here, reference numerals b to i in FIG. 2B indicate positions on the output side from the respective delay element circuits (DL) 12a to 12h, which are the same as reference numerals b to i in FIG. As a result, the data read from the memory 14 corresponding to the read address is
The data enclosing the data structure shown in (b) with a bold line is the arrow R
It is read so that it is supplied to the position on each output side when viewed in the direction. The data reading speed at that time is twice the writing speed, that is, half the writing time. From this speed relationship, data reading takes time.
The data is read out one row at a time, as shown in the data structure of FIG. Actually, for example, when processing data Nos.
Nos. 1 to 8 are read.

The adaptive filter device 10 adjusts timing so as to correspond to data reading from the memory 14 and supplies the multiplication coefficients K1 to K4 to the multipliers 12i to 12p of the tap section 12B. At this time, the supplied multiplication coefficients K1 to K4 are supplied in the relationship shown in FIG. That is, the multiplication coefficients K1 correspond to the data positions surrounded by the thick lines in FIG.
~ K4 is supplied. Thus, the multiplication coefficient output unit 18 may prepare the multiplication coefficient in the same structure as the memory 14 and read the multiplication coefficient according to the read address. However, the symbol "-" in FIG. 2 (c) indicates that there is no data.

When the data and the multiplication coefficient are supplied to the tap section 12B, zero is output from the multiplier supplied with the multiplication coefficient "-", and only the multiplier supplied with the multiplication coefficients K1 to K4. Outputs the operation result. Therefore, only four calculation results are output and used as data of four taps. The adder 12g adds the operation results to obtain a sum. The result of this filtering is output from the adder 12g via the delay element circuit (DL) 20 to the output data (2),.
(12),... Are output.

The data reading shown in FIG. 2 is described for the case where the motion vector value is zero for simplicity.
If data Nos. 1 to 8 and then data Nos. 5 to 12 are read out but the motion vector value is not zero, then data Nos. 5 to 12 will not be read out and different data will be read out. By switching the coefficient for each data, that is, for each pixel, discontinuity of the block boundary can be avoided and the filter processing can be continuously output.

On the other hand, a comparison is made with the conventional 4-tap adaptive filter device 30. The adaptive filter device 30 includes a delay unit 32, a memory unit 34, a tap unit 36, a multiplication coefficient output unit 36, a multiplication coefficient output unit 38, an adder 40, and a switch SW1. The output of the adder 40 is delayed by a delay element circuit (DL) 40, settled as a signal, and output. The delay unit 32 includes delay element circuits (DL) 32a to 32d. The memory unit 34 includes four memories 34a to 34d so as to correspond to the delay element circuit (DL) and to maintain continuity of signals (data) at block boundaries. Similarly, of course, for the tap portion 36,
Multipliers 36a to 36d are provided. Multiplication coefficient output section 3
8. The adder 40 and the delay element circuit (DL) 40 have the same configuration as in the above-described embodiment. Also, changeover switch SW1
Selects one of the memories 34a to 34d according to a write enable signal supplied from the input terminal 4 and a switching signal supplied via the input terminal 4a. Thus, when, for example, data Nos. 1 to 8 are supplied as input data to the memories 34a to 34d via the delay unit 32, the memory 34a stores data Nos. 1 and 5 and the memory 34b stores data Nos.
The memory 34c stores data Nos. 3 and 7, and the memory 34d stores data Nos. 4 and 8, respectively. When data is read from the memory unit 34, the written address is read. At this time, the multiplication coefficient output unit 38 performs the operation by supplying the fixed coefficient to each of the multipliers 36a to 36d. This calculation result is supplied to the adder 40, and the total sum of all is calculated. These series of operations describe a case where no motion vector value is included.

However, in order to consider the motion vector value and to read out data that does not include block boundaries and maintain data continuity, the data is divided and written for each pixel, and the data is written individually. The memory must be provided for the number of taps so that it can be read. Arranging the memories in accordance with the number of taps means that when high-precision filtering is required, the circuit size of the adaptive filter device 30 becomes large.

According to the present invention, as described above, the conventional FI
The R filter, one memory and a memory control unit can perform processing including data continuity and motion vector operations, and can also read out corresponding multiplication coefficients, greatly simplifying the device configuration. Also, a filter having a large number of taps can be easily realized. Also,
The present invention is not limited to the filter processing described above, and can be applied to filter processing in the vertical direction.

Next, another embodiment of the adaptive filter device according to the present invention will be briefly described with reference to FIGS. Portions common to the above-described embodiments are denoted by the same reference numerals, and description thereof is omitted. In this embodiment, the input data supplied from the input terminal 1 is distributed to two systems, and two delay units 12A, a memory unit 14, and a multiplication coefficient output unit 18 are provided so as to perform a filtering process on the distributed input data. The configuration is characterized in that data writing / reading is performed at the same speed by this configuration.

As described above, the delay unit 12A includes a delay unit 120 including delay element circuits (DL) 12a, 12c, 12e, and 12g, and a delay unit including delay element circuits (DL) 12b, 12d, 12f, and 12h. Section 122. In FIG. 4, the tap portion 12B is depicted as being separated, but the actual functions are exactly the same as in FIG. The memory unit 14 divides the odd-numbered data and the even-numbered data by the write enable signal so that the data can be separately written and writes the data into the two memories 14a and 14b. An inverted logic circuit (NOT) 22 is newly provided for the write enable signal so as to correspond to the classification of data. Memory 14a, 1
In 4b, data is read simultaneously when the read enable signal is supplied. Further, the multiplication coefficient output unit 18 has a multiplication coefficient output unit 18a, 18b corresponding to the memories 14a, 14b.
Is provided.

In this case, the same input data as in the previous embodiment is supplied (see FIG. 5A). At this time, in accordance with the write enable signal, data is drawn into the memories 14a and 14b, for example, by dividing the data into odd numbers and even numbers. memory
When 14a stores an odd number, data Nos. 1 to 7, that is, 1, 3, 5, and 7, are regarded as one data block. Next, data Nos. 5 to 11 are written as data blocks (see FIG. 5B). Therefore, the start position DS of the data block has a relationship of (4n + 1). When the memory 14b stores even numbers, data Nos. 2 to 8, namely, 2, 4,
Let 6 and 8 be one data block. Next, data No. 6 ~
12 is written as a data block (see FIG. 5 (d)). In this case, the start position DS of the data block is (4n +
2) Here, the variable n is a data block number and is an integer.

As shown in FIGS. 5C and 5E, two multiplication coefficients are output to the multiplication coefficient output sections 18a and 18b, respectively, corresponding to the positions where the delay element circuits (DL) are adjacent to each other. The multiplication coefficient output units 18a and 18b simultaneously read out and output the corresponding multiplication coefficients to the tap unit 12B. When this result is calculated by the tap unit 12B, a 4-tap filter process is performed in the same manner as in the previous embodiment. This result is shown in FIG.
Output data.

With this configuration, the memory and the multiplication coefficient output unit are divided into two systems. However, the total memory capacity is kept constant, the other configurations are not increased, and the data reading speed is reduced. It will be able to be done in half compared to the case. This makes it possible to more easily realize the filtering process.

[0039]

As described above, according to the adaptive filter device of the present invention, the memory control means writes data supplied to the memory means in response to the write control signal, and forms the data when reading from the memory means. The data reading start position is shifted for each number of taps, and a set of data blocks separated by the number of taps formed by this device and the number of actually used taps are delayed, and the number of formed taps and The read control is performed at a read speed based on the relationship between the number of taps used for. By this data read control, data corresponding to each delay stage is provided to each delay stage of the tap means by the number of taps formed at the read speed obtained from the relationship between the number of taps to be formed and the number of taps actually used. In addition, the memory unit is controlled to read in consideration of a feature amount such as a motion detection amount (or a motion vector or the like). The read data is delayed stepwise by the delay means and supplied to the tap means. Further, the coefficient output control means controls the coefficient supply means to output a coefficient considered including the feature amount to the tap means, and outputs a number of coefficients corresponding to the number of constituent taps,
Since the coefficients are not supplied to the other parts, when the sum of the multiplication results by the tap means is output by the addition means, the data used for the adaptive processing is not included in both adjacent data blocks, and the FIR filter is not included. , The continuity of the supplied data can be maintained and a highly accurate filtering process can be realized.

According to the signal processing method of the present invention, the supplied data is used as write data to be written according to the write control signal, and the write data is prepared as read data. Then, the read control signal is generated so as to be divided into a set of data blocks while delaying data according to the number of taps to be formed and the number of actual taps to be prepared. The read control signal has a read speed corresponding to the relationship between the number of taps and the actual number of taps with respect to the written data, and reads out data corresponding to each delay stage in consideration of the characteristic amount. Generated to be Therefore, the write data is read in accordance with the read control signal. By this data reading, it is possible to avoid a possibility that the read data may fall into a so-called data discontinuity that extends over adjacent blocks. Each of the data obtained by the stepwise delay processing is multiplied by the multiplication coefficient supplied in consideration of the corresponding feature amount, and signal processing adapted to the feature amount is obtained by summing up the multiplication results. It can be performed easily and continuously.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an adaptive filter device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the adaptive filter device shown in FIG.

FIG. 3 is a schematic block diagram of a conventional configuration as a comparative example with respect to the adaptive filter device of FIG. 1;

FIG. 4 is a schematic block diagram of another embodiment of the adaptive filter device shown in FIG. 1;

FIG. 5 is a timing chart for explaining the operation of the adaptive filter device shown in FIG.

[Explanation of symbols]

 10 Adaptive filter device 12 FIR filter unit 14 Memory 16 Memory control unit 18 Multiplication coefficient output unit 12A Delay unit 12B Tap unit 12a to 12h, 20 Delay element circuit (DL) 12i to 12p Multiplier 12q, 16a Adder SW switch

Claims (7)

[Claims] 1. A method according to claim 1, wherein the supplied data is divided into block units, a quantitative characteristic amount to be adapted is detected from the data in the divided block, and a plurality of individual characteristic values are delayed by delaying the data in consideration of the characteristic amount. In an adaptive filter device that performs adaptive filter processing by multiplying by a tap and summing up the sum of these data, the device includes a memory unit that stores the data, a write control that sequentially writes the data, and a write control unit that The data reading start position is shifted for each number of taps to be formed, and is divided by the actual number of taps used in the device.
When reading data from the memory means while delaying a set of data blocks, the characteristic amount is taken into consideration by a reading speed obtained from a relationship between the number of taps formed by the device and the number of taps actually used. A plurality of memory control means for performing read control for reading data corresponding to each delay stage from the memory means by the number of taps to be formed; and a plurality of delay elements for delaying an output read in accordance with the read control to the memory means Number of delay means, coefficient supply means for supplying a respective multiplication coefficient to each output of the delay element of the delay means, and the number of taps for forming the number of multiplication coefficients output by the coefficient supply means in the device And a coefficient output control means for controlling the output of the multiplication coefficient in consideration of the characteristic amount for each of the numbers, and a coefficient from the coefficient supply means for the delay element. An adaptive filter device comprising: tap means for multiplying each of the outputs; and addition means for summing the outputs of the tap means. 2. The apparatus according to claim 1, wherein said memory control means reads out said data at a speed twice as fast as said data write speed, and said coefficient output control means comprises said delay of said delay means. An adaptive filter device, wherein control is performed to switch the output of the coefficient supply means each time each output is output from the element. 3. An apparatus according to claim 1, wherein said memory control means is configured to store address information common to each of said plurality of memory means in response to a control signal for switching write / read control of said data at predetermined timings. The memory control means, wherein the memory means, the coefficient supply means and the delay means among the memory means, the coefficient supply means and the delay means are divided into a plurality of sets, and The apparatus further reads a speed read from the memory means at twice the writing speed at a speed corresponding to the predetermined timing, and each time the respective outputs are output from the delay element. An adaptive filter device for switching the output of said coefficient supply means. 4. The adaptive filter device according to claim 1, wherein said delay means, said tap means and said adding means are FIR filters. 5. The supplied data is divided into block units, a quantitative characteristic amount to be adapted is detected from the data in the divided blocks, and a plurality of individual data are delayed by delaying the data in consideration of the characteristic amount. In a signal processing method for performing adaptive filtering by multiplying by a tap and summing up the sum of these data, the method includes: a data preparation step of preparing the data in accordance with a supplied write control signal; The data read position is shifted for each number of taps formed for the data prepared in the data preparation step, and a set of data blocks divided by the number of actual taps prepared is formed while delaying the set of data blocks. A read control signal for reading data corresponding to each tap at a read speed obtained from the relationship between the number of taps and the number of taps actually used in consideration of the feature amount A read signal generating step of generating; a data providing step of providing the data to each tap in data block units according to the read control signal of the read signal generating step; And a delay step for sequentially delaying, and the number of taps forming a multiplication coefficient supplied to the output obtained in a stepwise manner in the delay step.
A coefficient output control step of controlling the position of the tap to be supplied in consideration of the characteristic amount; a coefficient providing step of outputting the multiplication coefficient to each of the taps in accordance with the control of the coefficient output control step; A signal processing method comprising: a multiplication step of multiplying each output from the delay step by the multiplication coefficient from the step; and an addition step of summing outputs of the multiplication step. 6. The method according to claim 5, wherein the data providing step reads the data at a speed twice as fast as the data writing speed, and the coefficient output control step includes the delay of the delay step. A signal processing method comprising: performing control to switch the output from the coefficient providing step each time each output is output from the element. 7. The method according to claim 5, further comprising an input selecting step of selecting a data supply destination before the data storing step, and branching in the input selecting step after the input selecting step. The data providing step, the delay step, the coefficient output control step, the coefficient providing step and the multiplying step at the respective supply destinations of the received data are performed simultaneously, and the method further comprises: The speed of read data, which is twice as fast as the write speed, is divided by the number of branches of the data to each supply destination. A signal processing method, wherein a multiplication coefficient to be output is switched every time the signal is output.