KR20080029825A - Digital filter - Google Patents

Abstract

A digital filter is provided to reduce unnecessary power consumption by performing an operation with precision suitable a condition of a filter process. A digital filter includes a coefficient storing device(200) storing a filter coefficient multiplying to a process object signal of a filter process or a filter coefficient which is multiplied to a signal generating in a filter processing process. A coefficient re-record controlling device(401) adjusts a re-record of the filter coefficient stored at the coefficient storing device. An operation device performs an operation to perform the filter process using the filter coefficient stored at the coefficient storing device to the process object signal. A filter process control device(402) controls the operation performed by the operation device.

Description

Digital filter {DIGITAL FILTER}

The present invention relates to a digital filter suitable for audio equipment and the like.

Digital filters have many advantages over analog filters, such as integrated circuits, compactness, low cost, and high reliability, and the filter characteristics can be easily adjusted by software processing. This digital filter is realized by, for example, a digital signal processor (DSP) programmed to perform desired filter processing. In recent years, digital filters having a configuration in which a user can freely rewrite filter coefficients used for filter processing have been provided.

Fig. 10 is a block diagram showing the functional configuration of this kind of digital filter. This digital filter is constituted by a DSP programmed to function as this three-band equalizer. Here, the three-band equalizer is obtained by biquad-dependent connection of equalizers EQ0, EQ1 and EQ2 configured by an Infinite Impulse Response (IIR) filter, respectively, to give a desired frequency characteristic to the input audio sample x (n). And output as output audio sample y (n). In addition, Patent Document 1 discloses an IIR filter for such an equalizer. The digital filter shown in FIG. 10 uses delay processing (901 to 912), multiplication processing (921 to 936), and addition processing (941) in each sampling period in order to operate a function as a three-band equalizer. To 943).

In each sampling period, in the multiplication processing 921 to 935, the filter coefficient cEQ00 and the like shown in the figure are multiplied by the output signal value dEQ00 and the like of the delay processing 901 to 911, respectively. In addition, in each sampling period, the addition process 941 adds the respective output values of the multiplication processes 921 to 925, and in the addition process 942, the respective output values of the multiplication processes 926 to 930 are added and added. In the process 943, the respective output values of the multiplication processes 931 to 935 are added. As a result, the signal values dEQ10, dEQ20, and dEQ30 shown in the following formulas (1) to (3) are calculated as the output values of the addition processes 941 to 943, and the signal values are updated in accordance with the calculation result when switching to the next sampling period. This is done.

FIG. 11 schematically shows one filter characteristic of the equalizer EQx (x = 0 to 2) shown in FIG. 10. As shown in Fig. 11, the filter characteristics of one equalizer EQx are specified by the peak frequency f0 at which the gain of the signal to pass is maximum, the gain G at the same peak frequency f0, and the cue Q indicating the sharpness of frequency selection. do. When the target peak frequencies f0, gain G, and cue Q of the equalizer EQx of the xth band (x = 0 to 2) are given, the filter coefficients cEQx0, cEQx1, cEQx2, cEQx3, and cEQx4 used for the same equalizer EQx are , Is calculated by the following equation.

However, A, ω, α, and β are as follows. Also, in the following, Fs is a sampling frequency.

For each of the equalizers EQx (x = 0 to 2), the user uses, for example, a personal computer or the like to filter coefficients cEQx0, cEQx1, cEQx2, cEQx3 and cEQx4 based on the desired pit frequency f0, gain G and cue Q. Can be calculated and written to the coefficient storage unit of the digital filter. When this coefficient writing is performed, the digital filter then functions as a three-band equalizer which performs the calculations of the above expressions 1 to 3 using the filter coefficients written in the coefficient storage unit.

Incidentally, the multiplication processing included in the above formulas (1) to (3), that is, the multiplication processing (921 to 936) in FIG. 10 is executed by using the multipliers in the DSP under time division control. The addition processings included in the above expressions (1) to (3), that is, the addition processings 941 to 943 in Fig. 10, are executed by using the adder in the DSP under time division control. Since the multipliers and adders in the DSP handle data of a finite bit width, an error occurs during calculation anyway. If this arithmetic error is large, it may not be possible to meet the requirements (for example, peak frequency f0, gain G and cue Q) as characteristics of the three-band equalizer. In addition, in particular, a digital filter constituted by an IIR filter such as a three-band equalizer shown in FIG. 10 has an advantage that the amount of calculation is smaller than that of a FIR (Finite Impulse Response) filter, while the calculation error is large. Sometimes it causes an oscillation phenomenon called a limit cycle.

By the way, the arithmetic precision which becomes the divergence of whether the problem, such as the lack of a desired specification and the generation of a limit cycle, will arise is not constant but depends on what filter process is performed. For example, in the case of the IIR filter as shown in FIG. 10, if the peak frequency f0 serving as the center of the pass band is high, a problem does not occur even if the computation accuracy is not so high, but if the peak frequency f0 is low, the computation precision is low. If you do not raise the problem tends to occur. Therefore, when the DSP performs the filter process under various conditions (for example, the peak frequency f0), among the filter processes executed under each of these conditions, the one with the highest computational precision required in order not to cause a problem, that is, Therefore, it is necessary to obtain the calculation precision in the worst case and to ensure the calculation accuracy.

As a method of designing a digital filter in consideration of such a worst case, there have been two methods. The first method is a design method in which the hardware intrinsic arithmetic precision of a DSP arithmetic unit, more specifically, the bit width of a multiplier or an adder is matched to what is needed in a worst case.

The second method, like the first method, does not optimize the hardware configuration of the DSP in accordance with the worst case. In the worst case, the double precision operation is executed by the calculator, and the worst case is performed. This is how to get the computational precision needed in the (worst case). For example, in the three-band equalizer shown in Fig. 10, assuming a worst case, in the second calculation method, if the original arithmetic precision of the multiplier or adder of the DSP does not meet the required arithmetic precision, The DSP performs the double precision operation shown in the following equations (13) to (15) to obtain the required calculation precision.

In Equations 13 to 15, dEQxyL (x = 0 to 2, y = 0 to 4) is a lower bit of the signal value dEQxy (x = 0 to 2, y = 0 to 4), and dEQxyU (x = 0 to 2, y = 0 to 4 are the higher bits of the signal value dEQxy (x = 0 to 2, y = 0 to 4).

[Patent Document 1] Japanese Patent Application Laid-Open No. 2003-110405

By the way, since the above-mentioned first method determines the calculation precision of a multiplier or the like in accordance with the worst case, there is a problem that hardware for calculation becomes large. In addition, there is a problem that power consumption increases with the increase in hardware for computation. In addition, since the above-described second method does not change the scale of hardware for calculation, the scale of hardware can be made smaller than that of the first method, but the number of calculations is required to obtain arithmetic precision in accordance with the worst case. Since the double precision operation is performed by increasing, the power consumption increases. In addition, in either of the first and second methods, the computational accuracy of the digital filter is fixed to the computational accuracy that can withstand use in a worst case. However, in the case of a digital filter in which the user can freely rewrite the filter coefficients, the digital filter may be used even in a condition that is not a worst case (for example, by operating at a high peak frequency f0). . Even in such a case, since the digital filter designed by the first method or the second method performs the calculation with a calculation precision determined in consideration of a worst case, that is, a calculation precision higher than the originally required calculation precision, There is a problem that power is consumed unnecessarily by operation at the operation precision of.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a digital filter which can perform calculation with an arithmetic precision suitable for an execution condition of a filter process, and reduces unnecessary power consumption.

The present invention provides coefficient storage means for storing a filter coefficient multiplied by a signal to be processed in a filter process or a filter coefficient multiplied in a signal generated in a process of the filter process, and the filter coefficient stored in the coefficient storage means. Coefficient rewriting control means for rewriting, calculation means for performing calculation for performing a filter process using the filter coefficients stored in said coefficient storage means to a signal to be processed, and means for controlling the calculation by said calculation means. And a filter processing control means for switching control of arithmetic precision of the calculation by said arithmetic means by changing the use mode of said arithmetic means on the basis of a parameter indicating an execution condition of said filter processing. Provide a filter.

According to this invention, since the calculation precision of the calculation by the calculation means is switched on the basis of the execution condition of the filter processing, when the filter processing is performed under various execution conditions, the filter processing is performed at an appropriate calculation accuracy suitable for the execution condition. Operation is performed to avoid unnecessary power consumption.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

<First Embodiment>

1 is a block diagram showing the configuration of a digital filter as a first embodiment of the present invention. This digital filter is a DSP programmed to perform the filter processing as the three-band equalizer of FIG. 10 previously described to the input audio sample x (n), and output the resulting audio sample y (n). 100, a coefficient storage unit 200, an interface 300, and a control unit 400.

The coefficient storage unit 200 is a means for storing the filter coefficients cEQxy (x = 0 to 2, y = 0 to 4) used for the filter processing as the three-band equalizer shown in FIG. 10, for example, such as EEPROM. It is composed of a rewritable nonvolatile memory.

The data path unit 100 is an apparatus for performing calculation for filter processing as the three-band equalizer of FIG. 10 described above, and includes an arithmetic unit 110 including a multiplier 111, an adder 112, and a register 113. The work RAM 120 and selectors 131 and 132 for selecting input information to be supplied to the multiplier 111 are provided.

Here, the work RAM 120 is a storage device used for the delay processes 901 to 912 of FIG. 10 described above, and includes 2N bits indicating the signal value dEQxy of each node of the 3-band equalizer of FIG. N stores a plurality of data. The multiplier 111 is a device for performing multiplication processes 921 to 936 and the like shown in FIG. 10 described above, and multiplies two N bits of input data to output 2N bits of data. The selector 131 selects among the filter coefficients cEQxy (x = 0 to 2, y = 0 to 4) in the coefficient storage unit 200, and supplies them to the multiplier 111. The selector 132 selects the signal value dEQxy or the input audio sample x (n) read from the work RAM 120 and supplies it to the multiplier 111 in accordance with an instruction from the control unit 400. Here, when the selector 132 supplies the signal value dEQxy read out from the work RAM 120 to the multiplier 111, according to the instruction from the control unit 400, the upper N bits of the 2N bit signal value dEQxy. Alternatively, the lower N bits are selected and supplied to the multiplier 111. The 2N-bit data output from the multiplier 111 is code-extended in the process of being supplied to the adder 112, and becomes 2N + M-bit data to which the integer part M bit is added after the sign bit. The adder 112 and the register 113 function as accumulators which accumulate the 2N + M bits of data and calculate signal values dEQ10, dEQ20, and dEQ30 shown in the following formulas (1) to (3) or (13) to (15). do. The processing of each part in the data path part 100 mentioned above is performed in synchronization with the clock phi of a predetermined frequency supplied from the control part 400.

[Equation 1]

[Equation 2]

[Equation 3]

[Equation 13]

[Equation 14]

[Equation 15]

The interface 300 is a device that transmits and receives a signal with a device external to the digital filter. The digital filter obtains the input audio sample x (n) from the outside by this interface 300, and outputs the output audio sample y (n) obtained by the filter process as a three-band equalizer to the outside. In addition, upon rewriting the filter coefficients in the coefficient storage unit 200, the interface 300 is connected to an external device such as a personal computer, and receives the filter coefficients for rewriting and the rewrite command of the filter coefficients from the external device. It plays a role.

The control unit 400 is a means for controlling the entire digital filter. In a preferred embodiment, the control unit 400 is composed of a CPU, a ROM storing a program executed by the CPU, and a RAM for work. The control unit 400 has a coefficient rewrite control unit 401 and a filter processing control unit 402. These entities are programs executed by the CPU of the control unit 400.

The coefficient rewriting control unit 401 receives a filter coefficient and a filter coefficient rewriting command from the external device via the interface 300 in a state where an external device such as a personal computer is connected to the interface 300. The filter coefficients are means for rewriting the filter coefficients in the coefficient storage unit 200 by one filter coefficient.

The filter processing control unit 402 is a means for controlling the filter processing as the three-band equalizer performed by the data path unit 100. The characteristic of this embodiment is an aspect of control of the filter process performed by this filter process control part 402. FIG. Under the prior art, the calculation precision of the calculation processing of the digital filter is determined in accordance with the execution case of the worst case among the various execution conditions of the filter processing, and the digital filter performs the filter processing under any execution condition. , The calculation for the filter process was performed with this determined calculation precision. In contrast, the filter processing control unit 402 according to the present embodiment performs non-warranty whether the execution condition of the equalizer EQx is a worst case for each of the equalizer EQxs (x = 0 to 2) constituting the three-band equalizer. It is determined whether the case is a non-worst case, and according to the determination result, the calculation precision of the filter processing as the equalizer EQx is determined, and the control of the data path unit 100 is performed so that the filter processing is performed at such calculation precision. . In other words, when the execution condition is a non-worst case, the operator 110 of the data path unit 100 performs a single-precision operation, and the execution condition is a worst case. In this case, the calculation unit 110 of the data path unit 100 performs double precision calculation. In more detail, as follows.

First, each equalizer EQx (x = 0 to 2) constituting the three-band equalizer shown in FIG. 10 described above has a problem that the lower the peak frequency f0 is, the lesser the problem is caused by the lack of a specification (limit cycle) or the like. The arithmetic precision required for performing the filter process without generating the error is high. That is, with respect to the individual equalizer EQx, whether the execution condition is a non-worst case or a worst case is determined by the peak frequency f0, and if the peak frequency f0 is equal to or greater than an arbitrary threshold value, the single precision operation No problem occurs (non-worst case), but if the peak frequency f0 is less than the same threshold value, problems are likely to occur unless double precision calculation is performed (worst case). In this embodiment, the single-precision arithmetic zone which is a range of the peak frequency f0 which does not cause a problem even if the filter processing by a single-precision arithmetic is performed, and the double precision which is a range of the peak frequency f0 which a problem arises when a double precision calculation is not performed. The boundary of the calculation zone is around 500 ms.

In the present embodiment, the peak frequency f 0, which is helpful for the determination of non-worst case / worst case, is not directly given to the digital filter, but is a filter calculated using the peak frequency f 0. Coefficients cEQxy (x = 0 to 2, y = 0 to 4) are supplied to the digital filter. Some of these filter coefficients cEQxy (x = 0 to 2, y = 0 to 4) largely depend on the peak frequency f0. Fig. 2 shows an embodiment of the change in the filter coefficient cEQxy (y = 0 to 4) when the peak center frequency f0 is changed in the IIR filter performing the x-th band of the three-band equalizer. In this figure, the single-precision calculation zone and the double-precision calculation zone are shown together with the filter coefficients cEQxy (y = 0 to 4).

As shown in Fig. 2, the filter coefficients cEQx1 and cEQx3 are highly dependent on the peak frequency f0, so that the filter coefficient cEQx1 is closer to -2.0 as the peak frequency f0 is lower, and the filter coefficient cEQx3 is lower as the peak frequency f0, Getting close to 2.0 Therefore, if an appropriate threshold value is set and, for example, the filter coefficient cEQ1 is less than the same threshold value, the double precision operation is performed, and if the filter coefficient cEQ1 is greater than or equal to the threshold value, the single precision operation is performed in the double precision operation zone and the single precision operation zone. It can be seen that an appropriate calculation precision can be selected. Therefore, in the present embodiment, the filter processing control unit 402 compares the filter coefficient cEQx1 with the threshold value of -1.99, and performs double precision operation when cEQx1 <-1.99 and single precision operation when cEQx1≥-1.99, and calculates the precision for the filter process. It is to be selected as.

Fig. 3 shows the validity of the threshold value -1.99 used in this case. When the filter coefficient cEQx1 is calculated for various combinations of the queue Q and the gain G in the range where the pit frequency f0 is 1000 Hz or less, the filter coefficient The number of times cEQx1 is less than -1.99. As shown in FIG. 3, in the region where the peak frequency f0 is higher than 650 Hz, the filter coefficient cEQx1 does not fall below -1.99 even if the cue Q and the gain G are combined in any combination. And the filter coefficient cEQx1 starts to fall below -1.99 when the peak f0 becomes 650 Hz or less. Therefore, as described above, if the double-precision calculation is performed when the filter coefficient cEQx1 is less than -1.99, it is guaranteed that the double-precision calculation is always performed when the peak frequency f0 is 500 Hz or less.

In addition to the functions described above, the filter processing control unit 402 supplies the clock? To be supplied to the data path unit 100 for a period until the next sampling period starts when all the filter processing to be executed within one sampling period is completed. Stops and avoids unnecessary power consumption.

The above is the detail of the structure of the digital filter which concerns on this embodiment.

Next, operation | movement of this embodiment is demonstrated. 4 is a state transition diagram showing the operation of the filter processing control unit 402 in the present embodiment. In the present embodiment, the filter processing control unit 402 executes the filter process as equalizer EQx (x = 0 to 2) in the data path unit 100 in each sampling period, and executes one audio sample y (n). Output it.

DSP Operation Idle State DSPIDLE is a state waiting for all processing to be executed within one sampling period to end and the next sampling period to begin. The filter processing control unit 402 stops the supply of the clock phi to the data path unit 100 in the DSP operation idle state DSPIDLE. In this DSP operation idle state DSPIDLE, if the FS flag indicating the start of the sampling period is asserted, the filter processing control unit 402 refers to the filter coefficient cEQ01 in the coefficient storage unit 200, and cEQ01≥- In the case of 1.99, the state is shifted to the single-precision arithmetic state EQ0. In the case of cEQ01 <-1.99, the state is shifted to the double-precision arithmetic state BIEQ0. Then, the supply of the clock phi to the data path section 100 is started.

In the single-precision arithmetic state EQ0, the filter processing control unit 402 executes the single-precision arithmetic of the above-described equation (1) to the data path unit 100, and executes the output signal value dEQ10 of the equalizer EQ0 obtained as a work RAM ( 120 is stored in the first calculation result storage area. In the double-precision arithmetic state BIEQ0, the double-precision arithmetic expression (13) described above is executed in the data path unit 100, and the resultant output signal value dEQ10 of the equalizer EQ0 is obtained as a first operation in the work RAM 120. It is stored in the result storage area.

When the single-precision arithmetic state EQ0 or the double-precision arithmetic state BIEQ0 ends, the filter processing control unit 402 refers to the filter coefficient cEQ11 in the coefficient storage unit 200, and cStates a single-precision arithmetic state when cEQ11≥-1.99. Transition to EQ1. The output signal value dEQ20 of the equalizer EQ1 is calculated in the data path unit 100 by the single-precision calculation of Equation 2 described above, and the output signal value dEQ20 is stored in the second operation result storage area in the work RAM 120. Save it. On the other hand, when cEQ11 <-1.99, the state is shifted to the double precision arithmetic state BIEQ1. The output signal value dEQ20 of the equalizer EQ1 is calculated by the double-precision calculation of Equation 14 described above, and the output signal value dEQ20 is stored in the second operation result storage area in the work RAM 120.

When the single-precision arithmetic state EQ1 or the double-precision arithmetic state BIEQ1 is completed, the filter processing control unit 402 refers to the filter coefficient cEQ21 in the coefficient storage unit 200, and cStates a single-precision arithmetic state when cEQ21≥-1.99. Transition to EQ2. Then, the output signal value dEQ30 of the equalizer EQ2 is calculated in the data path unit 100 by the single-precision calculation of Equation 3 described above, and the output signal value dEQ30 is stored in the third operation result storage area in the work RAM 120. Save it. On the other hand, when cEQ21 <-1.99, the state is shifted to the double precision arithmetic state BIEQ2. Then, the signal value dEQ30 of the equalizer EQ2 is calculated by the double precision calculation of the above-described equation (15), and the output signal value dEQ30 is stored in the third operation result storage area in the work RAM 120.

When the single-precision arithmetic state EQ2 or the double-precision arithmetic state BIEQ2 ends, the filter processing control unit 402 transitions the state to the fade out / fade in arithmetic state FADE. Then, the multiplication process 936 shown in FIG. 10 is executed by the data path unit 100, and the audio sample y (n) is output to the outside of the digital filter. In addition, in order to execute the delay processes 901 to 912 of FIG. 10 described above, in the work RAM 120, for example, the signal value dEQ01 is moved to an area for storing the signal value dEQ02, and the signal value dEQ00 is moved. Move to an area for storing signal value dEQ01; … The storage area of each signal value dEQxy is changed in the same state as. Further, the signal values dEQ10, dEQ20, and dEQ30 stored in the first to third operation result storage areas in the work RAM 120 are stored in the areas formed for the respective signal values. Then, the input audio sample x (n) is selected by the selector 132 and stored in the area for the signal value dEQ00 in the work RAM 120. In the next sampling period, the signal value dEQxy of each storage area in which the contents are updated in this manner is used for the calculation of the above-described formulas (1) to (3) or the above-described formulas (13 to 15). When the fade out / fade in operation state FADE is completed, the filter processing control unit 402 transitions the state to the DSP operation idle state DSPIDLE.

By the way, in this embodiment, even in the period in which the digital filter is performing the filter process, the filter coefficients in the coefficient storage unit 200 are updated through the interface 300, whereby the equalizer EQx (x = 0 to 2) Switching between single-precision arithmetic and double-precision arithmetic may occur with either of the filter processes. In this case, the filter processing control unit 402 causes the data path unit 100 to perform the fade out process in the fade out / fade in operation state FADE. This fade-out process is a process of gradually reducing the multiplication coefficient FADE from 1 to close to 0 by multiplying the output signal value dEQ30 of the equalizer EQ2 in the multiplication process 936 by using a predetermined number of sampling periods.

When this fade-out process is completed and the multiplication factor FADE becomes 0, the filter processing control unit 402 switches the state to the work RAM when the state transitions to the DSP operation idle state DSPIDLE in the immediately subsequent sampling period. Transition to initialization state MEMCLR. In this work RAM initialization state MEMCLR, the filter processing control unit 402 initializes the signal value dEQxy of each node of the three-band equalizer shown in FIG. 10 previously stored in the work RAM 120 of the data path unit 100. . After the initialization is completed, the filter processing control unit 402 causes the data path unit 100 to perform the fade in process when the state becomes the fade out / fade in operation state FADE in the immediately following sampling period. This fade-in process is a process of gradually increasing the multiplication coefficient FADE from 0 to multiply the output signal value dEQ30 of the equalizer EQ2 by a predetermined number of sampling periods from zero to close to one.

As described above, when switching between single-precision and double-precision operations occurs, the signal value in the work RAM 120 is initialized after the fade-out process is performed, and the filter process as a three-band equalizer is resumed after the fade-in process. Therefore, it is possible to prevent the noise caused by switching of the calculation precision from the output audio sample y (n).

5 and 6 are time charts showing specific operation examples of the present embodiment. In the example shown in FIG. 5, since the execution conditions of the equalizer EQx (x = 0 to 2) are all worst cases, and the filter coefficients cEQx1 (x = 0 to 2) are all less than -1.99, one sampling is performed. During the period, double precision arithmetic states BIEQ0, BIEQ1, BIEQ2, fade out / fade in arithmetic state FADE and DSP arithmetic idle state DSPIDLE occur. In contrast, in the example shown in FIG. 6, all of the execution conditions of the equalizer EQx (x = 0 to 2) are non-worst cases, and the filter coefficients cEQx1 (x = 0 to 2) are all -1.99. As a result, the single-precision arithmetic states EQ0, EQ1, EQ2, the fade out / fade in arithmetic state FADE, and the DSP arithmetic idle state DSPIDLE occur during one sampling period. Here, as shown in the above-described equations 1 to 3 and the above-described equations 13 to 15, the number of times of multiplication processing performed by the single-precision arithmetic state EQx (x = 0 to 2) is double precision calculation. It is 1/2 of the number of multiplication processes performed in state BIEQx (x = 0 to 2). Therefore, the duration of the single-precision arithmetic state EQx (x = 0 to 2) is about 1/2 of the duration of the double-precision arithmetic state BIEQx (x = 0 to 2). For this reason, as shown, when the execution condition of equalizer EQx (x = 0-2) is a non-worst case (FIG. 6), when it is a worst case (FIG. 5) In comparison, the period during which the clock phi is supplied to the data path unit 100 is shortened, and power consumption is reduced.

Next, with reference to FIG. 7, the aspect of the multiplication process of the filter coefficient cEQ and signal value dEQ performed under control by the filter process control part 402 is demonstrated. In FIG. 7, cEQ is the filter coefficients cEQxy (x = 0 to 2, y = 0 to 4) used for the multiplication processing (921 to 936) of the three-band equalizer shown in FIG. 10, and dEQ is the same multiplication processing (921 to The signal value dEQxy (x = 0 to 2, y = 0 to 4) used for the 936 is shown.

In the single-precision arithmetic state EQx (x = 0 to 2), the filter processing control unit 402 causes the data path unit 100 to execute only the processing of "higher-order calculation" shown in FIG. For example, when the data path unit 100 calculates the signal value dEQ10 of the above-described equation (1) in the single-precision arithmetic state EQ0, the filter processing control unit 402 writes an initial value 0 to the register 113. . Next, the filter processing control unit 402 supplies the multiplier 111 with the upper N bits of the filter coefficient cEX00 in the coefficient storage unit 200 and the signal value dEQ00 in the work RAM 120 through the selectors 131 and 132, respectively. And multiplication processing of both is performed. As a result, the multiplier 111 outputs 2N bits of data representing the multiplication result cEQ00 x dEQ00. The filter processing control unit 402 sign-extends the 2N bits of data to 2N + M bits of data, and causes the adder 112 and the register 113 to accumulate the data.

Next, the filter processing control unit 402 supplies the upper N bits of the filter coefficient cEX01 in the coefficient storage unit 200 and the signal N dEQ01 in the work RAM 120 to the multiplier 111 through the selectors 131 and 132, respectively. The multiplication process of both is performed, and the adder 112 and the register 113 perform accumulation of cEQ01 x dEQ01 as a result of this multiplication. The filter processing control unit 402 causes the data path unit 100 to perform multiplication processing cEQ02 x dEQ02, cEQ03 x dEQ10, and cEQ04 x dEQ11 and the accumulation thereof in the above-described equation (1) according to the same procedure below. As a result, 2N + M bits of data representing the signal value dEQ10 of the above-described equation (1) are obtained in the register 113. The filter processing control unit 402 stores the data consisting of the upper N bits of the 2N + M bits of data and the lower N bits of all 0s as the signal value dEQ10 in the first operation result storage area in the work RAM 120. As mentioned above, although the aspect of the multiplication process in single-precision arithmetic state EQ0 was demonstrated, the arithmetic processing of Formulas 2 and 3 previously published also in the same aspect is performed also in single-precision arithmetic states EQ1 and EQ2.

The above is the aspect of the calculation of the filter process performed in a non-worst case.

On the other hand, in the double-precision arithmetic state BIEQx (x = 0 to 2), the filter processing control unit 402 divides the signal value dEQ into the upper N bits and the lower N bits (including all the sign bits), and the same multiplier 111. ), Multiplication processing of the lower bits of the coefficient cEQ and the signal value dEQ ("lower calculation" in FIG. 7), and multiplication processing of the higher bits of the coefficient cEQ and the signal value dEQ ("higher calculation" in FIG. 7). It is executed sequentially, and multiplication processing is performed with arithmetic precision twice the arithmetic precision corresponding to the bit width N of the multiplier 111. The operation of the double-precision arithmetic state BIEQ0 is described as follows.

First, the filter processing control unit 402 writes an initial value 0 to the register 113. Next, the filter processing control unit 402 supplies the multiplier 111 with the N-bit filter coefficient cEX00 in the coefficient storage unit 200 through the selector 131. The filter processing control unit 402 also supplies the multiplier 111 with the lower N bits of the 2N bit signal value dEQ00 in the work RAM 120 via the selector 132. Then, the multiplier 111 performs a multiplication process on the lower N bits of the filter coefficient cEX00 and the signal value dEQ00. As a result, the multiplier 111 outputs 2N bits of data representing the multiplication result. Next, the filter processing control unit 402 causes the sign expansion of the multiplication result to generate a signal value of 2N + M bits, and comprises the adder 112 and the register 113 of the signal value of 2N + M bits. The accumulator is supplied to cause accumulation. As a result, 2N + M bits of data representing the multiplication result of the filter coefficient cEX00 and the lower N bits of the signal value dEQ00 are stored in the register 113. Then, before the execution of "upper calculation", the data in this register 113 is shifted to the lower bit side by N-1 bits to be the original 1/2 ^N-1 data.

Next, the filter processing control unit 402 causes the data path unit 100 to execute "higher-order calculation" as follows. First, the filter processing control unit 402 supplies the multiplier 111 with the N-bit filter coefficient cEX00 in the coefficient storage unit 200 through the selector 131. The filter processing control unit 402 also supplies the multiplier 111 with the upper N bits of the 2N bit signal value dEQ00 in the work RAM 120 via the selector 132. Then, the multiplier 111 performs a multiplication process of the upper N bits of the filter coefficient cEX00 and the signal value dEQ00. As a result, the multiplier 111 outputs 2N bits of data representing the multiplication result. Next, the filter processing control unit 402 causes the signal expansion of the multiplication result to generate a signal value of 2N + M bits, and comprises the adder 112 and the register 113 of the signal value of 2N + M bits. The accumulator is supplied to cause accumulation. As a result, in the register 113, the data obtained by adding the multiplication result of the lower N bits of the filter coefficient cEX00 and the signal value dEQ00 and the multiplication result of the filter coefficient cEX00 and the upper N bits of the signal value dEQ00, that is, double precision calculation The multiplication result of the filter coefficient cEX00 and the signal value dEQ00 by is obtained. According to the same aspect below, each multiplication process and their accumulation process shown in Equation 13 published above are performed. The output signal value dEQ10 of the equalizer EQ0 obtained in the register 113 is thereby stored in the first operation result storage area in the work RAM 120.

As mentioned above, although the aspect of the multiplication process in double-precision arithmetic state BIEQ0 was demonstrated, the arithmetic process of Formula (14) and 15 previously published also in double-precision arithmetic states BIEQ1 and BIEQ2 is performed similarly.

The above is the aspect of the calculation of the filter process performed in a worst case.

As described above, according to the present embodiment, based on the filter coefficient, whether the execution condition of the digital filter is a worst case or a non-worst case that requires high computational accuracy is required. The filter processing is determined using a common operator 110, by a double precision operation for a worst case, or a single precision operation with low power consumption for a non-worst case. . Therefore, both the filter processing in the worst case and the filter processing in the non-worst case can be performed without increasing the hardware scale and generating unnecessary power consumption. Can be. In addition, in this embodiment, when the filter process as a three-band equalizer consists of each folder process as a smaller equalizer EQx (x = 0-2), execution conditions are individually performed with respect to each small filter process. Since it is determined whether the worst case or the non-worst case is used and the calculation precision is selected, the filter processing can be performed by a single precision calculation with a great deal of power, and there is an advantage that delicate power saving is possible.

<2nd embodiment>

It is a figure which shows the aspect of the multiplication process of the filter coefficient cEQ and signal value dEQ in the digital filter which concerns on 2nd Embodiment of this invention. In the first embodiment, when the filter coefficient cEQ is N bits and the signal value dEQ is 2 N bits, and the filter processing is performed by double precision calculation, the signal value dEQ is divided into the upper N bits and the lower N bits, and the coefficient cEQ and The latter multiplication process and the coefficient cEQ and the former multiplication process were executed sequentially, and the multiplication result was accumulated. In contrast, in the present embodiment, the filter coefficient cEQ is set to 2N bits, the signal value dEQ is set to N bits, and the number of bits of the filter coefficient cEQ used for multiplication with the signal value dEQ is changed to perform the single precision operation / double precision operation. Switch over.

When the filter process is performed by a single precision operation, only the "upper calculation" shown in FIG. 8 is executed. That is, the multiplication of the upper N bits of the filter coefficient cEQ and the signal value dEQ is performed by the multiplier 111, the sign expansion of the multiplication result is performed, and accumulated by the accumulator made up of the adder 112 and the register 113.

When the above processing is performed for each combination of the filter coefficient cEQxy and the signal value dEQxy in the above-described equation (1), 2N + M bits of data representing the signal value dEQ10 are obtained in the register 113. The filter processing control unit 402 stores the upper N bits of this data in the first operation result storage area in the work RAM 120 as the signal value dEQ10. The operation of calculating the signal values dEQ20 and dEQ30 shown in the above expressions (2) and (3) is basically the same.

On the other hand, when the filter process is performed by double precision calculation, "lower calculation" and "higher calculation" shown in FIG. 8 are executed sequentially. First, multiplying the lower N bits of the filter coefficient cEQ by the signal value dEQ is performed by the multiplier 111, and the result of the multiplication is code-extended, and is accumulated by an accumulator made up of the adder 112 and the register 113. Then, prior to " upper calculation, " the data in the register 113 is shifted to the lower bit side by N-1 bits to obtain original 1/2 ^N-1 data. Next, multiplying the upper N bits of the filter coefficient cEQ and the signal value dEQ by the multiplier 111, the multiplication result is code-expanded, and accumulated by the accumulator made up of the adder 112 and the register 113. .

When the above processing is performed for each combination of the filter coefficient cEQxy and the signal value dEQxy in the above-described equation (1), 2N + M bits of data representing the signal value dEQ10 are obtained in the register 113. The filter processing control unit 402 stores the upper N bits of this data in the first operation result storage area in the work RAM 120 as the signal value dEQ10. The operation of calculating the signal values dEQ20 and dEQ30 shown in the above expressions (2) and (3) is basically the same.

Also in the present embodiment, since the single-precision operation / double-precision operation is switched according to whether the execution condition of the filter processing is a non-worst case or a worst case, the hardware is not scaled up. It is possible to perform the filter processing in the non-worst case and the worst case, and also to avoid the unnecessary power consumption in the non-worst case.

Third Embodiment

FIG. 9 is a state transition diagram showing the operation of the filter processing control unit 402 (see FIG. 1) in the digital filter according to the third embodiment of the present invention. In the first embodiment, for each equalizer EQx (x = 0 to 2), it is determined whether the execution condition of the filter process is a non-worst case or a worst case, and for each equalizer. Arithmetic precision was selected. On the other hand, in this embodiment, arithmetic precision is switched collectively about the whole process of equalizer EQx (x = 0-x).

In more detail, the filter processing control unit 402 refers to the filter coefficient cEQx1 (x = 0 to 2) in the coefficient storage unit 200 at the start of the sampling period. When all of the filter coefficients cEQx1 (x = 0 to 2) are equal to or greater than -1.99, the state is subsequently sequentially transitioned to the single-precision arithmetic states EQ0, EQ1, and EQ2, and the equalizer EQx (x is performed by single-precision arithmetic. The filter process of = 0 to 2) is executed. On the other hand, in the case of less than -1.99, which is at least one of the filter coefficients cEQx1 (x = 0 to 2), the state is subsequently sequentially transitioned to the double precision calculation states BIEQ0, BIEQ1, and BIEQ2, and the equalizer EQx ( The filter process of x = 0-2 is performed.

Also in this embodiment, the filter processing can be performed in a non-worst case and a worst case without using hardware on a large scale, and it is also useful for a non-worst case. You can avoid the power consumption. In addition, since this embodiment does not switch individual arithmetic precision with respect to each of equalizer EQx (x = 0-x) similarly to the said 1st embodiment, it is not possible to perform delicate power saving, In comparison, the control is simple.

<Other embodiments>

As mentioned above, although each embodiment of this invention was described, other embodiment may exist other than this invention. For example:

(1) In the above embodiment, the execution condition of the filter process is divided into two stages, a non-worst case and a worst case, and the single-precision operation or the double-precision operation depends on where the execution condition belongs. To choose. However, by dividing the execution condition of the filter process into three or more steps, and the execution condition becomes strict, the double precision operation, the triple precision operation,... … In such a state, the calculation precision may be increased.

(2) In the above embodiment, the filter coefficients are used as parameters representing the execution conditions of the filter processing. However, when the digital filter can obtain the peak frequency f0, the gain G, the cue Q, and the like of the filter processing from the outside, the parameters are applied to these parameters. Based on the execution condition of the filter process (non-worst case / worst case), the calculation precision may be selected.

(3) An automatic mode and a manual mode that can be set by an external operation are provided in the digital filter, and in the manual mode, the equalizer EQx (x = 0 to ~), for example, in accordance with the input of a command via the interface 300 or the like. 2) control of operation precision for each of the two), and in the automatic mode, operation precision is switched based on a parameter (filter coefficient in the first embodiment) indicating the execution condition of the filter process as in the first embodiment. Control may be performed.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a digital filter as a first embodiment of the present invention.

Fig. 2 is a diagram showing a relationship between peak frequencies and filter coefficients of an equalizer handled by the same embodiment.

FIG. 3 is a diagram showing the validity of a threshold of filter coefficients for determining whether an execution condition of a filter process is a non-worst case or a worst case in the same embodiment. FIG.

4 is a state transition diagram showing an operation of the filter processing control unit in the same embodiment.

5 is a time chart showing an operation example of the same embodiment;

6 is a time chart showing another example of operation of the same embodiment;

FIG. 7 is a diagram illustrating aspects of multiplication processing of filter coefficients and signal values in the same embodiment. FIG.

Fig. 8 is a diagram showing an aspect of multiplication processing of filter coefficients and signal values performed in the digital filter according to the second embodiment of the present invention.

Fig. 9 is a state transition diagram showing the operation of the filter processing control unit of the digital filter according to the third embodiment of the present invention.

Fig. 10 is a block diagram showing the functional configuration of a digital filter operating as a three byte equalizer.

FIG. 11 is a diagram schematically showing filter characteristics of one equalizer in the same 3-byte equalizer. FIG.

<Explanation of symbols for the main parts of the drawings>

100: data path section

200: coefficient storage unit

300: interface

400: control unit

401: count rewrite control unit

402: filter processing control unit

110: calculator

111: Multiplier

112: adder

113: register

131, 132: selector

Claims (17)

Coefficient storage means for storing filter coefficients multiplied by the signal to be processed in the filter process or filter coefficients multiplied in the signal generated in the process of the filter process; Coefficient rewrite control means for rewriting the filter coefficients stored in the coefficient storage means; Arithmetic means for performing arithmetic operations to perform a filter process using the filter coefficients stored in the coefficient storage means on a signal to be processed; Means for performing control of calculation by the calculation means, the filter performing switching control of arithmetic precision of calculation by the calculation means by changing a mode of use of the calculation means based on a parameter indicating an execution condition of the filter processing Processing control means Digital filter comprising a. The method of claim 1, And said control means performs switching control of said arithmetic precision using said filter coefficient stored in said coefficient storage means as a parameter representing an execution condition of said filter processing. The method of claim 1, The filter processing control means causes the calculation means to perform double-precision calculation when the execution condition of the filter processing indicated by the parameter is the worst case that requires the highest computational accuracy, and the filter indicated by the parameter. And in the case where the execution condition of the processing is a non-warranty case, the computing means performs a single precision calculation. The method of claim 2, The filter processing control means causes the calculation means to perform double precision calculation when the execution condition of the filter processing indicated by the parameter is a worst case that requires the highest computational accuracy, and executes the filter processing indicated by the parameter. And a single precision operation is performed on said calculating means when the condition is a non-worst case. The method of claim 1, The filter processing is constituted by a plurality of smaller filter processing units, and the filter processing control means individually controls the calculation accuracy so that the calculation precision required by each of the small filter processing units is ensured. A digital filter, which performs switching control. The method of claim 2, The filter processing is constituted by a plurality of smaller filter processing units, and the filter processing control means individually controls the calculation accuracy so that the calculation precision required by each of the small filter processing units is ensured. A digital filter, which performs switching control. The method of claim 3, The filter processing is constituted by a plurality of smaller filter processing units, and the filter processing control means individually controls the calculation accuracy so that the calculation precision required by each of the small filter processing units is ensured. A digital filter, which performs switching control. The method of claim 4, wherein The filter processing is constituted by a plurality of smaller filter processing units, and the filter processing control means individually controls the calculation accuracy so that the calculation precision required by each of the small filter processing units is ensured. A digital filter, which performs switching control. The method of claim 1, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 2, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 3, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 4, wherein The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter, characterized in that the switching control of arithmetic precision is performed collectively with respect to the small-scale filter processing. The method of claim 5, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 6, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 7, wherein The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method of claim 8, The filter process is constituted by a plurality of smaller filter processes, and the filter process control means includes the plurality of filter processes so that the highest computational precision among the computational precision required by the plurality of small filter processes is ensured. A digital filter characterized by performing switching control of arithmetic precision collectively with respect to a small filter process. The method according to any one of claims 1 to 16, It has a manual mode and an automatic mode which can be set by the operation from the outside, In the said manual mode, switching control of the said operation precision is performed according to the operation from the outside, In the said automatic mode, the parameter which shows the execution conditions of the said filter process And the switching control of the precision of the said arithmetic processing based on the control.

Images