JP3880807B2 - Digital filter and processing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital filter and a processing method thereof, and more particularly to a digital filter executed by a general-purpose microcomputer or DSP and software thereof and a processing method thereof.
[0002]
[Prior art]
In recent years, the operating frequency of general-purpose microcomputers and DSPs (digital signal processors) has increased, and general-purpose microcomputers incorporating multimedia instructions such as product-sum operation instructions have begun to appear. Along with this, the filter processing that has been conventionally performed by dedicated hardware has been realized by a general-purpose microcomputer, DSP, and software. In general-purpose microcomputers and DSPs, digital filter processing is generally realized by a ring buffer type FIR (finite impulse response type digital filter).
[0003]
Recently, as described above, multimedia processing such as audio, image, and music codec has been performed by software using a general-purpose microcomputer or DSP. In order to execute applications, it has become necessary to further speed up software processing. In addition, the operating frequency of microcomputers and DSPs has been increased and the power consumption has been reduced, and multimedia processing has also been installed in portable devices, and the power consumption has been further reduced along with the size of the memory used. It is becoming required.
[0004]
Here, a general digital filter processing method using a general-purpose microcomputer will be described.
[0005]
FIG. 7 is a configuration diagram of an FIR type digital filter having a delay number p. a0 to ap are filter coefficients (tap coefficients), and Z-1 is a unit delay element. The output yn with respect to the input Dn of this digital filter can be expressed by the following arithmetic expression.
yn = a0 * Dn + a1 * Dn-1 + a2 * Dn-2 +... + ap-1 * Dn- (p-1) + ap * Dn-p
FIG. 8 is a block diagram of a conventional digital filter. A digital filter of the conventional example shown in FIG. 8 includes a coefficient memory 12 for storing the filter coefficients a0 to ap shown in FIG. 7, and a data RAM (delayer) 11 for storing input data and holding delay data by unit delay elements. A write pointer P1 for designating the write address of the input data to the data RAM 11, a read pointer P2 for designating the address of the input data or delay data to be read when performing the product-sum operation for each tap, and the read input data or A multiplier register 15 for holding delay data, a coefficient pointer P3 for designating an address of a filter coefficient to be read from the coefficient memory 12 when performing a product-sum operation for each tap, a multiplicand register 16 for holding the read filter coefficient, To the sum calculator (multiplier 13, adder 14, result register 17) It is configured Ri.
[0006]
Note that an example of a digital filter that has a similar configuration, has symmetrical filter coefficients, and does not have a product-sum operation function, reduces the number of multiplications to shorten the processing time. It is shown in the publication.
[0007]
FIG. 9 shows a configuration of a ring buffer, a pointer, and a corresponding coefficient memory 12 when the data RAM 11 is generally used in a digital filter in a conventional general-purpose microcomputer and is configured in a ring buffer format.
[0008]
Here, the ring buffer is configured by (p + 1) buffers, which are a combination of a delay buffer having a delay number p and an input data buffer, and the coefficient memory 12 is configured by the same number as the ring buffer (number of taps (p + 1)).
[0009]
P1 is a write pointer indicating an address when writing input data to the ring buffer. P2 is a read pointer indicating the address of the delay data read when performing the product-sum operation for each tap. P3 is a coefficient pointer indicating a filter coefficient to be read out in the product-sum operation for each tap.
[0010]
The read pointer P2 designates the same buffer position as that of the write pointer P1 at the initial stage of the product-sum operation, and stores data to be multiplied by the tap coefficient for the product-sum operation starting from the initial position. Indicates the position.
[0011]
Time series input data D1, D2, D3, D4,. . . . Dp, Dp + 1, Dp + 2, Dp + 3, Dp + 4. . . . Is stored in this digital filter as follows. First, the data D1 is stored in a buffer located at the extreme end on the one end X2 side of the data RAM. Data D2, D3, D4,. . . . . . . Dp and Dp + 1 are sequentially written in the Y2 direction from the buffer at the end on the X2 side where the data D1 is stored. Therefore, the data Dp + 1 is stored in the outermost buffer on the X1 side of the buffer. This completes the data writing position. The next data Dp + 2 is overwritten on the data D1. Thereafter, data Dp + 3, Dp + 4. . . . Is overwritten on the data D2 and D3. (D1), (D2), (D3). . . (Dp + 1) is data written at that position before overwriting.
[0012]
In the above data storage, the data storage position is designated by the write pointer P1. That is, the write pointer P1 first designates the endmost buffer on the X2 side of the data RAM 11. Next, the write pointer P1 designates a buffer adjacent to the X2 side end buffer of the data RAM 11 in the X1 direction. Thereafter, the write pointer P1 is sequentially shifted in the X1 direction to sequentially specify the buffers. Then, after designating the buffer at the extreme end in the X1 direction, the buffer at the extreme end in the X2 direction is designated, and then the shift in the X1 direction is performed. In FIG. 9, the write pointer P1 currently designates the third buffer from the end on the X2 side. Thereby, the data Dn is overwritten on the previously stored data D3.
[0013]
In the product-sum operation, the multiplication of the data and the tap coefficient starts from the data designated by the normal write pointer P1, and is performed in the reverse direction with respect to the data storage order. That is, the read pointer P2 has the same value as the write pointer P1 at the initial stage of the product-sum operation, and thereafter shifts in the X2 direction. When the read pointer P2 points to the X2 side endmost buffer, the read pointer P2 next points to the X1 side endmost buffer. In FIG. 4, until the next data Dn + 1 is overwritten on the data Dn-p, the read pointer P2 is sequentially transferred to the data Dn, Dn-1, Dn-2, Dn-3, Dn-4, Dn. -Five,.. . . . , Dn-p is specified. As a result, the product sum a0Dn + a1Dn-1 + a2Dn-2 + a3Dn-3 +. . . + apDn-p is calculated.
[0014]
In the digital filter in the case where the data RAM is configured in a ring buffer format, data is arranged in a ring shape in p + 1 delay elements (buffers). For example, in the current data arrangement shown in FIG. 9, when the first input data Dn-p and the last input data Dn are arranged side by side and both ends X1 and X2 are connected, Dn-p Data up to Dn is Dn-p,. . . , Dn-3, Dn-2, Dn-1, Dn are arranged in a ring. Although this ring-like array can filter large amounts of data sequentially with a small number of buffers, pointer management is complex and each time the pointer is shifted, the pointer is at the end of the buffer, It is necessary to check whether or not.
[0015]
FIG. 10 shows a conventional filter processing flow when the data RAM is configured in a ring buffer format. Note that the processing shown in FIG. 10 is performed from the start to the end each time input data is input.
[0016]
As shown in the flow of FIG. 10, a product-sum operation loop for the number of taps (delay number p + 1) is executed every time one piece of input data is input. Every time the read pointer P2 is updated in the loop, It is necessary to check whether the read pointer P2 has reached the end of the ring buffer. (Step S309)
In the case of a digital filter that constitutes a data RAM (data buffer and delay buffer) in the conventional ring buffer format, the write pointer P1 is updated each time data is input, and the write position of the latest input data is moved and written. As the pointer P1 is updated, the start position of the read pointer P2 for reading delay data during the product-sum operation is also moved, so the read pointer P2 may start from the middle of the ring buffer. Since the read pointer P2 is updated for each product-sum operation, when the read pointer P2 starts from the middle of the ring buffer, the read pointer P2 is ringed while repeating the product-sum operation of the number of taps (p + 1). Since the end of the buffer is exceeded, it is necessary to check whether the pointer has reached the end of the buffer every time the read pointer P2 is updated.
[0017]
For microcomputers and DSPs with built-in multimedia instructions such as multiply-accumulate instructions, a condition for checking whether the pointer has reached the end of the buffer with respect to the execution time of the multiply-accumulate process and the pointer update process in the multiply-add process loop Judgment processing time accounts for a large percentage. This hinders the speeding up of the filtering process.
[0018]
In order to solve the above problem, Japanese Patent No. 3071765 proposes a method for increasing the processing speed by eliminating the need to check the end of the pointer when updating the pointer.
[0019]
Specifically, when the number of input data is a finite value n, as a data RAM, instead of a ring buffer, an array of the total number of input data n and delay number p (p + n) is prepared. Considering that the pointer does not exceed the end even when the pointer is updated, the pointer end check is avoided when the data RAM is configured in a ring buffer format.
[0020]
In order to describe the second conventional digital filter described above in more detail, it will be described with reference to the drawings.
[0021]
FIG. 11 is a diagram showing a configuration of a data RAM, pointers, and corresponding coefficient memories in the digital filter of Conventional Example 2.
[0022]
The data RAM is composed of (n + p) buffers in which the number of input data n and the delay number p are combined. 0 is stored in advance in p buffers from the top (X2) of the buffer. The write pointer P1 starts from the position (p + 1) th (D1 in FIG. 4) from the buffer head (X2).
[0023]
Next, the operation of the conventional digital filter will be described using a flow.
[0024]
FIG. 12 shows a filter processing flow of Conventional Example 2. As shown in the flow of FIG. 12, the end check process at the time of updating the pointer is not required in the product-sum operation loop.
[0025]
As described above, in the digital filter of Conventional Example 2, it is considered that the pointer does not exceed the end of the buffer array even if the pointer is updated, and the pointer end check is avoided when the data RAM is configured in a ring buffer format. By doing so, the execution speed of the filter processing is improved.
[0026]
[Problems to be solved by the invention]
However, the filter processing in the above-described conventional digital filter has the following problems.
[0027]
The first problem is that in the case of a digital filter in which a data buffer and a delay buffer are configured in a conventional ring buffer format, management of pointers is complicated, so that it takes many processing steps and hinders speeding up of filter processing. It is a point.
[0028]
The reason is that when the data buffer and the delay buffer are configured in a ring buffer format, the write pointer (P1) is updated every time data is input and the latest input data is written, so that the delay data is read out during the product-sum operation. The start position of the read pointer (P2) also moves and starts from the middle of the ring buffer.
[0029]
Since the read pointer (P2) is updated for each product-sum operation, the read pointer (P2) crosses the ring buffer boundary while repeating the product-sum operation of the number of taps (p + 1). This is because it is necessary to check whether the pointer has reached the end of the buffer every time P2) is updated.
[0030]
For microcomputers and DSPs with built-in multimedia instructions such as multiply-accumulate instructions, a condition for checking whether the pointer has reached the end of the buffer with respect to the execution time of the multiply-accumulate process and the pointer update process in the multiply-add process loop Judgment processing time accounts for a large percentage.
[0031]
The second problem is that in the digital filter of Conventional Example 2 that avoids the first problem, the total number of input data n and delay number p is used as a data RAM in order to avoid a pointer end check. Since it is necessary to prepare a (p + n) buffer (delay element) array, it is necessary to prepare a large number of buffers (delay elements) when the number of input data is large. This increases the circuit scale and increases the system cost.
[0032]
The reason is that, in order to eliminate the need for pointer check in the product-sum operation loop, when the number of input data is a finite value n, a total of (n + p) delay element arrays (data buffer) (data buffer) ) To update the pointer so that the pointer does not exceed the end of the buffer. Therefore, even when the finite value n of the number of input data is large, (n + p) delay element arrays This is because it is necessary to prepare.
[0033]
A third problem is that the digital filter of the above-described conventional example 2 may not be realized in a system with a small amount of installed memory such as a portable device.
[0034]
The reason is that in the digital filter of the above-described conventional example 2, it is necessary to prepare (n + p) delay elements (data buffers), which is the sum of the number of input data n + the number of delays p, as a data RAM. This is because the required data buffer size cannot be secured because only the specified memory is mounted.
[0035]
Further, in the case of digital filter processing in which the number of input data is indefinite (or infinite), there is a problem that the digital filter according to Conventional Example 2 cannot be realized.
[0036]
The object of the present invention is to solve the above-mentioned problems, and the data RAM adopts a ring buffer format as in the prior art, thereby minimizing the buffer size, extending the filter coefficient memory, and always setting the data read pointer. By starting from the end of the ring buffer, it is not necessary to check the end of the pointer when updating the pointer, and the processing steps are reduced.
[0037]
[Means for Solving the Problems]
    The digital filter of the present invention isA sum-of-products calculator, and input data and n (n> 0) delay data already received as input data, and n + 1 filter coefficients respectively corresponding to the input data and the n delay data A digital filter that performs a multiplication operation by multiplying and performing a sum-of-products operation that takes the sum of the multiplication results, wherein 2n + 1 is obtained by deleting a predetermined filter coefficient from a repetition of the n + 1 filter coefficients twice A coefficient memory having a first array of 2n + 1 buffers in which a number of filter coefficients are stored, and corresponding to the repeated n + 1 filter coefficients in the order of the n + 1 filter coefficients stored repeatedly. A second array of n + 1 buffers in which the input data and the n delay data are stored. A data RAM, a write pointer for designating the write address of the input data to the data RAM in a predetermined buffer constituting the second array, and updating according to the write of the input data, and the multiply-accumulate operation The address of the input data or the delay data read from the data RAM when executing is specified as a buffer constituting one end of the second array as an initial value when starting the filter operation, and the product sum The filter operation is started with a read pointer that is updated in response to the reading of the input data or the delay data that is performed each time an operation is performed, and the address of the filter coefficient that is read from the coefficient memory when the product-sum operation is performed. Configure one end of the second array specified by the write pointer as an initial value when A coefficient pointer set based on the position from the buffer and updated according to the reading of the filter coefficient performed for each execution of the sum-of-products operation,It is the structure provided with.
[0038]
In the digital filter of the present invention, the product-sum calculator includes a multiplier and an adder, and the product-sum calculator includes a result register that holds the result of the adder.
[0039]
Furthermore, the processing method of the digital filter of the present invention includes:The input data and n (n> 0) delay data already received as input data are multiplied by n + 1 filter coefficients corresponding to the input data and the n delay data, respectively. A digital filter processing method for performing a filter operation by executing a product-sum operation for calculating a sum, wherein a write pointer for designating a write position of the input data to n + 1 buffers is set to a predetermined position; A step of writing the input data to the buffer designated by the write pointer, and a read position for reading the input data and the delayed data from the n + 1 buffers when starting the filtering operation. A process for setting an initial value of a read pointer for designating one end of the n + 1 buffers When the filter operation is started, the n + 1 corresponding to the input data and the n delay data in the storage order of the input data and the n delay data stored in the n + 1 buffers. An initial value of a coefficient pointer that specifies a reading position when reading the filter coefficient from 2n + 1 buffers in which 2n + 1 filter coefficients are stored by deleting predetermined filter coefficients from a repetition of the filter coefficients twice. The step of setting based on the position from one end of the n + 1 buffers designated by the write pointer, the step of reading the input data or the delay data based on the designation of the read pointer, and the designation of the coefficient pointer Reading the filter coefficients based on the input data or the delay A step of executing the product-sum operation based on the input data or the delay data read out in the step of reading out the data and the filter coefficient read out in the step of reading out the filter coefficient. .
[0042]
DETAILED DESCRIPTION OF THE INVENTION
The digital filter and its processing method according to the present invention relates to a digital filter executed by a general-purpose microcomputer or DSP and its software, and in particular, by managing a pointer in a product-sum operation loop process by expanding a filter coefficient (tap coefficient). Unnecessary to minimize the increase in memory compared to conventional digital filters, reduce the number of processing steps to shorten the filter processing time (execution time), increase the system processing speed or power consumption Provide a configuration that can reduce
[0043]
In FIG. 2, in the digital filter according to the present invention, the data RAM 1 that stores input data and holds it for the number of delays is a ring buffer type memory area composed of buffers with a number of delays p + 1 as in the prior art. The coefficient memory 2 that holds the filter coefficients is configured as an array in which an array of tap coefficients for the number of taps (delay number + 1) is repeated twice except for one tap coefficient. Furthermore, at the start of the product-sum operation loop of the digital filter processing executed every time data is input, the data RAM read pointer P2 always starts from the extreme end of the ring buffer and is updated to the other end. The coefficient pointer P3 indicating the tap coefficient to be started is updated from the position corresponding to the current position of the write pointer P1 to the end side, so that the read pointer P2 and the coefficient pointer are repeated in the product-sum operation loop repeated several times. The end check of P3 becomes unnecessary, and the number of execution steps of the product-sum operation loop is reduced.
[0044]
In this way, the digital filter of the present invention extends the filter coefficient (tap coefficient), thereby making it possible to reduce the number of filter processing steps by making it unnecessary to check the end of the pointer when updating the data read pointer. .
[0045]
The present invention relates to digital filter processing by a general-purpose microcomputer or DSP, and is applied to a multimedia system that performs filter processing by software.
[0046]
Hereinafter, a digital filter according to an embodiment of the present invention will be described with reference to the drawings.
[0047]
FIG. 1 is a block diagram showing a configuration of a digital filter and a processing method thereof according to the first embodiment of the present invention. The digital filter shown in FIG. 1 stores a coefficient memory 2 that expands and stores an array of filter coefficients for the number of taps, stores input data for each unit time, and holds delay data by unit delay elements for the number of delays. A data RAM (delay unit) 1, a write pointer P 1 for designating a write address of input data to the data RAM 1, and a read pointer P 2 for designating an address of input data or delay data to be read when performing a product-sum operation for each tap A multiplier register 5 that holds the read input data or delay data, a coefficient pointer P3 that specifies the address of the filter coefficient to be read from the coefficient memory 2 when performing a product-sum operation for each tap, and holds the read filter coefficient Multiplicand register 6 and product-sum calculator (multiplier 3, adder 4, result register 7) And it is made of. The initial value of the coefficient pointer P3 is set based on the value of the write pointer P1 of the input data.
[0048]
Next, the correspondence of each pointer in the configuration of the data RAM 1 and the configuration of the coefficient memory 2 in the digital filter according to the first embodiment of the present invention will be described with reference to FIG.
[0049]
FIG. 2 is a diagram showing a configuration of a ring buffer type data RAM 1 and a coefficient memory 2 in the digital filter according to the first embodiment of the present invention. Here, the data RAM 1 is composed of (p + 1) buffers in which the delay buffer corresponding to the delay number p and the input data buffer are combined as in the prior art, and the coefficient memory 2 is the same number as the data RAM (number of taps (p + 1)). Tap coefficient arrays a0, a1, a2,. . . It is composed of an array in which ap-1 and ap are repeated twice and only the leading a0 is removed.
[0050]
Here, P1 is a position indicated by a write pointer P1 indicating an address when input data is written to the ring buffer. Similarly, P2 is the position indicated by the read pointer P2 indicating the address of the delay data read when performing the product-sum operation for each tap. P3 is a position indicated by a coefficient pointer P3 indicating a filter coefficient to be read in the product-sum operation for each tap. The write pointer P1 is updated to the X1 side every time input data is written. The read pointer P2 always starts from the buffer position at the extreme end of the X1 side at the start of the product-sum operation, and indicates the buffer position where the data to be multiplied and updated to the X2 side is stored every product-sum operation. The X2 side end position is shown at the end of the calculation.
[0051]
The coefficient pointer P3 starts from the index position from the coefficient memory head Y1 corresponding to the index value from the data RAM head X2 of the current write pointer P1 (in FIG. 2, since P1 is third from X2, P3 starts from Y1. The position of the tap coefficient used for the product-sum operation for each tap is updated to the Y2 side every product-sum operation.
[0052]
Next, the operation of the digital filter according to the first embodiment of the present invention will be described in detail with reference to the flowcharts of FIGS.
[0053]
When data is input to the digital filter of the digital filter according to the first embodiment of the present invention, first, the accumulation register (result register 7) is cleared to 0 (step S101 in FIG. 3).
[0054]
Next, the input data D1 is written at the position indicated by the write pointer P1 (step S102).
[0055]
Further, the read pointer P2 is initialized to a value indicating the end position (X1 side end buffer) of the data RAM (step S103). Next, the coefficient pointer P3 is set to a position shifted from the end position on the Y1 side by the index value from the X2 side of the current write pointer P1 (step S104).
[0056]
Next, data is read from the position of the read pointer P2 and set in the multiplier register 5 (step S105). Further, the filter coefficient is read from the position of the coefficient pointer P3 and set in the multiplicand register (step S106).
[0057]
Next, the result of multiplying the data of the multiplier register 5 by the coefficient of the multiplicand register 6 and adding the contents of the result register is stored in the accumulation register (result register 7) (step S107).
[0058]
The read pointer P2 is updated to indicate the buffer position adjacent to the X2 side (step S108), and similarly, the coefficient pointer P3 is also updated to indicate the coefficient position adjacent to the Y2 side (step S109).
[0059]
The processing from step S105 to step S109 is repeated several taps (step S110). After the product-sum operation for all taps is completed, the contents of the result register 7 as the filter processing result are output (step S111).
[0060]
Next, after updating the write pointer P1 to the X1 side (step S112), the updated write pointer P1 is confirmed (step S113). If the updated write pointer P1 exceeds the end X1 of the ring buffer, the The pointer P1 is reset to the ring buffer head position (step S114). When the next data is input, the filtering process is performed again from step S101.
[0061]
Next, a description will be given with reference to specific examples.
[0062]
A filter having 6 taps (5 delays) will be described as an example. FIG. 4 shows a filter associated with the input of the first data, the third data, the sixth data, and the ninth data among the time-series input data to the digital filter according to the first embodiment of the present invention. It is explanatory drawing which shows the content of the data RAM at the time of the product-sum operation loop start of a process, the position of the write pointer P1, the start position of the read pointer P2, and the start position of the coefficient pointer P3.
[0063]
As an initial state, all the buffers of the data RAM 1 are cleared to 0, and the write pointer P1 indicates the X2 side endmost buffer that is the head of the data RAM.
[0064]
First, when the first data D1 of time series input data is input, the accumulation register (result register 7) is cleared to 0 (step S101), and then the position indicated by the write pointer P1 (P1 in FIG. 4 (1)). The input data D1 is written at the position (step S102).
[0065]
Next, the read pointer P2 is initialized to a value indicating the end position (X1-side end buffer) of the data RAM (step S103). Next, the coefficient pointer P3 is set to a position shifted from the end position on the Y1 side by the index value from the X2 side of the current write pointer P1 (step S104). Here, since the write pointer P1 is first from the X2 side, the initial value of the coefficient pointer P3 is the first position from the Y1 side. The contents of the data RAM, the position of the write pointer P1, the start position of the read pointer P2, and the start position of the coefficient pointer P3 at this time are shown in FIG.
[0066]
Next, data is read from the position of the read pointer P2 and set in the multiplier register 5 (step S105). Further, the filter coefficient is read from the position of the coefficient pointer P3 and set in the multiplicand register (step S106).
[0067]
Next, the result of multiplying the data of the multiplier register 5 by the coefficient of the multiplicand register 6 and adding the contents of the result register is stored in the accumulation register (result register 7) (step S107). The read pointer P2 is updated to indicate the buffer position adjacent to the X2 side (step S108), and similarly, the coefficient pointer P3 is also updated to indicate the coefficient position adjacent to the Y2 side (step S109).
[0068]
The processing from step S105 to step S109 is repeated 6 times (step S110), and after the product-sum operation for all the taps is completed, the contents of the result register 7 as the filter processing result are output (step S111). Next, the write pointer P1 is updated to the X1 side (step S112), and the write pointer indicates the second buffer from the X2 side. Next, the updated write pointer P1 is confirmed (step S113), and since it does not exceed the end X1 of the ring buffer, the filtering process associated with the input of the head data D1 is completed. When the next data is input, the filtering process is performed again from step S101.
[0069]
Similarly, the contents of the data RAM, the position of the write pointer P1, the start position of the read pointer P2, and the start position of the coefficient pointer P3 at the end of step S104 in the filtering process accompanying the input of the third input data D3. Is shown in (2) of FIG. The start position of the coefficient pointer P3 is a position indicating the third coefficient from the Y1 side because the write pointer P1 indicates the third buffer from the X2 side.
[0070]
Similarly, the contents of the data RAM, the position of the write pointer P1, the start position of the read pointer P2, and the start position of the coefficient pointer P3 in the filtering process accompanying the input of the sixth input data D6 at the end of step S104. (3) of FIG. 4 shows the contents of the data RAM, the position of the write pointer P1, the start position of the read pointer P2 at the end of step S104 in the filtering process accompanying the input of the ninth input data D9, and The start position of the coefficient pointer P3 is shown in (4) of FIG.
[0071]
As described above, at the time of data storage, the data storage position is designated by the write pointer P1. That is, the write pointer P1 first designates the endmost buffer on the X2 side of the data RAM1. Next, the write pointer P1 designates a buffer adjacent to the X2 side end buffer of the data RAM 11 in the X1 direction. Thereafter, the write pointer P1 is sequentially shifted in the X1 direction to sequentially specify the buffers. Then, after designating the buffer at the extreme end in the X1 direction, the buffer at the extreme end in the X2 direction is designated, and then the shift in the X1 direction is performed. In FIG. 2, the write pointer P1 currently designates the third buffer from the end on the X2 side. Thereby, the data Dn is stored in the third buffer from the X2 side.
[0072]
On the other hand, data reading in the product-sum operation loop starts from the end position of the ring buffer, and when the product-sum operation for the number of taps is finished, the read pointer P2 always indicates the head position of the ring buffer. There is no crossing.
[0073]
Further, the filter coefficient read pointer P3 does not exceed the end of the coefficient memory when the product-sum operation for the number of taps is started from the position corresponding to P1.
[0074]
As described above, according to the digital filter of the present invention, since the data read pointer P2 and the coefficient pointer P3 do not cross the buffer boundary, it is not necessary to check the end of the pointer in the product-sum operation loop. It is possible to reduce the number of execution steps and improve the processing speed with respect to the conventional digital filter processing of the ring buffer format. As a result, the power consumption can be reduced by reducing the operation clock frequency.
[0075]
Next, another embodiment of the present invention will be described in detail with reference to the drawings.
[0076]
FIG. 5 shows the configuration of a data RAM and a coefficient memory using a digital filter according to the second embodiment of the present invention, taking a filter with 6 taps (5 delays) as an example.
[0077]
The digital filter according to the second embodiment of the present invention is the same as the first embodiment of the present invention shown in FIGS. 1 to 4 except for the configuration of the coefficient memory and the start position of the coefficient pointer P3 associated therewith. This is the same as the digital filter. The same reference numerals are assigned to the same components.
[0078]
Of the time-series input data to the digital filter according to the second embodiment of the present invention, the product sum of the filter processing accompanying the input of the first data, the fifth data, the sixth data, and the ninth data FIG. 5 shows the contents of the data RAM, the position of the write pointer P1, the start position of the read pointer P2, and the start position of the coefficient pointer P3 at the start of the calculation loop.
[0079]
The coefficient memory of the digital filter according to the first embodiment of the present invention includes tap coefficient arrays a0, a1, a2,. . . Whereas ap-1 and ap are repeated twice to remove the leading a0, the digital filter coefficient memory according to the second embodiment of the present invention has tap coefficient arrays a0, a1, a2 ,. . . Ap-1 and ap are repeated twice and consist of a sequence excluding only the final ap.
[0080]
Also, the start position of the coefficient pointer P3 at the start of the product-sum operation loop in the digital filter of the second embodiment of the present invention is the current position from the start position of Y1 in the digital filter of the first embodiment of the present invention. In contrast, in the digital filter according to the second embodiment of the present invention, the write pointer P1 is shifted from the X2 side of the current write pointer P1. Is set to a position shifted by plus one.
[0081]
As shown in FIG. 5C, when the write pointer P1 is the end position of the ring buffer, the start position of the coefficient pointer P3 at the start of the product-sum operation loop is the current write from the start position of Y1. The index value from the X2 side of the pointer P1 is set not at the position shifted by plus 1, but at the head position of the coefficient memory.
[0082]
As shown in the digital filter of the second embodiment of the present invention, the coefficient memory is divided into tap coefficient arrays a0, a1, a2,. . . Even when ap-1 and ap are repeated twice and only the final ap is removed, the effect is the same as that of the digital filter of the first embodiment of the present invention.
[0083]
Next, a digital filter according to a third embodiment of the present invention will be described in detail with reference to the drawings.
[0084]
FIG. 6 is a flowchart of the coefficient memory expansion process of the digital filter according to the digital filter of the third embodiment of the present invention. In the digital filter according to the third embodiment of the present invention, the coefficient memory in the initial state of the system has tap coefficient arrays a0, a1, a2,. . . When the actual filter processing is started only by ap-1 and ap, the coefficient memory is expanded in advance by the procedure shown in FIG. 6, and the digital filter of the first embodiment of the present invention Similarly, the filtering process can be performed. When the filtering process is not performed, the coefficient memory area corresponding to the number of delays increased by the expansion of the coefficient memory can be used as a memory area for other applications. Thereby, the digital filter of the present invention can be realized even in a system with a small memory capacity.
[0085]
【The invention's effect】
As described above, the first effect of the present invention is that the digital filter processing of the present invention does not require pointer management (check) in the product-sum operation loop processing, compared to the conventional digital filter processing of the ring buffer format. Therefore, it is possible to shorten the filter processing time and speed up the system. Thereby, it is possible to reduce power consumption by reducing the number of operating clocks.
[0086]
The reason is that the filter coefficient RAM is expanded compared to the conventional digital filter of the ring buffer format, and the sum-of-products calculation process starts from the beginning (or end) of the ring buffer and ends in the number of taps. This is because the end of the line is not exceeded.
[0087]
Specifically, for example, in a general-purpose microcomputer, the processing for one data input with a conventional ring buffer digital filter requires approximately (10 × p + 9) steps, whereas according to the present invention ( 7 × p + 10) steps are sufficient. If this is converted to a ratio, the processing time can be reduced to about 70% of the conventional time.
[0088]
In the filtering process, input data is processed at equal time intervals. Therefore, since the filter processing time can be shortened, the execution time of applications other than the filter processing can be increased. Also, by shortening the filter processing time, even if the operation clock is slowed down, the filter processing at the unit time interval is in time, so that the number of operation clocks can be reduced and power consumption can be reduced.
[0089]
The second effect is that the digital data in which pointer management (checking) is not required by using a buffer (delay element) array of a total number (n + p) of a finite input data number n and a delay number p as a conventional data RAM. In contrast to the filter processing, the present invention is to reduce the memory size required by reducing the number of memories that are increased for speeding up the digital filter processing to the number of delays p, thereby reducing the circuit scale. .
[0090]
The reason is that the number of taps of the FIR type digital filter is generally sufficiently smaller than the number of input data.
[0091]
For example, the number of filter taps used in an MP3 decoder, which is an audio codec technique, is about 22 to 512. On the other hand, the number of data is about 450,000 in the case of stereo data for 10 seconds at a sampling frequency of 22 KHz. In order to process this with a digital filter using a conventional (n + p) buffer (delay element) array of the total number of input data n and delay number p, a memory of about 440K words is required. In the digital filter of the present invention, the memory can be reduced to about 1.5K words.
[Brief description of the drawings]
FIG. 1 is a block diagram of a digital filter according to a first embodiment of this invention.
FIG. 2 is a configuration diagram of a data RAM and a coefficient memory described in FIG. 1;
FIG. 3 is a digital filter processing flow according to the first embodiment of this invention;
FIG. 4 is an explanatory diagram of pointer positions in the digital filter according to the first embodiment of this invention.
FIG. 5 is a block diagram of a digital filter according to a second embodiment of this invention.
FIG. 6 is a flow of coefficient memory expansion processing in the digital filter according to the third embodiment of the present invention.
FIG. 7 is a conceptual diagram of an FIR type digital filter.
FIG. 8 is a block diagram of a first conventional digital filter.
FIG. 9 is a configuration diagram of a data RAM and a coefficient memory in the first conventional digital filter.
FIG. 10 is a processing flow of a digital filter in the first conventional digital filter.
FIG. 11 is a configuration diagram of a data RAM and a coefficient memory in a second conventional digital filter.
FIG. 12 is a processing flow of a digital filter in a second conventional digital filter.
[Explanation of symbols]
1,11,21 Data RAM (delay device)
2,12,22 Coefficient memory
3,13 multiplier
4,14 Adder
5,15 multiplier register
6,16 Multiplicand register
7,17 Result register
P1 write pointer
P2 read pointer
P3 coefficient memory pointer

Claims (10)

A sum-of-products calculator, and input data and n (n> 0) delay data already received as input data, and n + 1 filter coefficients respectively corresponding to the input data and the n delay data A digital filter that performs a filter operation by performing a multiply-accumulate operation that performs multiplication and takes the sum of the multiplication results,
A coefficient memory having a first array of 2n + 1 buffers for storing 2n + 1 filter coefficients obtained by deleting the first filter coefficient or the last filter coefficient from the n + 1 filter coefficients repeated twice; ,
A second sequence comprising n + 1 buffers in which the input data and n delay data respectively corresponding to the repeated n + 1 filter coefficients are stored in the order of the repeatedly stored n + 1 filter coefficients. A data RAM having an array;
A write pointer that designates a write address of the input data to the data RAM in a predetermined buffer that constitutes the second array, and is updated in accordance with the write of the input data;
The address of the input data or the delayed data read out from the data RAM when executing the multiply-accumulate operation is designated as a buffer constituting one end of the second array as an initial value when the filter operation is started. A read pointer that is updated in response to the reading of the input data or the delayed data performed each time the multiply-accumulate operation is performed;
A buffer constituting the other end of the second array in which the address of the filter coefficient to be read from the coefficient memory at the time of executing the product-sum operation is designated by the write pointer as an initial value when starting the filter operation A coefficient pointer that is set based on the position from and updated in response to the reading of the filter coefficient performed each time the product-sum operation is performed
Digital filter with     The digital filter according to claim 1, wherein the product-sum calculator includes a multiplier and an adder.     The digital filter according to claim 2, wherein the product-sum calculator includes a result register that holds a result of the adder.     The digital filter according to claim 1, further comprising a multiplier register that holds the read input data or delay data.     The digital filter according to claim 1, further comprising a multiplicand register that holds the read filter coefficient. The coefficient memory has a first array composed of 2n + 1 buffers in which 2n + 1 filter coefficients obtained by deleting the head filter coefficient are stored from a repetition of the n + 1 filter coefficients twice. The position from the buffer constituting one end of the first array, which is an initial value when the filter operation of the coefficient pointer is started, constitutes the other end of the second array designated by the write pointer. The digital filter according to claim 1, wherein the position is the same as the position from the buffer.     The digital filter according to claim 1, wherein the data RAM having the second array is in a ring buffer format.     The digital filter according to claim 1, wherein the digital filter is an FIR type. The input data and n (n> 0) delay data already received as input data are multiplied by n + 1 filter coefficients corresponding to the input data and the n delay data, respectively. A digital filter processing method that performs a filter operation by executing a multiply-accumulate operation that takes a sum,
setting a write pointer for designating a write position of the input data to n + 1 buffers to a predetermined position;
Writing the input data to the buffer specified by the write pointer;
When starting the filtering operation, setting an initial value of a read pointer for designating a read position when reading the input data and the delayed data from the n + 1 buffers at one end of the n + 1 buffers;
When starting the filtering operation, the input data stored in the n + 1 buffers and the n + 1 delay data corresponding to the n delay data are stored in the storage order of the n delay data. A coefficient pointer for designating a reading position when reading the filter coefficient from 2n + 1 buffers storing 2n + 1 filter coefficients obtained by deleting the first filter coefficient or the last filter coefficient from the one obtained by repeating the filter coefficient twice Setting an initial value based on a position from the other end of the n + 1 buffers designated by the write pointer;
Reading the input data or the delay data based on the designation of the read pointer;
Reading the filter coefficient based on the specification of the coefficient pointer;
Executing the product-sum operation based on the input data or the delay data read by the step of reading the input data or the delay data, and the filter coefficient read by the step of reading the filter coefficient;
A method for processing a digital filter, comprising: After the step of performing the multiply-accumulate operation, updating the designation destination of the read pointer in a buffer adjacent to the buffer currently designated by the read pointer;
Updating the designated destination of the coefficient pointer in a buffer next to the buffer currently designated by the coefficient pointer;
Determining whether the sum-of-products operation has been performed for all of the n + 1 filter coefficients;
Further comprising a,
In determining whether to perform a pre Kisekiwa operation, when performing the product-sum operation for all the (n + 1) filter coefficients, next to the buffer in which the write pointer is currently designated Updating a designated destination of the write pointer in a buffer;
In the step of determining whether or not the product-sum operation has been executed, when the product-sum operation has not been executed for all of the n + 1 filter coefficients, the step of reading the input data or the delay data; ,
Reading the filter coefficients;
Performing the product-sum operation;
Updating the designation of the read pointer;
Updating the designated destination of the coefficient pointer;
Determining whether the product-sum operation has been performed;
10. The digital filter processing method according to claim 9, wherein the processing is executed again.

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