JPH04288633A - Microprocessor - Google Patents

Abstract

PURPOSE:To take out internal information to the external without an emulation monitor program and a context switch by transferring internal information indicating the execution condition of a microprocessor itself to an external memory and jumping the control to a program counter value. CONSTITUTION:When the microprocessor fetches an instruction (2)11-2 at address (xyz), an instruction alpha12-1 is forcibly fetched by the action of hardware control on the outside of the microprocessor. After execution of an instruction (1)11-1 at address (xyz-1), contents of a register where context information of the microprocessor is held are transferred to the designated address of an external memory and increment of the program counter is suppressed by execution of the instruction alpha 12-1. Consequently, the program counter value fetched after execution of the instruction alpha12-1 indicates address (xyz) as it is, and the microprocessor jumps to its own program counter value.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor equipped with instructions for supporting microprocessor development.

0002

[Prior Art] Emulators (commonly known as in-
There is a circuit emulator (ICE) device. This emulator is connected in place of the microprocessor on the target system and captures all signals input to the microprocessor. Inside the emulator, the operation of the microprocessor on the target system can be completely simulated, and the internal state of the microprocessor during operation can be extracted to the outside. Hereinafter, the operation of retrieving the internal information of the microprocessor to the outside immediately before executing an instruction at a certain address in the emulator will be explained using FIG. 3. Here, the information inside the microprocessor refers to information equivalent to the context such as the contents of registers.

FIG. 3 is a schematic diagram showing an example of the operation of extracting internal information of a conventional microprocessor in an emulator. In this FIG. 3, 11-1 and 11-
2 indicates instructions (1) and (2) of the user program, 13 is a break instruction, and 14 is an emulator monitor program. And here, the instruction (1) 11-1, (xyz-1) of the microprocessor address (xyz-1)
) address (2) 11-2 shall be executed in order,
Assume that the internal information of the microprocessor immediately before execution of instruction (2) 11-2 at address (xyz) is retrieved.

[0004] Next, the operation will be explained. First, the microprocessor executes the instruction (2) 11- at address (xyz).
At the time of fetching the break instruction 13, the break instruction 13 is forcibly fetched by means of hardware control by means not shown outside the microprocessor. And (xyz-
1) After the instruction at address (1) 11-1 is executed, an interrupt is generated by executing the break instruction 13, the user program is interrupted, context information is saved, and the emulator monitor program 14 is activated. Next, by executing the emulator monitor program 14, the internal information of the microprocessor is extracted to the outside. After the execution of the emulator monitor program 14 is completed, the context information of the user program is restored, the instruction (2) 11-2 at the address (xyz) that is originally to be executed is fetched, and the execution of the user program is resumed.

[0005]

[Problem to be solved by the invention] The problem to be solved is that conventional microprocessors take out internal information during program execution to the outside using the method described above. The point is that you need an emulator monitor program to take it out. Furthermore, conventional microprocessors have the problem of impairing real-time performance due to context switching.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a microprocessor that can extract internal information to the outside without an emulator monitor program or context switching.

[0007]

[Means for Solving the Problems] The present invention provides an instruction that has the function of transferring internal information indicating the execution status of the microprocessor itself, such as the context of the microprocessor, to an external memory and jumping to its own program counter value. It is equipped with the following.

[0008]

[Operation] In this invention, in the emulator,
At the point when a microprocessor fetches an instruction,
By discharging the internal information of the microprocessor to an external memory (not shown) and forcibly fetching an instruction to jump to its own program counter value,
After extracting the internal information of the microprocessor to the outside,
To fetch and execute an instruction that should originally be executed again, and to execute a subsequent user program without contradiction.

[0009]

[Embodiment] FIG. 1 is a schematic diagram showing the flow of executed instructions in an embodiment of a microprocessor according to the present invention, and shows an example of the flow of executed instructions in the case of a low-level microprocessor that does not perform instruction prefetching. . In FIG. 1, the same reference numerals as in FIG. 3 indicate corresponding parts,
12-1 is an instruction α, and this instruction α12-1 has a function to transfer the contents of a register that holds context information of the microprocessor to an external memory at a specified address by means not shown, and also to suppress incrementing of the program counter. have And this command α12-
1 is an instruction having a function of transferring internal information indicating the execution status of the microprocessor itself, such as the context of the microprocessor, to an external memory and jumping to its own program counter value.

In the case of a microprocessor that does not perform instruction prefetching, all calculations of the program counter for instruction fetching are controlled in synchronization with instruction execution. A function to jump to the counter value can be realized. Here, the microprocessor executes the instruction (1)11-1 at address (xyz-1), (xyz)
It is assumed that the instruction (2) 11-2 at address (xyz) is executed in order, and the internal information of the microprocessor immediately before the instruction (2) 11-2 at address (xyz) is executed is extracted. The microprocessor executes the instruction (2) 11 at address (xyz)
-2, the instruction α12-1 is forcibly fetched by means of hardware control by means not shown outside the microprocessor. And (xyz-
1) After executing the instruction at address (1) 11-1, the instruction α12
-1, the contents of the register holding the context information of the microprocessor are transferred to the external memory at the specified address by means not shown, and the increment of the program counter is suppressed. Therefore, the program counter value fetched after execution of the instruction α12-1 remains at the (xyz) address and jumps to its own program counter value. The instruction (2) 11-2 that should originally be executed is held at address (xyz), and the original user program can be executed without contradiction even after the instruction α12-1 is executed.

Next, another embodiment of the present invention will be explained using FIG. 2. FIG. 2 is a schematic diagram showing an instruction fetch operation in an embodiment of a high-level microprocessor that performs instruction prefetch. In this FIG. 2, instructions 1, 2, . . . 6 are instructions of the user program, and instructions 12
-2 is the instruction β provided according to the present invention. here,
For simplicity, a three-stage pipeline microprocessor is used. This instruction β12-2, like the instruction α12-1 in FIG. It has a function to jump to the program counter value. Here, the microprocessor (xy
It is assumed that instructions 1 to 6 of the user program held in order from address z-2) to address (xyz+3) are executed in order, and internal information of the microprocessor immediately before execution of instruction 3 at address (xyz) is extracted. .

[0012] Then, the microprocessor (xyz
) At the time of fetching the instruction 3 at address ), the instruction β12-2 is forcibly fetched by the action of hardware control by means not shown outside the microprocessor. Since the instruction fetch program counter calculation of a microprocessor that performs instruction prefetch is performed independently of instruction execution, the subsequent (xy
Instructions 5 and 6 are subsequently fetched from addresses z+1) and (xyz+2). When instruction β12-2 is executed, it transfers the contents of a register (not shown) that holds context information of the microprocessor to the external memory at the specified address by means not shown, and also transfers its own program counter value ( xyz) Jump to address. Therefore, after all the queues and pipelines are initialized, they are sequentially fetched again starting from instruction 3 at address (xyz), and the original user program can be executed without contradiction even after execution of instruction β12-2.

[0013]

[Effects of the Invention] As explained above, the microprocessor of the present invention has an instruction that has the function of transferring the contents of the register that holds the microprocessor's context information to external memory and jumping to its own program counter value. When the microprocessor fetches a certain instruction, the microprocessor's internal information is flushed out to external memory and an instruction that jumps to its own program counter value is forcibly fetched, thereby extracting the microprocessor's internal information to the outside. After that, the instruction that should have been executed is fetched and executed again, and the subsequent user program is executed without any contradiction.This has the effect of allowing the internal information of the microprocessor to be retrieved externally without the need for an emulator monitor program. . Furthermore, since context switching is not involved when extracting the internal information of the microprocessor to the outside, there is an effect that real-time performance is not impaired.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the flow of execution instructions in an embodiment of a microprocessor according to the present invention.

FIG. 2 is a schematic diagram showing an instruction fetch operation in another embodiment of the invention.

FIG. 3 is a schematic diagram showing an example of an operation of extracting internal information of a conventional microprocessor that does not use the present invention in an emulator.

[Explanation of symbols]

11-1 Command (1) 11-2 Command (2) 12-1 Command α 12-2 Instruction β

Claims (1)

[Claims] [Claim 1] A microprocessor is characterized by having an instruction having a function of transferring internal information indicating the execution status of the microprocessor itself, such as the context of the microprocessor, to an external memory and jumping to its own program counter value. microprocessor.