JP2002229776A - Data processor for executing multiple sets of instructions - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of executing multiple sets of instructions without requiring extra power consumption and without delaying a clock frequency. SOLUTION: The data processor is provided with a memory 210, a main instruction word processor core 200, a program counter register 220, a plurality of data registers 230, a processor state register 250 having an instruction set selector 260, a pre-decoder 270, an instruction fetching unit 280, a decoder 290, a program counter controller 225 aligning various instruction words in length, and a bus 215. The pre-decoder 270 converts the instruction words of types other than a specific type into the instruction words of the specific type and outputs them, thereby the program core 200 is merely required to process only the instruction words of the specific type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data processing device. More specifically, the present invention relates to a data processing device for executing a plurality of instruction sets.

[0002]

2. Description of the Related Art A data processing apparatus usually includes a processor core for executing a program instruction word including a predetermined instruction set. In addition to the processor core, the data processing device includes a data memory for storing an executable program instruction word and a program counter register for pointing to an address in the memory for the next instruction word. . However, this type of data processing device can only execute one set of instructions. It would be much more convenient and more effective if the data processing device could execute and operate more than one instruction set.

[0003] FIG. 1 is a diagram showing “Interoperability with multip”.
U.S. Pat. No. 6, entitled "ul instruction sets"
FIG. 2 is a block diagram showing a structure of a conventional data processing device disclosed in Japanese Patent No. 021,265 and configured to execute two instruction sets.

As shown in FIG. 1, a processor core 10 of this conventional data processing apparatus includes a register bank 30 and
A booth multiplier 40, a barrel shifter 50, a 32-bit arithmetic logic unit (ALU) 60, and a write data register 70 are provided.

[0005] Other components in the data processing device include a first
Instruction decoder & logic controller 100, second instruction decoder & logic controller 110, program counter controller 140, program counter (PC) 130
, A multiplier 90, a read data register 120, an instruction pipeline 80, and the memory system 20.

In the conventional data processing apparatus, separate instruction decoders and logic controllers are required for both instruction sets. That is, the first instruction decoder & logic controller 100 decodes the program instruction word forming the first instruction set, and the second instruction decoder & logic controller 1
10 decodes the second set of instruction program instruction words. The program instruction word of the first instruction set is typically 32 bits, and the program instruction word of the second instruction set is usually 16 bits. Thus, the programmer can use a more effective instruction set consisting of a 32-bit instruction set, and save memory by using a more effective instruction set consisting of a 16-bit instruction set. Can also.

Control means must be provided to control which instruction decoder is used to decode the current instruction word. This control is performed by the program counter controller 140. The program counter controller 140 includes the program counter 130
Set or reset either the most or least significant bit in As a result, the multiplier 90 is controlled, and the selection between the first instruction decoder & logic controller 100 and the second instruction decoder & logic controller 110 is performed.

[0008] In the prior art having such an architecture, the type of instruction set can be determined in real time. That is, the two instruction sets can be mixed with each other, and there is no need to handle the two instruction sets individually. However, this configuration requires two instruction decoders & logic controllers. Therefore, the power consumption of the processor core 10 increases and the chip size increases. This means
This is unacceptable for the trend to develop smaller processors with lower power consumption.

[0009] Another conventional data processor configured to execute two sets of instructions is the "Multipul instruc".
US Patent Specification No. 5,5 entitled "tions set mapping"
No. 68,646. With this architecture, there is no need to provide control means to control which instruction decoder is used to decode the current program instruction word. That is, there is no need to set or reset either the most significant bit or the least significant bit in the program counter.

In a pipeline type processor, there are three stages: an acquisition stage (pipeline stage), a decoding stage, and an execution stage. This patent document provides a configuration in which a decryption stage can be used during data processing. During the decryption cycle,
A mapping step and a control signal generation step are performed. Different instruction sets are mapped first and translated into the main instruction set. The main instruction set will be executed in a subsequent execution stage.

However, it is necessary to map the instruction set during the decoding stage. Therefore, the time required for the decryption stage increases. This means that a high frequency configuration cannot be realized. In addition, when the hit speed is 95%, the power consumption becomes considerably large. These are not in line with current trends.

[0012]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data processing apparatus capable of executing a plurality of instruction sets without extra power consumption and without reducing a clock frequency. That is.

[0013] A data processing device according to the present invention includes a memory for storing a plurality of instruction words of a plurality of instruction sets; a processor core for executing a main instruction word of the plurality of instruction words; A program counter register (PC) for pointing to the next stored instruction word; a plurality of data registers for storing data including the IS bit and the instruction word type; and for storing the state of the processor core. A processor status register having an instruction set selector (ISS) for pointing to the current instruction set of the plurality of instruction sets; and at least one of the plurality of instruction sets to a main instruction word. A pre-decoder for translating and outputting;
An instruction fetcher for storing the main instruction word and holding TAG information, valid information and ISS information of the fetched instruction; and a main instruction word for decoding the main instruction word and decoding the main instruction word A decoder adapted to provide the decoded main instruction word to the processor core so that the word can be executed by the processor core; changing the value of the PC in response to the ISS, thereby reducing the length of the various main instruction words A program counter controller that functions to align and a bus that interfaces between the predecoder and the memory.

The processor core executes the instruction word from the main instruction set A, and executes the execution result and the instruction set type (IS).
Are stored in the data registers (R0 to R14) or in the program counter. The program status register (PSR) holds status bits, status bits, and mode bits after execution of each instruction. The predecoder processes the instruction word according to the instruction set selector PSR (ISS). The decoder decodes the instruction word of the instruction set A sent from the instruction fetcher. In this data processor, the processor core has only one instruction set mode, instruction set A, but the processor core is configured by the predecoder and the ISS.
Program instruction words belonging to other instruction sets can be executed.

When an instruction set switch occurs, one or more instruction words will specify a branch address in bits 31 through 1 of the data registers. The branch instruction is located at the 31st among the plurality of registers.
Copy ~ 1 bit into the program counter. The least significant bit of the program counter is always set to zero. At the same time, the branch instruction replaces the least significant bit in the registers with the I in the PSR.
Copy to SS. After execution of the branch instruction, the program counter will point to the first instruction (first instruction) of the new instruction set, and the ISS will indicate the new instruction set mode. When a new instruction word addressed by the program counter is input into the predecoder, the decoding method of the new instruction word is determined according to the new ISS value. If the ISS represents an instruction word of the instruction set B, the predecoder observes the input instruction word as the instruction set B, and uses the B subdecoder to convert the instruction word to the instruction set. Decode as an instruction word belonging to A. Thereafter, the predecoder outputs an instruction word of the instruction set A to the instruction fetcher. The instruction fetcher fetches the output from the predecoder into the data portion, and updates the TAG bit, the valid bit, and the ISS bit of the fetched instruction. Unlike the prior art, the instruction fetch hit is V
(Valid bit) is equal to 1, the tag bit of the PC is equal to the tag bit in the TAG portion, and PSR (I
SS) is equal to TAG (ISS). In addition, the decoder and program core always
It is only necessary to handle instruction words belonging to instruction set A.

It will be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to explain the present invention. .

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are intended to provide a further understanding of the invention, are a part of this specification, and are incorporated in this specification. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings illustrate several embodiments of the present invention and, by reference to the description, may be helpful in understanding the principles of the invention.

Hereinafter, preferred embodiments of the present invention will be described in detail. Preferred embodiments of the present invention are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 2 shows a block diagram of a data processing apparatus for executing a plurality of instruction sets.

The data processing apparatus according to the present invention can execute a plurality of instruction sets. The data processing device according to the present invention includes a processor core 200, a memory 210,
A program counter register (PC) 220, a plurality of data registers R0 to R14, a processor status register (PSR) 250, a predecoder 270, an instruction fetcher (Icache) 280, a decoder 290, and a program counter controller 225. And a bus 215.

The memory 210 is used to store a plurality of instruction words (eg, A instruction words or B instruction words) or data. Program counter register (PC) 220 is used to address (indicate an address) the next instruction word stored in memory 210. Data register (R0-R1
4) 230 is used to store data or the result of the instruction. The data register has two bit parts. When a particular branch instruction is executed, one or more bit portions are observed as instruction set select bits (IS) 240 and the other bit portions are observed as target addresses (TA) 245. I
The S bit will be stored in the PSR (processor status register) and the TA bit will be stored in the PC (program counter).

Processor status register (PSR) 250
Is used to store the state of the processor core 200. The processor status register 250 has one or more bits forming an instruction set selector (ISS) 260 for indicating the current instruction set. PSR (IS
S) can be set by a specific branch instruction according to one or more IS bits of R0 to R14.

The predecoder 270 contains one or more sub-decoders 272 for translating one or more instruction sets into a main instruction word. The main instruction word is sent to the processor core 20 via the decoder 290.
Used to be performed by 0. In this embodiment, processor core 200 can simply be implemented by executing only the main instruction word. However, the data processing apparatus according to the present invention can execute a plurality of instruction sets by the predecoder 270. In order to facilitate understanding, hereinafter, the main instruction word will be referred to as "A" instruction word, and the other instruction words will be referred to as "B", "C", and the like. The sub-decoder 272 is controlled by bits of the PSR (ISS) 260. The output of predecoder 270 is A
Instruction word.

A decoder 290 is used to decode the A instruction word. Processor core 200 is used to execute the A instruction word decoded by decoder 290. Program counter controller 22
5 modifies the program counter value (PC value) according to the ISS 260 to adapt to the length of various instruction sets. The bus 215 connects the predecoder 270 and the memory 210
Is the interface between

FIG. 3 is a flowchart showing an instruction word execution flow in the preferred embodiment of the present invention.
In this case, two instruction sets are applied to the processor.

First, at step 320, a plurality of instruction sets are stored in memory. For example, the memory stores the A instruction word and the B instruction word at the same time.
The A instruction word is X bits and the B instruction word is Y bits. Each instruction word is located at a separate memory address. When the processor core executes an instruction word, the program counter always points to the next memory address where the next instruction word is located. In other words, the processor core requests the next instruction word at step 320 by using the program counter. If X and Y are not equal, the PC value needs to be translated into the associated A instruction word address in the instruction fetcher.

The instruction fetcher stores only the A instruction word. Essentially, if X and Y are not equal, the address of the B instruction word in the instruction fetcher will be different from the memory address. For example, the B instruction word stored in the memory is (0, 2, 4, 6). When stored in the instruction fetcher, the address of the B instruction word is
(0, 4, 8, C). The instruction fetch controller must translate the address of the B instruction word to the correct address in the instruction fetcher.

In the next step 330, when the valid bit (V bit) is equal to 1, the tag bit of the TAG portion is determined to be equal to the tag bit of the PC, and the TAG (ISS) is changed to the PSR (ISS). Are considered equal. This means that the requested instruction word is DAT
The part A is fetched, meaning that the type of the fetched instruction word matches the type of the requested instruction word. In step 380, the instruction fetcher can directly output the captured A instruction word.

The TAG bit in the TAG portion of the instruction fetcher is an instruction word address consisting of m bits.
The N bits in the PC can be addressed in the TAG portion, and the PC tag bits will be compared to the tag bits in the TAG portion. If the tag bit of the PC is equal to the tag bit in the TAG portion, this means that the fetched instruction word address is equal to PC. To determine if the tag bit is valid, the V bit is set to invalid if the instruction fetcher is enabled and to valid if the instruction word is being fetched. The above-mentioned TAG (ISS) means the type of the fetched instruction word. When an instruction is fetched, the instruction type of the entire line is stored.

The decoder decodes the requested instruction word. In step 390, the processor core
The instruction is executed, and the execution result is stored in R0 to R14 or in a program counter. In the case of a branch instruction, the contents of the program counter need not be changed to control the execution flow.

When the instruction fetcher is wrong, ie, T
When AG (ISS) is not equal to PRS (ISS), the requested instruction word was not fetched into the instruction fetcher, or the entire line of instructions was one of the type of requested instruction word. Not mean. If this occurs, the instruction fetcher requests the bus using the PC value, as shown in step 340. The bus requests the memory using the memory address and waits at step 350 for the memory to return the requested line. When the instruction word is input to the pre-decoder, the pre-decoder selects one sub-decoder and transfers the input instruction word to PSR (I
SS), and in step 360 outputs the appropriate A instruction word to the instruction fetcher. In step 370, the output from the predecoder is stored in the instruction fetcher. The instruction fetcher uses the V bit and T
AG and set the first PSR (ISS) to TAG
(ISS), and the output from the predecoder is stored in the data portion. Then, the instruction word, as usual,
Be executed.

After execution of each instruction, the processor status register is updated to hold the status, status, mode, and ISS flags. The program counter is changed (updated) at step 395 to point to the next instruction word.

FIG. 4 is a flowchart showing an instruction set switching operation in the preferred embodiment of the present invention.

The instruction set is switched by software.
In particular, it is controlled by a specific branch instruction. Upon instruction set switching, one or more instruction words identify the branch address in the target address portion of R0-R14 and identify the instruction set bits in the IS portion, as shown in step 400.

In step 410, the branch instruction is identified, and the identified branch instruction is
0, the terminal addresses of R0 to R14 (T
A) Copy the part into the program counter. Other bits are set to zero. At the same time, the specified branch instruction replaces the IS part of R0 to R14 with the I part in the PSR.
Copy to SS.

After completion of the specified branch instruction, the program counter addresses the first instruction of the new instruction set, and the PSR (ISS) will indicate the mode of the new instruction set.

In step 330 in FIG. 3, the instruction fetcher is hit and TAG (ISS) is set to PS.
R (ISS). FIG. 5 shows the operation in the instruction fetcher for a more detailed explanation.
Referring to FIG. 5A and FIG. FIG. 5 (a) shows a conventional operation in the instruction fetcher. In this case, the comparison operation is performed without using the PSR (ISS). Address 510 is stored in the program counter (PC) and is applied to the instruction fetcher. The M bits of the address are
One input of the TAG portion is selected, and the N bits of the address 510 are compared with the tag bits of the TAG portion of the instruction fetcher. The valid bit in the TAG part is
Indicates whether the selected input is valid or invalid. IS in TAG part
The S bit indicates the input instruction type. In step 330 in FIG. 3, the V bit is "valid", the ISS bit of the TAG portion is equal to the ISS bit of the PSR, and the N bits of the address are set to the TA of the instruction fetcher.
Completion depends on whether it is equal to the tag bit in the G part.

FIG. 5B illustrates the operation in the instruction fetcher in the preferred embodiment of the present invention.
In this case, the PSR (ISS) is introduced during the comparison operation. Address 510 is stored in the PC and applies to the instruction fetcher. The N bits of the address are compared to the tag bits stored in the TAG portion of instruction fetcher 520. This is indicated by the m bits of address 510. TAG
The V bit in the part indicates whether the input is valid or invalid. PSR
(ISS) is introduced and compared to TAG (ISS). As shown in FIG. 3, the "determine whether the instruction fetcher has hit" step 330 is determined by the "AND" algorithm as follows. That is, 1. 1. whether N bits are equal to the tag bit in the TAG portion of the instruction fetcher; 2. Whether or not the V bit indicates “valid”; PSR (ISS) is T
AG (ISS). TAG (ISS) is TAG
Is the ISS bit in the PSR (IS
S) is the ISS bit in the PSR. When a plurality of instruction words having different bit numbers are mixed, for example, a 16-bit instruction word and 3
If a two-bit instruction word is intermingled, one or more bits in address 510 are introduced to clarify the first or second half of the instruction word. For example, as shown in FIG. 5 (b), a third bit is introduced for the compare operation and N for the TAG in the indicated register.
The algorithm for determining whether the bits are equal is N + 1 for the TAG in the indicated register.
The algorithm is changed to determine if the bits are equal.

As shown in FIG.
To translate one or more instruction sets into a main instruction word, such as the "A" instruction word described above,
One or more sub-decoders 272 are provided. FIG.
This will be described in more detail with reference to (a) and FIG. 6 (b). FIG. 6 (a) shows a conventional architecture for processing various instruction words. Data bus B
An example is shown where there are four instructions per line from IU 610. By being selected by switch 620, one of the four instruction words is applied to instruction fetcher memory 630. To execute the instruction word, one of the instruction words is communicated to a decoding step by a decoder. The transmitted instruction word is first mapped and then decrypted. After mapping and decoding, the instruction word is applied to the processor core and executed. In a preferred embodiment of the present invention, as shown in FIG. 6 (b), after selection by switch 620, the selected instruction word is applied to predecoder 650 and switch 660 simultaneously. If the instruction word is a B instruction word that is not the main instruction word,
The instruction word will be translated into a main instruction word, such as the A instruction word. The instruction word processed by the predecoder is applied to switch 660. Then, by selecting according to the ISS from the PSR, the instruction word is stored in the memory
70.

FIGS. 7A and 7B show a case where command words A and B are mixedly transmitted from the data bus. First, in FIG. 7A,
The instruction fetcher requests the BIU to set PC = 0,
BIU responds with line 710 with four instruction words. The type order is "ABBA". TAG
(ISS) always stores the type of the first instruction word, and the instruction fetcher processes the entire line according to the type of the first instruction word. For example, in the illustrated embodiment, since the type of the instruction word at PC = 0 is A, the TAG (ISS) becomes “A”. The data portion in the instruction fetch memory is filled with an "A" instruction type. The type order is “AAAAA”.

After n cycles, the BIU line has been written to the instruction fetcher and has been modified. C
The PU operates as PC = 4 and PSR (ISS) = B. However, at this point, TAG (IS
S) = A. This means that the instruction fetcher is wrong. In this case, the instruction fetcher is a PC
= 4, the BIU requests “ABB
A line having an instruction type order of "A" is responded. As shown in FIG. 7B, when PC = 8,
After processing the B instruction word by the predecoder,
TAG (ISS) = B, the data portion in the instruction fetch memory is filled with "B", and the instruction type order is "BBBB". At this point, the TAG (IS
S) stores that the line 710 of the data bus BIU is of the B type. TAG (ISS) is the PSR (I
SS). This means that the instruction fetcher hits. Regardless of the order of the instruction word types, the instruction fetcher can always determine and interpret the correct instruction type. In practice, it is rare that instructions of different types are mixed in one line.

The data processing device according to the present invention has several advantages over the conventional data processing device. One advantage is that the data processing device according to the invention can execute instruction words from a plurality of instruction sets. It is not limited to one instruction set or two instruction sets. As a result, the program creator can obtain extremely great convenience in producing the program. When a more effective instruction is requested, a more effective instruction set is used. If the memory is expensive, an instruction set that uses little memory is used.

Another advantage is low power consumption. In conventional devices, every instruction set requires a separate dedicated instruction decoder and logic controller. This is expensive and wasteful in terms of power consumption, because a dedicated instruction decoder is activated each time an instruction is fetched. However, in the present invention, the predecoder is activated only when the first instruction word is fetched. On average, the hit rate of the instruction fetcher is about 95%. This means that the predecoder in the present invention only needs to be activated five times to fetch 100 instruction words.

In addition, the CPU architecture does not need to be changed when implementing other instruction sets. All that needs to be changed is the bus interface and predecoder. This also makes the cost of the invention even more advantageous.

It will be appreciated that various modifications and changes may be made to the structure of the present invention without departing from the scope or spirit of the invention.
It will be clear to those skilled in the art. Therefore, it is intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

[Brief description of the drawings]

FIG. 1 is configured to execute two sets of instructions;
FIG. 9 is a block diagram illustrating a structure of a conventional data processing device.

FIG. 2 is a block diagram showing a preferred embodiment of a data processing apparatus of the present invention capable of executing a plurality of instruction sets.

FIG. 3 is a flowchart illustrating an instruction word execution flow according to a preferred embodiment of the present invention;

FIG. 4 is a flowchart showing a flow of switching instruction sets in a preferred embodiment of the present invention.

FIG. 5 is a diagram showing a comparison between the prior art and the present invention for the TAG portion in the instruction fetcher.

FIG. 6 is a diagram showing a comparison between the prior art and the present invention for the DATA portion in the instruction fetcher.

FIG. 7: TAG of instruction fetcher when A instruction word and B instruction word occupy the same memory line
FIG. 7 is a diagram for explaining the behavior of a portion and a DATA portion.

[Explanation of symbols]

 200 Processor core 210 Memory 215 Bus 220 Program counter register (PC) 225 Program counter controller 240 Instruction set select bit (IS) 245 Target address (TA) 250 Processor status register (PSR) 260 Instruction set selector (ISS) 270 Predecoder 272 Sub decoder 280 Instruction fetcher 290 Decoder R0-R14 Data register

Claims (9)

[Claims] 1. A data processing device for executing a plurality of instruction sets, comprising: a memory for storing a plurality of instruction words of the plurality of instruction sets; and a main instruction of the plurality of instruction words. A processor core for executing the word; a program counter register (hereinafter abbreviated as “PC” as necessary) for pointing to the next instruction word stored in the memory; A plurality of data registers for storing data; an instruction set selector for storing the state of the processor core and indicating the current instruction set of the plurality of instruction sets (hereinafter, required) A processor status register having an abbreviation "ISS" in accordance with the above.); And translating at least one of the plurality of instruction sets into a main instruction word. A pre-decoder for storing the main instruction word; and an instruction fetcher for storing the main instruction word; and for decoding the main instruction word and enabling the decoded main instruction word to be executed by the processor core. A decoder adapted to provide a decoded main instruction word to the processor core; and the PC in response to the ISS.
A program counter controller that changes the value of the main instruction word and thereby adapts the instruction word length of the various main instruction words; and a bus that interfaces between the predecoder and the memory. Characteristic device. 2. The device according to claim 1, wherein each of said data registers is provided with two bit portions, and at least one bit portion is provided with an instruction set selection bit (hereinafter referred to as “IS ], And the other bit portion is observed as a target address (hereinafter abbreviated as "TA" as necessary). 3. The apparatus according to claim 2, wherein the target address is a start address of the instruction set. 4. The apparatus of claim 2, wherein said ISS is set by a particular branch instruction according to said IS in said data register. 5. The apparatus of claim 1, wherein said predecoder comprises at least one subdecoder for translating at least one of said instruction set into said main instruction word. Equipment to do. 6. The apparatus according to claim 1, wherein switching of the sub-decoder is controlled according to the ISS, and an output from the pre-decoder is the main instruction word. An apparatus characterized in that: 7. The apparatus of claim 1, wherein a bit width of the main instruction word is not equal to another instruction word, and the instruction fetcher adds a bit for recognition to the P instruction word.
Apparatus adapted to convert the value of C to point to an appropriate main instruction word. 8. The apparatus of claim 1, wherein said ISS has at least one bit. 9. The apparatus of claim 8, wherein the ISS is set according to one or more of the ISs of the data register by a particular branch instruction.