TW552556B - Data processing apparatus for executing multiple instruction sets - Google Patents

Abstract

The present invention discloses a data processing apparatus for executing multiple instruction sets, which includes a system memory for storing a plurality of instructions in an instruction set; a processor core for executing the main instructions in the permanently instruction set; a program counter for indicating the address of the next instruction in the memory; a plurality of data buffers for storing the data of instructions; a processor status register for storing the status of the processor, wherein the processor status register includes an instruction set select (ISS) for indicating the current instruction set in these instruction sets; a predecoder for translating those not main instruction sets into the main instruction set; a cache memory for storing the main instructions, a decoder for decoding the main instructions into the control signal for the control processor core; a program count controller for modifying the value of program counter in response to the instruction set select to be matched with the instruction length different from the main instruction; and, a bus interface as the interface between the cache memory and the system memory.

Description

\ fl.doc / 006 \ fl.doc / 006 Date of revision 92 7.14 Supplementary notes, invention description: The present invention relates to a data processing device (Data Pr〇cessing

Apparatus), and in particular, a data processing device for executing Multiple Instruction Sets. The data processing device usually includes a processor core for executing program instructions of a preset instruction set. In addition to the processor core, it may further include a system, a body, to store and execute program instructions, and a program counter register to indicate the address of the next instruction in the memory. However, this type of device allows only one type of instruction set to be executed. If the device can execute more than one type of instruction set at the same time, it will be more flexible and more powerful. ^ Figure 1 is a block diagram showing the structure of a conventional data processing device that executes two instruction sets, and is disclosed in US No. 6,021,265 entitled "Interoperability with multiple mStructlon sets" As shown in Figure 1, a processor core in a conventional data processing device includes a register bank 30, a Booth Multiplier 40, and a shifter (Barrel Shifter). ) 50, a 32-bit Arithmetic Logic Unit (ALU) 60, and a Write Date Register 70. Other components of this device include a first instruction decoding and Logic controller (Instruction Decoder & Controller) 100, and a second instruction decoding and logic controller 110, a program counter controller (PC Controller) 140, a program counter (PC) 130, a multiplexer (Multiplexer) 90, a data read register 120 (Read- 552556

Modified date 92 7.14

Data Register), ~ Instruction pipeline 80, and a memory system 20. In this conventional device, for example, for two instruction groups, separate instruction decoding and logic control methods are required. Therefore, the first instruction decoding and logic unit 100 decodes the program instruction of the first instruction set, and the second instruction decoding and logic unit 110 decodes the program instruction of the second instruction set. The program instructions in the first instruction set are usually 32 bits, while the program instructions in the second instruction set are usually 16 bits. In this way, the programmer can choose between using a 32-bit instruction set with more functions, or using a 16-bit instruction to save memory size. A controller must be included to control which instruction decoder is used to decode the current program instructions. This is achieved by setting the program counting controller 140, or resetting the Most Significant Bit (MSB) or Least Significant Bit (LSB) in the program counter 130. In this way, the multiplexer 90 can be controlled to choose between the first and second instruction decoding and logic controllers 100 and 110. In such a conventional device, the type of the instruction set is determined in real time. In other words, the two instruction sets are mixed together, and the programmer can arbitrarily decide which instruction set to use in the program without processing them separately. However, in terms of hardware design, traditional devices require two decoders and a logic controller to continuously decode and consume power. Therefore, such a design will cause the processor core 10 to consume more power and require longer processing cycles. This will not be accepted by the trend of low power and local oscillation frequency pursued by everyone. The other is a traditional resource designed to execute two different sets of instructions 6

wfl.doc / 006 Amendment date 92 7.14 A supplementary device is disclosed in the US Patent No. 5,568,646 for mappingn2. The disclosed architecture does not require a controller to control which decoder is used to decode the current program instructions. In other words, there is no need to set or reset the maximum bit (MSB) or minimum bit (LSB) in the program counter. In a general pipeline processor, data processing is divided into three stages, and the first is the fetching stage.

Stage), one is the Decoding Stage, and the other is the Executing Stage. The design disclosed in this patent is a decoding stage during data processing. Two steps including mapping and generating control signals are performed in a decoding clock. Different fingers 1¾ sets of instructions are first mapped into a * main program group instruction, and then a control signal is decoded according to this main program group instruction to control the processor core to execute this main program group instruction. However, since the mapping action is required during the decoding phase, the cycle time during the decoding phase will be greatly increased. That is to say, it will be difficult to get into the design of rounds. In addition, its power consumption will also increase significantly. Similarly, this kind of hardware design will not be able to meet the needs of low power and high frequency trends. Therefore, the present invention provides a data processing device for processing multiple instruction sets, which can better meet the goals of low power and high frequency design. It includes a memory for storing instructions of a plurality of instruction sets, a processor core for executing one of the main instruction sets of the instruction sets, and a program counter register for specifying storage in the memory. The address of the next instruction, a plurality of data registers to store the data of these instructions, a processor state temporarily 552556 fl.doc / 006

'Positive Charger (PSR), the revision date 92.7.14 is used to store the state of the processor core, where the processor state register includes an Instruction Set Selector ^ ISS to indicate these The current instruction set in the instruction set, a pre-decoder, is used to translate non-main instructions into the main instruction and output it, and a cache is used to store the Icache. The main instruction, a decoder, is used to decode the main instruction. The processing core is used to execute the main instruction decoded by the decoder. A program counter controller is used to adjust the program counter register to Matches commands that differ in length from the main command, and a bus that acts as an interface between system memory and cache memory. The processor core executes the instructions from the main instruction group A and stores the results in the data registers R0 ~ R14. If it is a branch instruction, it is stored in the program count register. After executing each instruction, the program status register (PSR) records the execution flags (Flags), instruction set selection flags (ISS), and execution mode (Mode). To maintain the latest processor state. The pre-decoder converts non-main instruction group instructions into main instructions according to the instruction group selection flag. Then, the cache memory stores the output of the pre-decoder in the data memory (Data Ram) and stores the instruction set selection flag in the tag memory (Tag Ram), and the decoder stores the instruction set of the cache memory. The instructions are decoded into control signals from the processor core. In this data processing device, the processor core processes only the instructions of the main instruction set. However, the processor core can use the pre-decoder and the instruction set selection flag to enable it to execute program instructions of other instruction sets. When the instruction set change occurs, one or more instructions will store the branch address (Target Address, TA) in the bit of the data register, the same as 8 552556

l.doc / 006 Revision date 92.7.14

.¾¾ Store the new Instruction Select Flag (IS) in bit 0 of the data register. Next, a specific branch instruction (Branch and Exchange, BX) will overwrite bits 31 ~ 1 in the register to the program counter, and set bit 0 in the program counter to zero. At the same time, the specific branch instruction copies the instruction set selection flag (IS) in the data temporary storage to the instruction set selection flag (ISS) in the program status register. After executing the branch instruction, the program counter will determine the address of the first instruction in the new instruction group, and the instruction group selection flag indicates a new instruction group mode. When a new instruction at the address of the program counter is input into the pre-decoder, the pre-decoding method of the new instruction is determined by the new instruction group selection flag. If the instruction group selection flag indicates an instruction group B, the pre-decoder will treat the instruction as coming from instruction group B, and use the pre-decoder to convert this input instruction into an instruction of instruction group A. Then, the pre-decoder will output the instruction of the instruction group a to the cache memory. If the instruction group selection flag indicates an instruction from instruction group A, the pre-decoder treats it as an input instruction from instruction group A and passes it to the cache memory. The cache memory only stores the instructions of instruction group A. The decoder and the processor core also always process the instructions of instruction group a. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: Table 1 is a A block diagram showing the structure of a conventional data processing device for executing one of two instruction sets. Series 2 is a block diagram illustrating a preferred embodiment of the present invention. 9 552556

l.doc / 006 Revision date 92.7 14 A data processing device for processing multiple instruction sets. FIG. 3 is a flowchart illustrating a flow of executing instructions in a preferred embodiment of the present invention. FIG. 4 is a flowchart illustrating a flow of instruction conversion in a preferred embodiment of the present invention. Figures 5A and 5B show the cache operation of the preferred embodiment of the present invention. Figure 6A shows a conventional architecture that is conventionally used to handle different types of instructions. Figure 6B shows the architecture for processing different types of instructions according to the preferred embodiment of the present invention. Fig. 7A shows a conventional processor, processing method for mixed instructions. Fig. 7B shows a processing device according to a preferred embodiment of the present invention, and a processing method for mixed instructions. Description of the marks of the drawings: 10 processor core 20 memory system 30 temporary storage database 40 Booth multiplier 50 shifter 60 32-bit arithmetic logic unit 70 write data register 80 instruction buffer 90 multiplexer 10 552556 Amendment B 92.7 14

06439twfl.doc / 006 Correction supplement 100 First instruction decoding and controller 110 Second instruction decoding and controller 120 Data read / write register 130 Program counter 140 Program counter controller 200 Processor core 210 Memory 215 Bus 220 Program Count register 225 Program count control 230 Data register 240 Instruction set selection flag bit 245 Target address 250 Processor status register 260 Instruction set selection flag 270 Pre-decoder 272 Decoder 280 Cache memory 290 Decoder 510 Address register 512 Instruction set selection flag 520 Cache tag memory 610 Bus line 620 640 660 Switcher 630 670 Cache data memory

11 552556 Modified date 92.7.14 0643 9twf 1 .doc / 006 650 Pre-decoder 310-395 Process flow of instruction execution 400-420 Process flow of instruction group conversion For example, please refer to Figure 2, which is shown in A data processing device for executing multiple instruction sets in a preferred embodiment of the present invention is particularly directed to a pipeline processor. The data processing device provided by the present invention is used to process multiple instruction sets (Multiple Instruction Set). It includes a processor core 200, a memory 210, a program counter (PC) 220, a plurality of data registers R0 ~ R14, and a processor status register (PSR) 250. , A cache memory (Icache) 280, at least one pre-decoder 272, a decoder 290, a program counter controller (PC Controllo 225, and a bus 215. The memory 210 is used to store multiple Instruction code (Multlple Instruction Word) (for example, A or B instruction) or data. Program counter register (PC) 220 is used to determine the address of the next instruction stored in memory 210. Data register (R0 ~ R14) 230 is used to store instruction data or results. There are two parts in the bit in the data register 230. When a special Branch Instruction is executed, one or more Each bit will be regarded as the instruction set selection bit (Instructl0n Set Selection bits' is called IS) 240, and the other bits will be regarded as the target address (Target address, called TA) 245. Instruction set selection Bit IS will have processor status Register (program status Register * 'PSR), and the target address TA will be stored in the program counter 12 552556 --964 «twfl.doc / 006 correction date 92.7 14 _ —. When the instruction group is converted, the instruction The selection bit (IS) is the flag of the new instruction set, and the target address 245 is the start address of the new instruction set. The processor state register (PSR) 250 is used to store the state of the processor core 200. This processor The state register 250 includes one or more bits in the Instruction Set Selector (hereinafter referred to as ISS) 260 to indicate the current instruction set. For convenience of explanation, the processor state register One or more bits of the instruction set selection flag (ISS) 260 in (PSR) 25 are referred to as PSR (ISS). The PSR (ISS) can be based on one or more of the data registers R0 to R14. The IS bit is set by a specific branch instruction. The pre-decoder 270 includes one or more sub-decoders 272 to translate one or more instruction sets into a main instruction. (Primary Instruction Word). This main instruction is passed through the decoder 290 It is executed by the processor core 200. In this embodiment, the processor core 2000 can simply execute only the main instruction. The data processing device of the present invention can execute many different types of instruction sets by the pre-decoder 270. In order to understand the embodiments of the present invention simply, " A " is the main instruction below, and other instructions are indicated by the instruction '' B 'or' 'C' '. Among them, the instruction B or C is a subset of the main instruction '' Απ, and can be converted into the instruction '' A 'by the instruction ΠB ". The decoder 272 is controlled by PSR (ISS) this time, and the output of the pre-decoder 270 is the main instruction a. The cache memory 280 is used to store main instructions. The tag memory in the cache memory stores the tag bits, valid bits, and instruction sets in the processor status register of the Memory Line. 13 552556 Revision date 92.7.14- ---- 0 ^ 4 ^ 9twfl .doc / 006%

Amendment Exemption One, three flags PSR (ISS). The data memory in the cache memory stores instruction words. Because the cache memory only stores the main instruction set A, the instruction set selection flag (ISS) must be stored in the tag memory for identification. The instruction set selection flag stored in the tag memory is hereinafter referred to as TAG (ISS). If the bit width of the A instruction is different from other instructions, for example, the A instruction bit width is 32 bits and the B instruction bit width is 16 bits, then the tag memory 520 of the cache memory 280 needs to be in the tag bit. An additional bit is added to the tag to distinguish whether the instruction code stored in the data memory is the instruction indicated by the program counter when the TAG (ISS) instruction is the B instruction set. Basically, if X is not equal to Y, the address of the B instruction in the cache will be different from the address in the memory. For example, if the address of the B instruction stored in the memory is (O,〗 〆 /) or (8, A, C, E). When it is stored in the cache memory, the address of the B instruction will be changed to (0, 4, 8, C). Therefore, the tag bit in the tag memory will have one more bit to distinguish whether the stored command is (0, 2, 4, 6) or (8 persons C, E). The decoder 290 is used to decode the A instruction. The processor core 2000 is used to execute the A instruction decoded by the decoder 290. The program count controller 225 corresponds to the instruction set selection flag PSR (IS S) 260 to modify the program counter 値 (hereinafter called PC Value) ′ to conform to the length of different instruction sets. The bus 215 is an interface of the pre-decoder 270 and the memory 210. FIG. 3 is a flowchart of instruction execution according to a preferred embodiment of the present invention. In this example, only the two types of instruction sets applicable to the processor are explained. Of course, the present invention is not limited to this. $ In step 32〇, the processor core (Process Core) uses the program number 14 552556 --- iFslfl.doc / 006 to modify the date 92.7.14 値 (PC Value) to read instructions from the cache memory . Multiple instructions are stored in memory. For example, the memory stores both the A command and the B command. Among them, the bit of the A instruction is X, and the bit of the B instruction is Y. Each instruction occupies a different memory address. When the processor core executes an instruction, the program counter always points to the memory address of the next instruction. That is, in step 320, the processor core uses the program counter to obtain the next instruction. In the following step 330, it is determined whether the next instruction indicated by the program register is stored in the cache memory (tnt), that is, as shown in the icon.

"Icache Hit?" This judgment step is determined by three conditions. The first condition is whether the valid bit (Valid bh) in the cache memory is valid, and this valid bit represents whether the tag bit (tag) in the tag memory is valid. The second condition is whether the tag bits of the tag memory in the cache memory address are equal to the tag bits (tag bhS) stored in the program counter. In addition, the third condition is whether the TAG (ISS) in the cache memory address is equal to the PSR (ISS) in the processor status register.

If the above three conditions are met, that is, Icache Hh, it means that the required instruction already exists in the data memory in the cache memory, and the type of the stored instruction (Cached Instruction Word) is the same as the required type Fit. Therefore, immediately after step 380, the cache memory will output the instruction code to the decoder, and the decoder will decode the instruction. The tag bits of the tag memory of the cache gfi memory are m bits in the program counter. The N bits in the program counter can address the label memory to output the label bits, and the label bit in the program counter is 15 552556 ------ 06.439twfl.doc / 006 Modified date 92.7.14 η η Modified- One bit) can be compared with the tag bit output in the tag memory. If the tag bits in the program counter are equal to the tag bits output in the tag memory, it means that the address of the stored instruction is equal to the address in the program counter. In order to determine whether the tag bit is valid, the above-mentioned legal bit will be set to Invalid when the cache memory is turned on, and set to Valid when the instruction is temporarily stored. The above TAG (ISS) represents the type of instruction stored. When the instruction is cached, the instruction type of the entire line will be memorized. This line is for pipelined lines. For example, each line of the pipeline can transmit four instructions at the same time.

Then in step 390, the processor core will execute the instruction and store the result in R0 ~ R14 or the program counter. If this instruction is a branch instruction, the program counter needs to be changed to control the execution flow.

If the above three conditions are not all met, that is, there is no Icache Hit, that is, TAG (ISS) is not equal to PSR (ISS), or the instruction is not stored in the cache memory (Icache Miss). When such a situation occurs, as shown in step 340. This bus will use the counter of the program counter to request memory and wait for the memory to respond to the required lines, as shown in step 350. When the instruction is replied from the memory and input into the predecoder, the pre-decoder will select the sub-decoder according to the PSR (ISS), and translate the input instruction into the relevant A The instruction 'is not the same as step 3 6 0. In step 370, the output of the pre-decoder will be stored in cache memory. And this cache memory will set the legal bit, tag bit, store PSR (ISS) to TAG (ISS), and store the data output from the pre-decoder to the cache memory 16 552556 Correction date 92.7.14

l.doc / 006 Then, the instructions will be executed as usual. After each instruction is executed, the Processor Status Register will be updated to maintain the latest flags, states, modes, and ISS flags. As described in step 395, the program counter will be updated according to ISS 値 to indicate the instruction set of the next instruction. Referring to Fig. 4, it shows the flow of steps of instruction set conversion in a preferred embodiment of the present invention. The conversion of the instruction set is controlled by software, and the symbol is a specific Branch and Exchange Instruction. When an instruction group conversion occurs, in step 400, one or more instructions will write the branch address (Target Address) of the new instruction group into the target address (TA) section of the registers R0 ~ R14. And write the selection flag of the new instruction set into the instruction set selection bits (IS) of the registers R0 ~ R14. In step 410, a specific branch instruction copies the target address (TA) section in the registers R0 to R14 to the program counter, as described in the next step 420. All other bits in the program counter are set to zero. At the same time, a specific branch instruction overwrites 1s of R0 ~ R14 to the ISS area of PSR. After the designated branch instruction is completed, the program counter will position the first instruction in the new instruction set ’and PSR (ISS) will indicate the new instruction set mode. In step 330 in the above figure 3, determining whether the cache memory hits (Hh) and whether TAG (ISS) is equal to PSR (ISS) will be described in detail in Figures 5A and 5B below. Please refer to FIGS. 5A and 5B, which show operations in the cache memory. In Figure 5A, it shows 17 552556 06439twfl.doc / 006 Rev. Date 92.7 "4‘ General cache operation. This is an example without PSR (ISS) for comparison. The address signal 510 is stored in the program counter (PC) and transmitted to the cache memory 520. The m bits of the address signal 510 are used to rotate into the tag memory and output the corresponding tag bits. The N bits of the address signal 510 are used to compare with the output tag bits (Comparison Operation). A valid bit (VaHd Blt) in the tag memory will represent whether the selected output tag bit is valid or invalid.

In FIG. 5B, the operation method in the cache memory of the preferred embodiment of the present invention is shown, in which PSR (ISS) is used to add the comparison operation (Comparison Operation). The address signal 510 is stored in the program counter. The m bits in the address signal are input to the tag memory, and the tag memory outputs the corresponding tag bits. The N bits in the address signal 510 are compared with the tag bits output by the tag memory. A valid bit (Valid Bh) in the tag memory will represent whether the output tag bit is valid or invalid. In this embodiment, PSRCISS) will be used to determine whether it is equal to TAG (ISS) in the tag memory. The PSR (ISS) is one or more bits of the instruction set selection flag (ISS) in the aforementioned processor state register (PSR). TAG (ISS) represents the ISS bit in the tag memory. If instructions with different numbers of bits are mixed, for example, a 16-bit instruction is mixed with a 32-bit instruction, another extra bit at address signal 510 can be used to identify the first half or the first half of the instruction. The two halves. For example, as shown in Figure 5B, this interpretation method is to change whether the original N bit is equal to the tag bit of the specified tag memory to whether the N + 1 bit on the address signal 510 is equal to 18 552556

W9t vvfl.doc / 006 Supplemental memory N + l bit correction date 92 7.14 Pre-decoding benefit 27 with one or more secondary decoders π as shown in Figure 2 is used to convert non-primary Instruction translation is the main instruction, such as the above-mentioned A instruction. For a more detailed description, please refer to FIGS. 6A and 6B. Figure 6A shows the traditional head: structure that is known to handle different types of fingers. In the parent line (Line), for example, four instructions are transmitted from a Bus Interface Unit (BIU) 610. Select by Switch 620, one of the commands will be sent to the data memory 630 of the cache memory. To execute the instruction, one of the instructions is passed to the decoder Decode. The transmitted instructions are first mapped and then decoded. After mapping and decoding, this instruction will be passed to the Processor Core for execution. In the preferred embodiment of the present invention, as shown in FIG. 6B, after the selection of the switch 64o, the selected instruction will be transmitted to the pre-decoder 650 and the switch 660 at the same time. If the selected instruction is a B instruction, since it is not the main instruction, the pre-decoder 650 will translate this B instruction into a main instruction, such as the A instruction. This pre-decoded instruction will be passed to the switcher 660. With the ISS bit transmitted from the PSR, this instruction will then be passed to the DRAM 670 in the cache. Figures 7A and 7B explain the use of a mixed command line from the bus, for example, there are both A and B commands in the line. First, please refer to Figure 7A. The cache memory will request the bus BIU with the program counter as 0, and the bus BIU will respond to line 710 including four, ABBA, and command format lines. Head TAG (ISS) then ^ will-remember the reward of the first instruction, and cache the hit of the body 552556

l.doc / 006 Revised 92.7 14

Hit ·) will also be based on TAG (ISS). For example, as shown in this embodiment, the TAG (ISS) is the instruction A, because the instruction at the address of 0 in the program counter is the A instruction. And here the data memory system of caching billions is full of A instruction types. The order of this instruction will become "AAAA", as shown in the figure. After n clocks, the bus BIU line may have been written into the cache memory and has changed. The central microprocessor will start Program counter 値 PC = 4 of PSR (ISS) = B. But at this stage TAG (ISS) = A, it means that the cache memory will not hit (M1SS). Once again, the cache memory will be PC = 4 requires the bus BIU, and the bus BIU will respond to the four command lines of "ABBA" again. Then, please refer to Figure 7B. The instruction of PC = 4 will be converted by the pre-decoder and stored in the data memory and output to the decoder. At this time, TAG (ISS) = B, the data memory system of the cache memory is filled with ΠB ”, and the order of its instructions is‘ ΈΒΒΒ ”. After n clocks, the central microprocessor starts to execute the instruction of PC = 8. At this time, TAG (ISS) is equal to PSR (ISS), which represents the cache. The memory hit (Hh) and the cache memory can output instructions to the decoder. Regardless of the order of the instruction types, the cache will determine the correct instruction type and switch to the main instruction. In actual operation, such a situation of mixing different instruction types on the same line is quite rare. The data processing device of the present invention has a number of advantages over conventional data processing devices. One of them is that the data processing device of the present invention can execute multiple instructions, which is not limited to one or two instructions. In this way, program compilers have great flexibility in designing programs. If performance is the main consideration, you can use more powerful instructions, such as 20 552556 in 32 bits ---------- 0645 ^ twf 1. doc / 006

If the memory capacity is the main consideration, such as a 16-bit instruction. Another advantage is to reduce the power consumption. The correction date of 92.7.14 can be used to save memory. On traditional devices, all instruction groups will have their own designated instruction decoder and logic control unit. This is a very expensive and power-hungry design because multiple instruction decoders and logic control units need to operate continuously. However, in the present invention, the pre-decoder only needs to be performed when the first instruction is fetched, and then the converted result is stored in the cache memory. Generally speaking, when the cache memory hit probability is 95%, it means that the pre-decoder in the present invention only needs to operate 5 times in 100 instruction fetches. This can significantly reduce the power consumed. Another advantage is that it reduces the cycle time of the Decode Stage. In conventional devices, whether using two decoders or mapping to process multiple instruction sets, the cycle time in the decoding phase is increased. Especially the use of mapping will greatly increase the cycle time of the decoding stage. These traditional devices will increase the overall cycle time of the central processing unit. However, in the present invention, no matter how many instruction sets, only one instruction decoder is used. The instruction decoder only decodes instruction types that are the main instruction set, so it does not increase any cycle time during the decoding phase. At the same time, in high-frequency designs, cache memory generally uses synchronous memory (Synchronous Ram), so the pre-decoder will not increase the cycle time in the Fetch stage. The present invention has been disclosed as above with preferred embodiments, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Protection range 21 552556

0643 9Γ \ Amendment 9twfl.doc / 006 Amendment date 92.7.14 One # 7¾½ attached to the scope of the patent application shall prevail. twenty two

Claims (1)

y ^ 643§twfl.doc / 006 Amendment date 92.7.14: Wei 丨 Shi \; Patent application scope: 1. A data processing device for executing multiple instruction sets, including: a memory for storing multiple instructions A group of instructions; a processor core to execute one of the main instructions; a program counter register to determine the address of the next instruction stored in the memory; a plurality of instructions A data register for storing data of the instructions; a processor state register for storing a state of the processor core, wherein the processor core includes an instruction set selection flag to indicate Current instructions of the instruction sets; a pre-decoder for converting at least one of the instruction sets into the main instruction; a cache memory for storing the main instruction, wherein the cache memory includes an instruction The group selects a flag to indicate the instruction type of the stored instruction line; a decoder to decode the main instruction, wherein the processor core is used to execute the main instruction decoded by the decoder; ; A program count control, corresponding to the instruction set selection flag, to modify a program counter 値 to adjust the length of the instruction different from the main instruction; and a bus, as the cache memory and the system memory Interface. 2. The data processing device for executing multiple instruction sets as described in item 1 of the scope of patent application, each of these data registers has two bit sections, at least one of which is regarded as an instruction set Select the bit, supplement with 552556 Amendment 1-and-tfl.doc / 006 Amendment Date 92.7.14 Bit is regarded as a target address. 3. The data processing device for executing multiple instruction sets as described in item 2 of the scope of patent application, the target address is one of the instruction set starting address 0 4. Use as described in item 2 of the scope of patent application A data processing device for executing multiple instruction sets, in which bits are selected according to instructions in the data registers, and the instruction set selection is set to a specific branch instruction. 5. The data processing device for executing multiple instruction sets as described in item 1 of the patent application scope, wherein the pre-decoder includes at least one secondary decoder to translate at least one instruction set into the main instruction. 6. The data processing device for executing multiple instruction sets as described in item 1 of the scope of the patent application, wherein the cache memory adds an instruction set selection bit to indicate the instruction type of the stored instruction. 7. The data processing device for executing multiple instruction sets as described in item 1 of the patent application scope, wherein the instruction selector includes at least one bit. 8. The data processing device for executing multiple instruction sets as described in item 1 of the scope of the patent application, wherein the instruction set selection flag can be specified by one or more instruction register bits of a data register. Branch instruction setting. twenty four