KR100407452B1 - Data processing apparatus for executing multiple instruction sets - Google Patents

Abstract

A data processing device for executing multiple instruction sets includes a memory for storing a plurality of instructions of the multiple instruction set, a processor core for executing the primary instructions of the instructions, and a program counter register for addressing the next instruction stored in the memory. (PC), a plurality of data registers for storing the data of the instructions, and an instruction set selector (ISS) for storing the state of the processor core and indicating the current instruction set of the instruction set. The processor core register, a predecoder for moving and outputting at least one of the instruction set to the primary instruction, an icache for storing the primary instruction, and decoding the primary instruction, Is used to execute a primary instruction decoded by the decoder, and the primary instruction. And a program counter controller responsive to the instruction set selector to modify the value of the program counter to match the length of the other instructions, and a bus interface interfaced between the predecoder and the memory.

Description

DATA PROCESSING APPARATUS FOR EXECUTING MULTIPLE INSTRUCTION SETS}

The present invention relates to a data processing apparatus. In particular, the present invention relates to a data processing apparatus for executing multiple instruction sets.

The data processing apparatus generally includes a processing core for executing program instructions of a predetermined instruction set. With this processing core, the data processing apparatus may also include a data memory storing executable program instructions and a program counter register indicating an address in the memory of the next instruction. However, this type of device allows execution of only one instruction set. Devices that are executable and operable in one or more instruction sets are much more flexible and powerful.

1 is a block showing the structure of a conventional data processing apparatus designed to execute two instruction sets, as disclosed in US Pat. No. 6,021,265, entitled "Interoperability with multiple instruction sets." It is also.

As shown in FIG. 1, the processor core 10 of a conventional data processing apparatus includes a register store 30, a booth multiplier 40, a barrel shifter 50, and 32 bits. An arithmetic logic unit (ALU) 60 and a write data register 70 are provided.

Other components in the apparatus include a first command decoder and logic controller 100, a second command decoder and logic controller 110, a program counter controller 140, a program counter (PC) 130, and a multiplexer. 90, a write-data register 120, an instruction pipeline 80, and a memory system 20.

In such a conventional apparatus, separate instruction decoders and logic controllers are required for both instruction sets. Thus, the first command decoder and logic controller 100 decodes the program instructions of the first instruction set, and the second command decoder and logic controller 110 decodes the program instructions of the second instruction set. Program instructions in the first instruction set are generally 32 bits, and program instructions in the second instruction set are generally 16 bits. In this way, programmers have the option of using a more powerful instruction set of 32-bit instruction sets or storing and using the instruction set of 16-bit instruction sets in memory.

Control means must be included to control the instruction decoder for decoding the current program instruction, which instruction is performed by the program counter controller 140 which sets or resets the most significant or least significant bit in the program counter 130. The control means also alternately control the multiplexer 90 to select between the first command decoder and logic controller 100 and the second command decoder and logic controller 110.

In the prior art of such a structure, the instruction set type can be determined in real time. That is, the two sets of instructions can be mixed together, and these two sets need not be processed separately. However, two decoders and logic control circuits are needed in the design. More power consumption and larger chip size are needed for processor core 10, which is not suitable for the trend of developing less power consumption and smaller size processors.

Another conventional data processing apparatus designed to execute two instruction sets is disclosed in US Pat. No. 5,568,646, entitled " Multiple instructions set mapping. &Quot; The configuration does not require control means for controlling the command decoder to decode the current program instruction. That is, there is no need to set or reset the most significant or least significant bit in the program counter.

There are three stages for a pipeline-type processor: a fetching stage (pipeline stage), a decoding stage, and an execution stage. The patent is designed to use a decoding step in data processing. During the decoding cycle, two steps are performed, including mapping and generating the control signal. Different instruction sets are mapped so that they move first to the primary instruction set. The primary instruction set can be executed in the next execution step.

However, the instruction sets must be mapped during the decoding phase, in which case the decoding stage loading is increased. This means that high frequency design is difficult. Also, in the case of a 95% hit rate, power consumption increases significantly. This does not meet the requirements of the current trend.

1 is a block diagram showing the structure of a conventional data processing apparatus designed to execute two instruction sets.

2 is a block diagram of a preferred embodiment of a data processing apparatus for executing multiple instruction sets in accordance with the present invention.

3 is a flow chart of a preferred embodiment showing the instruction execution flow in accordance with the present invention.

4 is a flow chart of a preferred embodiment showing an instruction set switching flow in accordance with the present invention.

5 is a comparison of the TAG portion of the iCache between the prior art and the present invention.

6 is a comparison of the DATA portion of the iCache between the prior art and the present invention.

FIG. 7 illustrates the operation of the icache in the TAG part and the DATA part when the commands A and B occupy the same memory line.

It is therefore an object of the present invention to provide a data processing apparatus for executing multiple instruction sets without extra power consumption or without slowing down the clock frequency.

The data processing apparatus includes a memory for storing a plurality of instructions of a multiple instruction set, a processor core for executing the primary instructions of the instructions, a program counter register (PC) for addressing the next instruction stored in the memory, instructions A processor status register comprising a plurality of data registers for storing data including an IS bit and a type of the processor, an instruction set selector (ISS) for storing a state of the processor core and indicating a current instruction set of the instruction set; A predecoder for moving and outputting at least one of the instruction set to the primary instruction, an icache for storing the primary instruction and managing the TAG, Valid and ISS information of the cache instruction, and the primary instruction. Decode used by the processor core to execute the primary instructions decoded by the decoder. And it provided with a bus interface between the first instruction and the other instructions to adjust the length of the program counter controller responsive to the instruction set selector to modify the value of the program counter, and a pre-decoder and a memory.

The processor core executes instructions from the primary instruction set A, and stores the result and instruction set type (IS) in the data registers R0 to R14 or program counters. The processor status register (PSR) holds the condition, status, and mode bits after execution of each instruction. The predecoder predecodes the instructions according to the instruction set selector (ISS). The decoder decodes the instructions of the instruction set A generated from the icache. In such a data processing apparatus, the processor core has only one type of instruction set, which is instruction set A, but can execute program instructions from other instruction sets by the predecoder and the ISS.

When a switch in the instruction set occurs, one or more instructions assign a branch address to bits 31-1 of the multiple data registers. Branch instructions copy bits 31 to 1 of multiple registers into the program counter. The least significant bit of the program counter is always zero. Similarly, branch instructions copy the least significant bits of multiple registers into the ISS of the PSR. After executing the branch instruction, the program counter will address the first instruction of the new instruction set, and the ISS will indicate the new instruction set mode. The new instruction addressed by the program counter is input to the predecoder and the decoding methodology of the new instruction is determined by the new ISS value. When the ISS represents instruction set B, the predecoder represents the input instructions as in instruction set B, and uses the B subdecoder to decode input instructions, such as instructions from instruction set A. The predecoder then outputs the instructions in instruction set A to the icache. ICache stores the output of the predecoder in the data portion and updates the TAG, Valid and ISS bits of the instructions stored in the TAG portion. Unlike the prior art, the icache hit means V is equal to one, the tag bit of the PC is equal to the tag bit of the TAG portion, and the PSR (ISS) is equal to the TAG (ISS). The decoder and processor core always process instruction set A.

It is to be understood that the above general description and the following detailed description are intended to provide further explanation of the invention as illustrative and claimed.

Hereinafter, a data processing apparatus for executing a multi-command set according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an embodiment of a data processing apparatus for executing a plurality of instruction sets.

The data processing apparatus of the present invention is for executing multiple instruction sets. The device includes a processor core 200, a memory 210, a program counter register (PC) 220, a plurality of data registers (RO-R14) 230, a processor status register (PSR) 250, a predecoder ( 270, an eye cache 280, a decoder 290, a program counter controller 225, and a bus 215.

The memory 210 is used to store multiple instructions (eg, A or B words). The program counter register (PC) 220 is used to address the next instruction stored in the memory 210. Data registers (RO-14) 230 are used to store data or command results. There are two bit sections in the data register. When a given branch instruction is executed, one or more bits are represented by the instruction set select bit (IS) and the other bits are represented by the target address (TA) 245. The IS is stored in the PSR (Processor Status Register) and the TA is stored in the PC (Program Counter Register).

The processor status register (PSR) 250 is used to store the state of the processor core 200. The processor status register 250 has one or more instructions of the instruction set selector (ISS) 260 to indicate the current instruction set. The PSR (ISS) is set by a branch instruction defined according to one or more IS bits of RO-R14.

The predecoder 270 includes one or more sub decoders 272 for converting one or more instruction sets into first instructions. The first instruction is used to execute the decoder 290. In this embodiment the core 200 is simply executed by simply executing the first instruction. However, the data processing apparatus of the present invention may execute multiple instruction sets by the predecoder 270. For the sake of understanding, the first command will be referred to as an "A" command, and the other command will be referred to as "B" or "C". The sub decoder 272 is controlled by a PSR (ISS) 260. The output of the predecoder 270 is an "A" command.

The decoder 290 is used to decode the "A" instruction. The processor core 200 is used to execute the "A" instruction decoded by the decoder 290. The program counter controller 225 responds to the ISS 260 to adjust the length of another instruction set and modify the program count value (PC value). The bus 215 interfaces between the predecoder 270 and the memory 210.

Reference is made to the flowchart of FIG. 3 showing an instruction execution flow in accordance with the present invention.

The processor is used for two instruction sets.

First, in step 320 multiple sets of instructions are stored in memory. For example, the memory stores "A" and "B" instructions at the same time. The "A" instruction is X bits long and the "B" instruction is Y bits long. Every instruction specifies an individual memory address. When the processor core executes an instruction, the program counter always points to the next memory address of the next instruction. In other words, the processor core uses a program counter to request the next instruction in step 320. If X (bit length of the A instruction) is not equal to Y (bit length of the B instruction), then the PC value is needed to translate to the "A" instruction address associated with the icache.

Icache only stores the "A" command. In essence, if X (the bit length of the A instruction) is not equal to Y (the bit length of the B instruction), then the addresses of the " B " instructions in the icache are different from the addresses of the memory. For example, the address of the "B" instruction stored in memory is (0,2,4,6). When it is stored in the icache, the address of the "B" instruction will change to (0, 4, 8, C). An icache controller is needed to translate the address of the "B" instruction into the change address of the icache.

In step 330, if there is one valid bit, the tag bit of the TAG part is the same as the tag bit of the PC, and the TAG (ISS) is the same as the PSR (ISS). This means that the requested instruction is cached in the data portion and the cached instruction type matches the requested instruction type and in step 380 the icache can output the cached "A" instruction directly.

The tag bit in the TAG portion of the icache is the m bit of the instruction address. The N bits of the PC can define the entry of the TAG portion and the tag bits of the PC are compared with the tag bits of the TAG portion. If the tag bit of the PC is the same as the tag bit of the TAG portion, this means that the cached instruction address is the same as the PC. To determine if the tag bit is valid or not, the V bit will be set to invalid upon icache enable and set to valid when the instruction is cached. The full line command type is remembered when the command is cached.

The decoder decodes the requested instruction. In step 390, the processor core executes an instruction and stores the result of R0-R14 or program counter 390. In the case of branch instructions, the program counter items need to be changed to control the flow of execution.

If the icache is missed or the TAG (ISS) is not equal to the PRS (ISS), it means that the requested instruction is not cached in the icache and the entire instruction does not match the requested instruction type. When this happens, as in step 340, the iCache uses the PC value to request the bus. The bus uses the memory address to request memory and waits in memory to return the required line at step 350. When an instruction is input to the predecoder, the predecoder selects one sub decoder to convert the input instruction according to the PSR (ISS) and outputs the associated "A" instruction for the cache in step 360. In step 370, the output of the predecoder is stored in the icache. The eye cache designates a valid bit, a tag, and a member from the first counter PSR (ISS) to TAG (ISS) and stores a predecoder output in the data unit. The command is then typically executed.

After each instruction execution, the processor status register is updated to hold the condition, status mode and ISS flags. The program counter is modified in step 395 to specify the next instruction.

Reference is made to FIG. 4 showing an instruction set switching flow in accordance with the present invention.

Instruction set switching is software controlled and in particular controlled by designated branch instructions.

In step 400, when an instruction set switch occurs, one or more instructions specify a branch address in the target address portion of R0-R14 and an instruction set bit in the IS section.

The branch instruction designated in step 410 copies the end address TA of R0 to R14 into the program counter of step 420. The other bits are set to zero. At the same time, the designated branch instruction copies the IS part of RO to R14 to the ISS of the PSR.

After the end of the designated branch instruction, the program counter sets the first instruction of the new instruction set and the PSR (ISS) indicates the new instruction set mode.

In order to determine whether the icache matches or the TAG (ISS) is equal to the PSR (ISS), the above-described step 330 of FIG. 3 may refer to FIGS. 5A and 5B showing the operation of the icache for further details. .

5A illustrates the operation of a typical eye cache. This is a case of comparing the operation without the PSR (ISS) combination. The address 510 is stored in the program counter PC and applied to the icache. The m bits of the address select one entry of the tag portion and the N bits of the address 510 are compared with the tag bits of the tag portion of the eye cache. The V bit in the tag portion indicates whether the selection entry is valid or invalid. The ISS bit in the tag portion indicates the command type of the entry. Step 330 shown in FIG. 3 is completed by whether the V bit represents "valid" or whether the ISS bit of the TAG is the same as the ISS bit of the PSR and the N bit of the address is the same as the tag bit in the tag portion of the icache. do.

5B illustrates the operation of the eye cache according to an embodiment of the present invention in which the PSR (ISS) is introduced as a comparison operation. Address 510 is stored in the PC and applied to the icache. The N bits of the address 510 are compared with the tag bits stored in the tag portion of the eye cache 520 indicated by the m bits of the address 510. The V bit of the tag portion indicates whether the entry is valid or invalid. PSR (ISS) is introduced to compare with TAG (ISS). As shown in FIG. 3, the "Ichahe Hit" step 330 is determined by the following "AND" algorithm.

1. Is the N bit the same as the tag bit in the icache tag section?

2. Does the V bit represent "Valid"?

3. Is PSR (ISS) the same as TAG (ISS)?

The TAG (ISS) is the ISS bit of the TAG and the PSR (ISS) represents the ISS bit of the PSR. If the instructions are mixed together with different number of bits, for example, if 16-bit instructions and 32-bit instructions are mixed with each other, one or more bits of the address 510 may be used to designate the first or second half of the instruction. Is introduced. For example, as shown in Fig. 5B, a third bit is applied to the comparison operation, and represents an algorithm as to whether or not it is equal to the TAG of the indicated register when N bits are changed to N + 1 bits.

As with the "A" instruction described above, the predecoder 27 as shown in FIG. 2 has subdecoders 272 for converting one, one or two or more instruction sets for the first instruction.

See Figures 6A and 6B for more details. 6A shows a typical structure for processing other instructions. For example, there are four instructions per line in the data bus BIU 610. One of the four instructions selected by the switch 620 is applied to the memory 630 of the icache. One of the instructions is sent to the decoder to execute the instruction. The transmitted command is first mapped and decoded. After mapping and decoding, the instructions are applied to the processor core for execution. As shown in FIG. 6B, in the exemplary embodiment of the present invention, the command selected after the switch 640 is applied to the predecoder 650 and the switch 660 simultaneously. If the instruction is a B instruction instead of the first instruction, the predecoder 65 converts the B instruction into a first instruction, that is, an A instruction. The predecoded command is applied to the switch 660. An instruction is then sent to the memory 670 of the icache by selection according to the ISS bit in the PSR.

Reference is made to FIGS. 7A and 7B which show the case of instructions A and B mixed from the data bus. Referring first to FIG. 7A, iCache requests a BIU with PC = 0 and the BIU responds with line 710 containing four instructions. The type command is "ABBA". The TAG (ISS) always remembers an encountered instruction and iCache handles the entire line by the first faced instruction type. For example, as shown in the embodiment, the TAG (ISS) is "A" because the instruction type is A at PC = 0. The data portion of the icache memory is filled with the "A" instruction type. The type command is "AAAA".

After n cycles, the BIU line is probably written to iCache and changed. The CPU commands PC = 4 and PSR = (ISS) = B. However, this represents a miss in tag TAG (ISS) = A. Again the iCache requires a BIU with PC = 4 and the BIU responds to the line with the command type order "ABBA".

Next, referring to FIG. 7B, when PC = 8, after the pre-decoding of the command type order "ABBA", TAG (ISS) = B and the data portion of the icache memory are filled with "B" and the command type order is "BBBB". . At this time, the TAG (ISS) for storing the line 710 of the data bus BIU is B type. TAG (ISS) is the same as PSR (ISS) and represents an icache hit. If there is no problem with the order of the instruction type, iCache can always determine the correct instruction and predecode. In other words, there are no cases where there is a mix of different command types on one line.

The data processing apparatus of the present invention has a number of advantages over conventional data processing apparatus. One advantage is that the data processing apparatus of the present invention can execute instructions in multiple instruction sets. It is not limited to one or two instruction sets. The present invention allows extreme usefulness when a programmer writes programs. If power commands are required, a stronger command set is used. If memory is useful, the instruction sets stored in memory are used.

Another advantage is reduced power consumption. In a typical apparatus all instruction sets have a separate instruction decoder and logic control circuitry. This is expensive and consumes a lot of power because the indicated command decoders are needed to toggle the command fetch at each time. However, in the present invention, the predecoders are only toggled when fetching the first instruction. On average, the icache hit rate is ˜95%, and the predecoder of the present invention is toggled five times in just 100 instruction fetches.

Thus, the CPU architecture does not require changes to implement other instruction sets. The only change required is the bus interface and the predecoder. In addition, the present invention can further reduce the cost.

It will be apparent that the present invention can be modified in various ways within the scope of the technical spirit of the present invention without departing from the technical spirit of the present invention. In this respect, the present invention includes all modulation changes which are foreseen within the scope of the following claims and their equivalents.

Claims (9)

A data processing apparatus for executing a multi-instruction set, Memory for storing multiple instructions in multiple instruction sets, A processor core for executing the first instruction of the instruction, A program counter register (PC) for addressing the next instruction stored in memory, A plurality of data registers for storing the data of the instruction, A processor status register that stores a state of the processor core and includes an instruction set selector (ISS) for indicating a current instruction set of the instruction set, A predecoder for moving and outputting at least one of the instruction sets to the primary instruction, Icache to store the first instruction, A decoder that decodes the primary instructions, wherein the processor core is used to execute the primary instructions decoded by the decoder, A program counter controller responsive to the instruction set selector to modify the value of the program counter to match the length of the first and other instructions, And a bus interfaced between the predecoder and the memory. 2. The data register of claim 1, wherein each of the data registers has two portions of bits, wherein at least one bit appears as an instruction set select bit (IS) and the remaining bits stored in the data register appear as a target address (TA). Data processing unit. The data processing apparatus of claim 2, wherein the target address is a start address of an instruction set. 3. The data processing apparatus of claim 2, wherein the instruction set selector (ISS) is set by a branch instruction designated according to the instruction set select bit (IS) of the data register. The data processing apparatus of claim 1, wherein the predecoder comprises at least one sub decoder for moving at least one of the instruction set to the primary instruction. The data processing apparatus of claim 1, wherein the sub decoder switching is controlled by an instruction set selector (ISS), and the output of the predecoder is a primary instruction. 2. The data of claim 1, wherein the bit width of the primary instruction is not equal to the bit width of the other instructions, and icache adds an instruction set selection bit to move the PC value to indicate a relative primary instruction. Processing unit. 2. The apparatus of claim 1, wherein the instruction set selector comprises at least one bit. 9. The data processing apparatus of claim 8, wherein the instruction set selector is set by a branch instruction designated according to one or more instruction set select bits of a data register.