JP3112861B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor system for executing a program consisting of a plurality of instructions in a pipeline, and the order of execution of instructions contained in the program executed by the microprocessor is stored in the data of the instruction A microprocessor that executes in an order other than the order in which the programs are described by referring to the dependencies,
In addition, the present invention relates to a method and a configuration for determining the execution order of a processor that performs a superscalar execution of a plurality of instructions whose data dependencies have been solved at the same time or near time.

[0002]

2. Description of the Related Art In a general-purpose microprocessor that performs parallel execution while extracting parallelism at an instruction level, it is necessary to confirm whether input data required by an instruction has been prepared.
Regardless of the static order, an OutOfOrder execution form that dynamically determines and executes the execution order from the one whose dependency has been resolved is general. When an instruction executable at a certain time is equal to or more than the number of resources to be used, the method of selecting an instruction to be executed is generally “select from old instructions”.
The method is general and widely used.

For example, as shown in FIG. 2, there are instructions I1 to I10 in a program, and the static order of the instructions in the program is from I1, I2, I3, I4, I5 to oldest.
... Assume I10. It is also assumed that the data dependency exists in the direction indicated by the arrow in FIG. That is,
The instruction pointed by the arrow indicates that the instruction connected to the origin of the arrow is executable when the execution of the instruction ends. The instruction pointed to by a plurality of arrows indicates that the instruction can be executed only after all the instructions on the pointing side have been completed. It is also assumed that the instruction I9 in FIG. 2 takes 20 clocks to complete execution, and the other instructions take only one clock to execute. The microprocessor that executes this program is a microprocessor that can execute two instructions at the same time and can execute a two-way superscalar.

In this example, when the instruction I1 is executed, the instructions I2, I3 and the instruction I9 become executable when the execution of the instruction I1 is completed. According to the "select from old instructions" method, the instructions selected to be executed next are I2 and I3. When the execution of the instructions I2 and I3 is completed, the next executable instructions are the instructions I4, I5 and I9.
4. Execute I5. When the instructions I4 and I5 have been executed, the instructions I6, I7 and I9 become executable and the instruction I
6, I7 are executed. After the execution of the instructions I6 and I7, the instructions I8 and I9 become executable and executed.

In this case, the instruction I10 cannot start executing until the instructions I8 and I9 are completed.
Is an instruction that takes 20 clocks, so that I10 is also delayed by 20 clocks before its execution starts. In other words, the large latency of the instruction I9 appears in the execution time of the program, which greatly affects the performance. Specifically, in the above program, the execution time from I1 to I10 is 25 clocks, and the latency of 20 clocks of the instruction I9 accounts for a large proportion of the entire execution time.

That is, as described in the above example, when there are a plurality of instructions that can be executed at a certain point in time, the general method of selecting the execution order from the oldest one is the execution time of the instruction with a large latency. However, there are cases in which it cannot be hidden, causing a decrease in performance.

To solve this problem, Japanese Patent Application Laid-Open No. Hei 4-25233
No. 6, a method for optimizing the execution order of programs and optimizing the execution order by a processor that performs pipeline processing is proposed. This is to optimize the execution time by reducing the instruction waiting time that may occur depending on the execution order of instructions, so-called pipeline break, by inserting an appropriate instruction and changing the execution order. It is.

This apparatus statically analyzes the dependence of an instruction sequence, performs weighting on instruction processing, and reconstructs an instruction sequence. However, since this apparatus performs static analysis, it does not operate during execution. Latency (such as when a memory access instruction causes a cache miss and performs a fill process, or an operation instruction whose processing time varies depending on the value) cannot be handled. In addition, for processors that have software compatibility but are not hardware compatible, the processing weighting for each processor changes, so it is necessary to optimize programs for each processor. It is a target.

[0009]

The first problem is that 0u
In a microprocessor that executes t0f0rder execution, if there is a plurality of microprocessors at the same time during execution of a program, the data dependency of which has been eliminated (that is, determined to be executable) at the same time. The "execute" selection method can result in significant overhead, causing performance degradation. The reason is that when a certain program is completed, the data dependency inherent in the program is fixed, and a general microprocessor that can execute 0ut0f0rder while extracting the parallelism of the program based on the data dependency is used. If they are executed, there will be a plurality of execution orders, and the execution time of the program will change depending on the execution method.

The second problem is that, in order to solve the first problem by completely specifying the order of instruction execution, it is assumed that dependencies included in a program can be statically analyzed at compile time or the like. However, it is inefficient and difficult to completely optimize the execution order of a program. The reason is that the same software operates, but in a plurality of microprocessors having different architectures, their instruction execution times are generally different. Therefore, one program is statically assigned so as to correspond to each microprocessor. It needs to be analyzed and optimized, which is inefficient. Even if the number of target microprocessors is one, there are some instructions whose execution time dynamically changes at the time of execution (eg, cache fill processing due to a cache miss of a memory access instruction). This is because it is extremely difficult to perform static analysis.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art. In order to conceal the latency at the time of executing an instruction with a latency, a history at the time of executing the instruction is stored, and the instruction is stored based on the history. It is an object of the present invention to provide a microprocessor having a mechanism for dynamically determining an execution order at the time of execution. Since this mechanism dynamically determines the execution order at the time of execution, there is no need for prior static analysis or optimization of the program.

[0012]

A microprocessor according to the present invention comprises an instruction fetch mechanism (F0 in FIG. 1) for fetching instructions, an instruction decode mechanism (D0 in FIG. 1) for decoding fetched instructions, and And a post-execution processing unit (W0 in FIG. 1) for performing post-execution post-processing. The performance of detecting the above-mentioned performance degradation state in or near the microprocessor is provided. A monitoring mechanism (P0 in FIG. 1) and a history management memory (H in FIG. 1) which is a storage device for storing information on instructions with a latency that may cause performance degradation.
0), and further includes an instruction execution control unit (A0 in FIG. 1) having a selection means for determining the order of execution of instructions from the history of instructions stored in the storage device.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, F0 is an instruction fetch mechanism, and D0 is an instruction decode mechanism, which simultaneously decodes a plurality of instructions predicted to be executed. E0 is an instruction execution mechanism that executes a plurality of instructions at the same time. W
0 is a post-execution processing unit. A0 is an instruction execution control unit that selects an instruction to be executed next by the instruction execution unit E0 among instructions whose dependencies have been eliminated. Performance monitoring mechanism P0
Monitors microprocessor utilization. The history management memory H0 stores information related to instructions having a history in which the operation rate of the processor has been lowered with a long latency. Instruction fetch mechanism F0, instruction decode mechanism D0, post-execution processing unit W
0, the instruction execution control unit A0, the performance monitoring mechanism P0, and the history management memory H0 all perform pipeline processing.

An example when the program shown in FIG. 2 is executed with the configuration shown in FIG. First, the microprocessor MP
Instruction fetch mechanism F0 fetches a plurality of instructions I1 to be executed from the memory M0. The memory M0 may be provided in the microprocessor MP. The instruction decode mechanism D0 decodes the fetched instruction into a signal executable by the microprocessor. If a low operation rate state clock has been registered for the instruction to be decoded in the past, the instruction is read from the history management memory H0.

The instruction execution control unit A0 refers to the contents of the history management memory H0 referenced at the time of decoding, and checks whether or not the decoded instruction I1 has previously reduced the operating rate of the processor due to the latency of the instruction I1 itself. . If there is such a history in the past, the instruction is executed with priority. In this example, since the instruction I1 has no such history and is not registered in the history management memory H0, the instruction I1 is selected by the usual “select from oldest” method.

Issued (selected) by the instruction execution control unit A0
The executed instruction is executed in the instruction execution unit E0.
For the instruction execution unit E0, the performance monitoring unit P0 holds the address of the instruction I1 being executed, and when the instruction exists in the instruction execution unit E0, counts the number of instructions existing in the instruction execution unit E0 ( When the instruction execution unit E0 is executing only the instruction Ix, the number of instructions is 1), and the number of clocks in a state where the number of instructions is equal to or less than the preset instruction number T0 is counted. Here, the instruction at the address Ix is the instruction execution unit E
The number of low operation rate state clocks when they are at 0 is represented by C (I
x). The operation rate of the instruction execution unit E0 is based on the number of instructions in the instruction execution unit E0 at that time.
Let it be 1. If the count value is larger than the predetermined number of clocks T1, the instruction address and the number of clocks in the low operation rate state are stored in the history management memory H0. In this example, T1 = 5. The number of clocks in the low operation rate state C (I1) = 1 in the instruction I1 is smaller than T1 and is not registered in the history management memory H0.

The history management memory H0 is configured as an associative memory which refers to the instruction address Ix as a key, and stores the number C (Ix) of the low operation rate state clocks. In FIG. 2, since the execution of the instructions I1 to I7 is completed in one clock, the performance monitoring mechanism P0 does not detect the low operation rate state, and therefore, the history management memory H0
No information from the instructions I1 to I7 is written.

However, when the instructions I8 and I9 are executed,
In the first one clock, the operation rates of the instruction execution unit E0 are 2 because the instructions I8 and I9 are executed together, but in the next clock, the execution of the instruction I8 has been completed, so that only the instruction I9 remains. Instruction execution mechanism E over 19 clocks
The process remains at 0. In this case, since the number of operating instructions is 1, the performance monitoring mechanism P0 counts up C (I9) for the instruction I9 to 19. Since C (I9) is larger than T1, the address of the instruction I9 and C (I9) = 19 are written in the history management memory H0.

In the above process, the execution time of the instructions I1 to I10 takes 25 clocks. Thereafter, the execution of the program proceeds, and when the instruction I1 is executed again, the executable instructions are I2, I3, and I9. Instruction decode mechanism D0
From the control to the instruction execution control unit A0, the instruction execution control unit A0 refers to the history management memory H0,
9 detects that it has caused a 19 clock low availability condition. When this is detected, the instruction execution control unit A0 preferentially selects the instruction I9. The other is the older instruction I2
Select Then, the instruction I
2, I9 starts execution.

While instruction I9 is being executed, I2, I
Instructions are executed by the instruction execution unit E0 one by one in the order of 3, I4, I5, I6, I7, and I8. Instruction I9 is then 1
During three clocks, the state of the number of operating instructions 1 continues. The performance monitoring mechanism P0 counts up to C (I9) = 13. Although it is a value larger than T1, the C (I
9) Since the value is smaller than = 19, the value of the history management memory H0 is not changed. If C (I9) is larger than the previous value, register C (I9) and the address in the history management memory H0. When the execution of the instruction I9 is completed, the instruction I10 becomes executable for the first time, and is executed by the instruction execution mechanism E0.

In the second process, the instructions I1 to I1
The execution time up to 0 is 22 clocks, and the performance improvement of 3 clocks has been realized. As described above, according to the present embodiment, by referring to the histories of a plurality of executable instructions, it is possible to dynamically know at execution time whether or not the instructions may have a latency. Also,
By using this for selecting instruction issuance, the number of clocks in a state where the operation rate of the execution unit is reduced due to instruction latency can be reduced, and the processing efficiency of instructions can be improved.

Next, an embodiment of the microprocessor according to the present invention will be described with reference to FIG. Reference numerals 1 and 2 in FIG. 3 denote addresses of two instructions decoded from the instruction decode mechanism D0, respectively. H0 is a history management memory. This configuration has a CAM structure and the number of entries is 256.
Entry. However, in general, a set associative configuration or a direct map configuration is also conceivable. It is desirable that the number of entries be large. In the present embodiment, a memory having two read ports is configured so that a value can be referred to at the same time by the addresses of two instructions to be decoded at the same time. The content is 8-bit data indicating the number of low operation rate state clocks.

The data 10 and 11 read from the history management memory H0 by the addresses 1 and 2 are sent to the instruction synchronization mechanism 20. This is a synchronization mechanism for examining the dependencies of decoded instructions, and is the same as that mounted on a general microprocessor. The instruction determined to have the instruction dependency resolved by the instruction synchronization mechanism 20 is written to the memory 14. The memory 14 stores information on the instruction and the number of low operation rate clocks corresponding to the instruction. In this example, (8-bit low operation rate state clock number + information of issued instruction) × 6 entries are prepared.

The comparator 15 selects the first and second largest number of low operation rate state clocks among the six instructions stored in the memory 14. The two instructions are executed by the instruction execution unit E0. The performance monitoring mechanism P0 monitors the state of the instruction execution mechanism E0, and the number of low operation rate state clocks is larger than the above-described T1 and the memory 1 is decoded.
If the number of clocks is larger than the past value obtained from 4, the number of clocks is written to the memory 14.

Next, an embodiment relating to monitoring and registration of the performance monitoring mechanism (P0 in FIG. 1) will be described with reference to FIG. E0 in FIG. 4 is an instruction execution mechanism. In this embodiment, instruction execution units E01 and E02 are provided so that two instructions can be executed simultaneously. In this figure, parts other than the instruction execution mechanism E0 constitute a part of the performance monitoring mechanism (P0 in FIG. 1).

Instruction execution start signals 3 and 4 of two instructions given to the instruction execution unit, and instruction execution end signals 111 and 11 issued by the instruction execution units E01 and E02 at the end of instruction execution.
2 and the number of instructions 100 currently in the instruction execution unit, the counters A13 and A14 indicate that “the number of instructions in the instruction execution unit is T0 (1 in this embodiment) from the start to the end of each instruction. ) The following states are counted. The counted value is the “number of low operation rate state clocks” for each instruction.

When the counting is completed, the detectors A15, A15
For each instruction at 16, "the number of low operation rate state clocks that have not been registered in the history management memory (H0 in FIG.
(In this embodiment, 5) or more, or the number of low operation rate state clocks counted this time is larger than the value registered in the history management memory (H0 in FIG. 1) in the past. " When this state is detected for each instruction, an instruction to register the low operation rate state clock number in the history management memory (H0 in FIG. 1) is issued on the signal line 18 or 19. By referring to this, the performance monitoring mechanism (P0 in FIG. 1) registers in the history management memory (H0 in FIG. 1).

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. Even if there is, it is included in the present invention.

[0029]

The first effect is that optimal instruction execution scheduling can be performed in program execution.
Thereby, the program execution performance of the microprocessor is improved. The reason is that, once the occurrence of the overhead is detected, the scheduling is performed by a more suitable method for the second and subsequent times, so that the optimal instruction execution scheduling is performed. The second effect is that the first effect can be accelerated without static analysis of the program or prior optimization. This eliminates the need for redundant program conversion. This is because a history is dynamically registered at the time of execution and scheduling is performed while dynamically referring to the history.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an outline of the present invention.

FIG. 2 is an example of a program in which overhead increases depending on the order of instruction execution.

FIG. 3 is a configuration diagram showing an embodiment of the present invention.

FIG. 4 shows a part of an instruction execution mechanism and a performance monitoring mechanism according to an embodiment of the present invention.

[Explanation of symbols]

M0: Memory, MP: Microprocessor, F0
...... Instruction fetch mechanism, D0 ... Instruction decode mechanism,
A0: Instruction execution control unit, E0: Instruction execution mechanism, W
0: Post-execution processing unit, P0: Performance monitoring mechanism, H0:
… History management memory

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-95862 (JP, A) JP-A-9-120359 (JP, A) JP-A-4-252336 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 9/38 G06F 11/28-11/34

Claims (4)

(57) [Claims] 1. A microprocessor which fetches instructions in a program from a memory, decodes a plurality of instructions simultaneously, and can execute a plurality of instructions at the same time. A microprocessor capable of executing instructions in an order other than the static order of instructions, wherein the microprocessor includes a plurality of execution units.
A microprocessor having means for detecting a state in which an execution unit is not used and a specific instruction that caused the state . 2. The microprocessor according to claim 1, wherein said microprocessor includes a plurality of execution units.
A microprocessor having a performance monitoring mechanism for counting the number of clocks when a certain execution unit is not used . 3. A microprocessor according to claim 2, the registration means in the history management memory and the history management Memorihe is a storage device for registering in association with the clock number of instructions and the condition that caused the state A microprocessor comprising: means for extracting information registered from the storage device for an instruction specified by an address of an instruction in a program. 4. The microprocessor according to claim 3, wherein a group of instructions determined to be executable at any time during execution of the program is determined based on information corresponding to each instruction of the group of instructions extracted from the storage device. And a means for determining an order of executing instructions to be executed, and an instruction executing means for executing instructions according to the order of execution.