JP4892387B2 - Execution path detection apparatus, information processing apparatus, execution path detection method, program, and recording medium - Google Patents

Description

  The present invention relates to an execution path detection device, an information processing device, an execution path detection method, a program, and a recording medium.

  In order to realize high-speed processing and low power consumption of a processor that executes an application program, a method that focuses on the locality of the program has been proposed. This technique realizes high-speed processing and low power consumption by finding a critical instruction sequence for executing a program and optimizing the processing of the instruction sequence. As a technique for finding such a critical instruction sequence, there is a technique that uses an execution history of a branch instruction included in the instruction sequence.

  For example, in Patent Document 1, a loop structure instruction portion is detected by paying attention to the number of executions of a branch instruction that branches in a return direction opposite to the direction in which instructions in the instruction sequence are executed. A branch history recording apparatus that records a path route that is determined to have a large number of executions is disclosed. That is, in Patent Document 1, the path path is detected as an execution path of an instruction sequence having a high execution frequency under the assumption that locality exists in the loop structure portion of the program.

For example, Patent Document 2 includes a profiler table that stores a branch history of a branch instruction and a return branch destination table that stores a branch destination address in the return direction and the number of branches, and the branch destination of the return branch destination table. An estimation device that detects an execution path of an instruction sequence having a high execution frequency based on an address and a branch history stored in a profiler table is disclosed.
JP 2000-148482 A JP-A-2005-92532

  However, the branch history recording apparatus disclosed in Patent Document 1 needs to be processed by software. Therefore, there is a problem that the processing time for detecting an execution path of an instruction sequence having a high execution frequency becomes long, and it is difficult to specify an execution path of a desired instruction sequence during the processing of the processor.

  In addition, in the estimation apparatus disclosed in Patent Document 2, it is necessary to record an enormous branch history and branch destination address, and the storage area for storing the branch history and branch destination address becomes enormous. There is. In such an estimation device, if an attempt is made to reduce the storage area, the processing is interrupted due to the necessity of saving or the like, and the processing time for detecting the execution path of a desired instruction sequence becomes longer. Furthermore, since the processing by the SW profiler unit in Patent Document 2 is complicated, it is difficult to implement hardware, and it must be realized by software. Therefore, as in Patent Document 1, it is difficult to specify an execution path of a desired instruction sequence during the processing of the processor.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to execute an execution path detecting apparatus capable of detecting an execution path of an instruction sequence having a high execution frequency at high speed with a small memory capacity. An information processing apparatus, an execution path detection method, a program for causing a computer to implement the execution path detection method, and a recording medium for recording the program.

In order to solve the above problems, the present invention
An execution path detection device for detecting an execution path of an instruction sequence having a high execution frequency,
An execution history table in which the number of executions of the instruction at the head address of the instruction sequence block in which an instruction sequence including a branch instruction is one block is stored;
A branch history table storing a branch history of the branch instruction;
A branch history management unit that performs a process of collecting a branch history of the branch instruction,
On the condition that the number of executions exceeds a given threshold, the branch history management unit starts collecting the branch history, and path information for identifying the execution path is based on the branch history. This is related to the execution path detection device that outputs the output.

In the execution path detection device according to the present invention,
A counter that counts the number of times the instruction at the head address of the instruction sequence block is executed;
The execution history table is
The number of executions can be stored for each instruction at the head address.

  According to any one of the above-described inventions, focusing on the locality of the application program, since the repeated portion of the instruction sequence executed frequently is detected, the branch history of the repeated portion is collected. Therefore, it is not necessary to collect an enormous branch history when detecting an execution path of an instruction sequence having a high execution frequency in an application program. Therefore, according to the present invention, it is possible to detect an execution path of an instruction sequence having a high execution frequency at a high speed with a small memory capacity while suppressing a decrease in execution path detection accuracy.

In the execution path detection device according to the present invention,
At least a part of the storage area of the execution history table may overlap with the storage area of the branch history table.

In the execution path detection device according to the present invention,
At least a part of information to be registered in the branch history table may be written in a storage area of the execution history table.

  In any one of the above-described inventions, first, a repeated portion of an instruction sequence executed frequently is detected using the execution history table, and then the branch history of the repeated portion is collected in the branch history table. Therefore, the execution history table can be made unnecessary at the stage of collecting the branch history. Therefore, according to the present invention, the storage area for the execution history table and the branch history table is shared. The capacity can be reduced.

In the execution path detection device according to the present invention,
In the execution history table,
The number of executions of the instruction at the branch destination address in the return direction of the branch instruction may be stored.

  According to the present invention, since only the execution history of the branch instruction in the return direction is collected, it is possible to detect an execution portion that is frequently repeated with a small memory capacity.

In the execution path detection device according to the present invention,
The execution history table stores the start address and the number of executions,
The branch history management unit
The collection of the branch history can be started using a head address stored in association with the number of executions exceeding the threshold.

  According to the present invention, it is possible to collect the branch history of the frequently repeated portion detected using the execution history table, so that the branch history table can be configured with a small memory capacity.

In the execution path detection device according to the present invention,
The branch history table is
Memorize memorized information by set associative method,
Each set includes
The start address, the target address of a branch instruction included in the instruction sequence block, and the number of branches are stored.
Of the target addresses stored corresponding to the branch instruction, the target address of the set having the largest number of branches can be output.

In the execution path detection device according to the present invention,
The branch history management unit
The target address obtained by searching the branch history table using the branch destination address of the branch instruction as an index can be output as path information.

  According to any one of the above inventions, since the target address can be output based on the branch history table, it is possible to specify an execution path at high speed while omitting useless software processing.

In the execution path detection device according to the present invention,
When the branch destination of the branch instruction does not become the start address recorded in the execution history table, or when the predetermined number of executions of the branch instruction does not reach within a given sampling time,
The branch history management unit
The stored information in the branch history table can be invalidated.

  According to the present invention, after the branch history collection is started, the branch history table is invalidated by detecting that the execution is not frequently repeated, so that path information is collected wastefully. There is no need.

The present invention also provides
Any of the above execution path detection devices;
A central processing unit that executes and executes an application program,
The present invention relates to an information processing apparatus in which processing of the application program is optimized based on the path information from the path detection apparatus.

The present invention also provides
Any of the above execution path detection devices;
A central processing unit that executes application programs;
The present invention relates to an information processing apparatus including a path processing unit that optimizes processing of the application program based on the path information from the path detection apparatus.

  According to any one of the above-described inventions, an information processing apparatus can be provided in which an execution path detection apparatus that can detect an execution path of an instruction sequence that is frequently executed at high speed with a small memory capacity is applied and processing is optimized.

The present invention also provides
An execution path detection method for detecting an execution path of an instruction sequence having a high execution frequency,
Storing in the execution history table the number of executions of the instruction at the head address of the instruction sequence block having one instruction sequence including a branch instruction as a block;
Starting collecting branch history of the branch instruction on condition that the number of executions exceeds a given threshold, and storing the branch history in a branch history table;
And outputting path information for specifying the execution path based on the branch history.

In the execution path detection method according to the present invention,
At least a part of the storage area of the execution history table may overlap with the storage area of the branch history table.

In the execution path detection method according to the present invention,
The start address is
The branch destination address in the return direction of the branch instruction,
The execution history table stores the start address and the number of executions,
The collection of the branch history can be started using a head address stored in association with the number of executions exceeding the threshold.

In the execution path detection method according to the present invention,
The branch history table is
Memorize memorized information by set associative method,
Each set includes
The start address, the target address of a branch instruction included in the instruction sequence block, and the number of branches are stored.
Of the target addresses stored corresponding to the branch instruction, the target address of the set having the largest number of branches can be output.

In the execution path detection method according to the present invention,
The target address obtained by searching the branch history table using the branch destination address of the branch instruction as an index can be output as path information.

In the execution path detection method according to the present invention,
When the branch destination of the branch instruction does not become the start address recorded in the execution history table, or when the predetermined number of executions of the branch instruction does not reach within a given sampling time,
The stored information in the branch history table can be invalidated.

  According to any one of the above-described inventions, it is possible to provide an execution path detection method capable of detecting an execution path of an instruction sequence frequently executed at high speed with a small memory capacity.

The present invention also provides
The present invention relates to a program for causing a computer to execute any of the execution path detection methods described above.

  ADVANTAGE OF THE INVENTION According to this invention, the program which makes a computer implement | achieve the execution path detection method which can detect the execution path of an instruction sequence with high memory frequency at high speed with a small memory capacity can be provided.

The present invention also provides
The present invention relates to a computer-readable recording medium on which the program described above is recorded.

  ADVANTAGE OF THE INVENTION According to this invention, the recording medium which recorded the program which makes a computer implement | achieve the execution path detection method which can detect the execution path of an instruction sequence with high memory frequency at high speed can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Information Processing Device FIG. 1 is a block diagram showing a configuration example of an information processing device according to this embodiment.

  The information processing apparatus 100 includes a central processing unit (CPU) 10, an accelerator 20, and a profiler (execution path estimation apparatus, execution path detection apparatus) 30. The information processing apparatus 100 includes a bus 50, and data and addresses are exchanged with the CPU 10, the accelerator 20, and the profiler 30 via the bus 50. A memory 110 connected to the bus 50 via the memory bus 52 is provided outside the information processing apparatus 100, and the CPU 10, the accelerator 20, and the profiler 30 are connected to the memory 110 via the bus 50 and the memory bus 52. Can be accessed.

  The CPU 10 reads an application program stored in the internal memory of the CPU 10 or the memory 110, and executes an instruction corresponding to the program.

  The accelerator 20 performs processing to be executed by the CPU 10 in place of the CPU 10. The processing time of the accelerator 20 is shorter than the processing time of the CPU 10. The function of the accelerator 20 is realized by hardware or software. When the function of the accelerator 20 is realized by software, the accelerator 20 has a CPU and a memory, and reads an accelerator program stored in the memory or the memory 110 in FIG. 1 and executes processing corresponding to the program. The function of the accelerator 20 is realized by the CPU.

  Such an accelerator 20, for example, obtains the processing result of the program in a state where the instruction sequence of the program to be processed by the CPU 10 is optimized so that the processing time is shorter or the power consumption is lower. Generate. The accelerator 20 can obtain the same result as the processing result of the CPU 10 when the program is executed in a shorter time by executing the instruction sequence from which the unnecessary instruction sequence is deleted among the programs to be processed by the CPU 10, for example. It is like that. Further, for example, the accelerator 20 can obtain the same result as the processing result of the CPU 10 when the program is executed by processing the instruction sequence of the program to be processed by the CPU 10 in parallel in a shorter time. .

  The profiler (execution path detection device in a broad sense) 30 detects (estimates) a path of a loop structure (execution path, instruction path, hot path) that is frequently executed during execution of a program with high accuracy and identifies the detected path Hot path information (pass information in a broad sense), which is information for performing the process, is output. The profiler 30 detects an instruction sequence that is repeatedly executed from among the instruction sequences that constitute a program executed by the CPU 10, and performs a process of specifying a path that is frequently executed based on a branch history of the instruction sequence that is repeatedly executed.

  Further, a hot path processing unit 120 is provided outside the information processing apparatus 100. The hot path processing unit 120 identifies a loop structure path with high execution frequency based on the hot path information from the profiler 30 and optimizes the processing of this path to shorten the processing time of the information processing apparatus 100 or to process information. The power consumption during processing of the apparatus 100 is reduced.

  For example, the hot path processing unit 120 optimizes the instruction sequence so that the path of the instruction sequence identified based on the hot path information from the profiler 30 is processed in parallel, or optimizes the instruction sequence by deleting unnecessary instructions. To do. At this time, the hot path processing unit 120 stores the instruction sequence after the optimization processing in the accelerator 20 or a memory accessed by the accelerator 20.

  Alternatively, for example, the hot path processing unit 120 changes the hardware configuration of the accelerator 20 so as to shorten the processing time of the path of the instruction sequence specified based on the hot path information from the profiler 30, or processes the path. Thus, a process of changing the hardware configuration of the accelerator 20 so as to reduce the power consumption of the information processing apparatus 100 is performed. In this case, the accelerator 20 is a dynamically reconfigurable circuit, and the hot path processing unit 120 supplies hardware configuration information necessary for dynamic reconfiguration to the accelerator 20.

  Next, an outline of processing of the information processing apparatus 100 in FIG. 1 will be described.

  In this embodiment, an instruction sequence execution path is considered in units of instruction sequence blocks called basic blocks.

  FIG. 2 is an explanatory diagram of basic blocks in the present embodiment.

  Considering the execution path of the instruction sequence constituting the application program, the instructions constituting the application program can be distinguished into a branch instruction that changes the flow of program execution and an instruction other than the branch instruction. Since the instructions constituting the program are executed in order from the instruction with the smallest address value to the instruction with the larger address value, the instruction sequence block can be divided for each branch instruction that changes the flow of execution. This block is a basic block. The basic block is, for example, a block of an instruction sequence that starts from the instruction next to the last branch instruction of the immediately preceding basic block and ends with the first branch instruction when the instruction is executed in the direction in which the address value is larger.

  In FIG. 2, basic blocks BB1, BB2,..., BBK (K is a positive integer of 3 or more) are shown. The basic block BB1 starts with the instruction “inst1” at the head address BSA1 of this block, sequentially executes instructions in the instruction execution direction, and ends with the branch instruction “bne” at the address BIA1. If the branch instruction “bne” is a conditional branch instruction, the branch destination address when the condition is “true” is BSA3, and the branch destination address when the condition is “false” is the address next to the address BIA1. BSA2.

  The basic block BB2 starts with the instruction “inst2” at the head address BSA2 of this block, sequentially executes instructions in the instruction execution direction, and ends with the branch instruction “br” at the address BIA2. Since the address BSA2 is a branch destination address of the branch instruction of the address BIA1, the address BSA2 is the branch target address BTA1.

  The basic block BB3 starts with the instruction “inst3” at the head address BSA3 of this block, sequentially executes instructions in the instruction execution direction, and similarly ends with a branch instruction (not shown) at the address BIA3. The address BSA3 is a branch target address BTA2 of the address BSA3 because it is the branch destination address of the branch instruction of the address BIA1.

  Therefore, the instruction execution path can be expressed as a path of the basic blocks BB1 and BB2, or can be expressed as a path of the basic blocks BB1 and BB3.

  FIG. 3 shows an outline flow of an example of processing of the information processing apparatus 100 of FIG.

  First, the profiler 30 of the information processing apparatus 100 collects the execution history of the CPU 10 that executes the application program, and detects an execution instruction portion that is repeatedly executed at a high frequency from the instruction sequence constituting the application program (step S10). . At this time, the instruction sequence constituting the application program can be divided into basic blocks each including one branch instruction, and the execution path of the program can be specified by the flow between the basic blocks. As a result, as shown in FIG. 4, for example, a path returning from the basic block F to the basic block A is detected as an execution instruction portion that is repeatedly executed with high frequency. In FIG. 4, basic blocks A to F are shown, and it is assumed that program execution flows from the basic block A to any one of the basic blocks B to G.

  As illustrated in FIG. 3, the information processing apparatus 100 then starts collecting branch histories of execution instruction parts with high execution frequency detected in step S <b> 10. Then, the information processing apparatus 100 outputs hot path information that identifies a path based on the collected branch history information (step S11).

  The hot path processor 120 receives the hot path information from the profiler 30, optimizes the hot path process as described above (step S12), and ends the series of processes (end).

  FIG. 5 is an explanatory diagram of the hot path in FIG.

  5, the same basic blocks A to F as in FIG. 4 are shown. Each basic block includes an instruction FI of a basic block start address (BSA) of the basic block and a branch instruction BI of a branch instruction address (BIA) which is a final address of the basic block. The arrows connecting the basic blocks indicate that the processing flow has been changed by the branch instruction, and the numerical value attached to the arrow indicates the number of branches by the branch instruction.

  For example, there are two branch destinations of the branch instruction BI of the basic block A, and the branch instruction BI is a conditional branch instruction. An arrow from the basic block A to the basic block B indicates that the branch destination address when the condition of the branch instruction BI of the basic block A is “true” is the start address BSA of the basic block B, for example. This means that the change in the flow of processing from the basic block A to the basic block B has been 800 times as a history. An arrow from the basic block A to the basic block C indicates that the branch destination address when the condition of the branch instruction BI of the basic block A is “false” is the start address BSA of the basic block C, for example. This means that the change in the flow of processing from the basic block A to the basic block C has been 200 times as a history.

  On the other hand, for example, the branch instruction BI of the basic block D has one branch destination, indicating that the branch instruction BI is an unconditional branch instruction. This unconditional branch means that the history is 700 times.

  In order to collect the above history as history information, the start address BSA of the basic block, the branch destination address BTA (Branch Target Address) (target address in a broad sense), the address BIA of the branch instruction, and the number of branches using a table Managed. A route having a large number of branches between each basic block is identified as a hot path. In FIG. 5, the route of the basic blocks A, B, D, and F becomes a hot path, and the hot path is specified by outputting the start address string of each basic block of the basic blocks A, B, D, and F as hot path information. .

  As a result, the processing of the information processing apparatus 100 can be optimized intensively by applying a higher load by optimizing the instruction sequence of the basic blocks A, B, D, and F paths.

  Thus, in the present embodiment, focusing on the locality of the program, since the repeated portion of the instruction sequence executed at a high frequency is detected, the branch history of the repeated portion is collected. There is no need to collect a huge branch history when detecting a hot path of an application program. Therefore, according to the present embodiment, it is possible to detect an execution path of an instruction sequence having a high execution frequency at a high speed with a small memory capacity while suppressing a decrease in path detection accuracy.

2. Description of Profiler Next, the profiler 30 of FIG. 1 that performs such hot path detection will be described.

  FIG. 6 shows an outline of the configuration of the profiler 30 of FIG.

  The profiler 30 includes a control unit 200 and a management table unit 300. The control unit 200 includes an execution history management unit 210 and a branch history management unit 220. The management table unit 300 includes an execution history table 310 and a branch history table 320.

  Note that the function of the control unit 200 may be realized by software or may be realized by dedicated hardware. When the control unit 200 is realized by software, the CPU of the profiler 30 that has read a program that realizes an execution path detection method described later performs processing. Further, the management table unit 300 desirably shares the storage areas of the execution history table 310 and the branch history table 320 as described later.

  The execution history management unit 210 performs control for managing the execution history table 310.

  FIG. 7 shows an outline of the configuration of the execution history table 310 of FIG.

  The execution history table 310 has a plurality of entries. Each entry stores the execution count COUNT of the instruction at the head address BSA in association with (corresponding to) the head address BSA of the basic block. That is, the number of executions of the instruction at the basic block start address BSA is counted, and the execution history table 310 stores the execution number for each instruction at the start address of the basic block.

  Here, the head address BSA is a branch destination address in the return direction of the branch instruction. Therefore, in the execution history table 310, instead of the basic block start address BSA, the start address BSA may be registered as a branch destination address in the return direction. By collecting only the execution history of branch instructions in the return direction in this way, it becomes possible to detect an execution portion that is repeated frequently with a small memory capacity.

  Therefore, the execution history management unit 210 registers and adds to the execution history table 310 the start address BSA of the basic block (instruction sequence block) having the instruction sequence including the branch instruction as one block, and the execution count of the instruction at the start address BSA. Management control for searching, etc. is performed.

  In FIG. 6, the branch history management unit 220, on condition that the number of executions of the instruction at one of the top addresses of the basic block managed by the execution history table 310 has exceeded a given threshold value TH1. Collection of branch history of branch instructions is started, and thereafter processing for collecting branch history is performed.

  FIG. 8 shows an outline of the configuration of the branch history table 320 of FIG.

  The branch history table 320 has a plurality of entries. Each entry stores the address BIA of the branch instruction, the branch destination address BTA of the branch instruction, and the branch count COUNT of the branch instruction in association with the head address BSA of the basic block. Here, the head address BSA is a branch destination address in the return direction of the branch instruction or a branch destination address in the forward direction of the branch instruction.

  Therefore, the branch history management unit 220 performs management control for registering, adding, searching, and the like in the branch history table 320 with the basic block start address BSA, the branch instruction address, the branch destination address of the branch instruction, and the number of branches. Further, the branch history management unit 220 outputs hot path information (path information for specifying an execution path with a high execution frequency) based on the branch history registered in the branch history table 320.

  In FIG. 8, it is not necessary to store the branch instruction address BIA in the branch history table 320. However, by storing the branch instruction address BIA in the branch history table 320, offset information based on the branch instruction address BIA can be used as the branch destination address BTA information. Can be reduced.

  By the way, in the present embodiment, first, a repeated portion of an instruction sequence executed frequently is detected using the execution history table 310, and then the branch history of the repeated portion is collected in the branch history table 320. . Therefore, the execution history table 310 can be eliminated at the stage of collecting branch history. Therefore, in the present embodiment, the storage areas of the execution history table 310 and the branch history table 320 are shared, and the storage capacity provided in the management table unit 300 can be reduced.

  FIG. 9A and FIG. 9B are explanatory diagrams of the management table unit 300 in this embodiment.

  FIG. 9A shows an outline of the configuration of the shared table included in the management table unit 300. The shared table has a plurality of entries. Each entry stores the address BIA of the branch instruction, the branch destination address BTA of the branch instruction, and the branch count COUNT of the branch instruction in association with the head address BSA of the basic block. That is, the shared table has the same configuration as the branch history table 320 shown in FIG.

  In the present embodiment, the function of the execution history table 310 shown in FIG. 7 is realized using the shared table shown in FIG.

  That is, as shown in FIG. 9B, the branch instruction address BIA and branch destination address BTA fields in the management table of FIG. 9A are disabled (shaded area in FIG. 9B). . As a result, when the shared history table functions as the execution history table 310, only the basic block BSA and the count COUNT fields are enabled. Thereby, the functions of both the execution history table 310 and the branch history table 320 can be realized with the shared table shown in FIG.

  For this reason, in this embodiment, it can be said that at least a part of the storage area of the execution history table 310 overlaps with the storage area of the branch history table 320. Further, at least a part of information to be registered in the branch history table 320 can be written in the storage area of the execution history table 310.

  In the following, it is assumed that the management table unit 300 has the configuration of the shared table shown in FIG.

2.1 Profiler Processing Example FIG. 10 shows an outline flow of processing of the profiler 30 in the present embodiment.

  First, the branch history management unit 220 of the profiler 30 performs an initialization process for using the shared table as an execution history table as shown in FIG. 9B (step S20).

  Next, the execution history management unit 210 collects an execution history using a shared table that functions as an execution history table (step S21). Whether or not there is a high-frequency repetition by determining whether or not the number of executions of the instruction at the head address of the basic block stored in the shared table functioning as the execution history table exceeds a given threshold value TH1 Is determined (step S22).

  When it is determined in step S22 that there is no high frequency repetition (step S22: N), the execution history management unit 210 returns to step S21 and continues collecting the execution history.

  When it is determined in step S22 that there is a high-frequency repetition (step S22: Y), the execution history management unit 210 notifies the branch history management unit 220 to that effect. The execution history management unit 210 or the branch history management unit 220 performs an initialization process for using the shared table as a branch history table as shown in FIG. 9A (step S23).

  Thereafter, the branch history management unit 220 starts collecting branch histories using the head address stored in association with the number of executions exceeding the threshold value TH1. The branch history management unit 220 collects branch history using a shared table functioning as a branch history table, and passes a branch destination address with a large number of branches based on branch history information every time a branch instruction is input. It outputs as information (step S24). The branch history management unit 220 registers, adds, and replaces branch instructions and branch destination addresses using a known branch history collection method, but also registers the number of branches.

  Next, every time a branch instruction is input, the branch history management unit 220 causes a miss in the branch history table, and the branch destination address of the branch instruction is the start address of the basic block once recorded in the execution history table. Is detected or not, it is determined whether or not iterative processing is performed (step S25). When it is determined that there is no repetitive processing (when the branch destination of the branch instruction is not the start address recorded in the execution history table) (step S25: Y), the branch history management unit 220 stores the branch history in the branch history table. Discard (invalidate, initialize) (step S26), and return to step S20 (return).

  The branch history management unit 220 holds the number of executions of branch instructions. In step S25, when it is determined that there is an iterative process (step S25: N), the branch history management unit 220 determines whether the execution count of the branch instruction is equal to or greater than a given threshold value THX within a given sampling period. It is determined whether or not (step S27). When it is determined that the number of executions of the branch instruction within the sampling period is equal to or greater than the threshold value THX (step S27: Y), the branch history management unit 220 returns to step S24 and continues collecting branch history and outputting hot path information. To do. On the other hand, when it is determined that the execution count of the branch instruction is not equal to or greater than the threshold value THX within the sampling period (step S27: N), the branch history management unit 220 discards (invalidates) the branch history in the branch history table ( Step S26) and return to step S20 (return). As described above, by detecting whether or not the repetition is greater than or equal to the threshold value THX in step S27, it is not always necessary to detect the hot path for the frequently repeated portion detected in step S22, and the hot path information detected by the profiler 30 is detected. Can improve the accuracy.

  As described above, when the branch destination of the branch instruction does not become the start address recorded in the execution history table, or when the predetermined number of executions of the branch instruction does not reach the given sampling time, the branch history management The unit 220 can discard the branch history.

  The above processing may be realized by a program for causing a computer to function. In this case, a program for realizing the above processing is stored in the memory 110 or the profiler 30 (not shown) in FIG. 1, and the CPU (not shown) of the profiler 30 stores the program of the memory 110 or the profiler 30 (not shown). The above processing can be realized by reading. Further, in FIG. 1, for example, the program may be provided by a computer-readable recording medium instead of the memory 110 or the memory (not shown) of the profiler 30. This recording medium is a storage medium that can be used by a computer, and stores information such as programs and data. Its function is an optical disk (CD, DVD), magneto-optical disk (MO), magnetic disk, It can be realized by hardware such as a hard disk, a magnetic tape, or a memory (ROM). A CPU (not shown) of the profiler 30 performs various processes of the present invention (this embodiment) based on information stored in the storage medium. That is, information (program or data) for executing (implementing) the means of the present invention (this embodiment) is stored in this storage medium.

  FIG. 11 shows a flowchart of a processing example of the execution history management unit 210.

  First, the execution history management unit 210 monitors the execution of a branch instruction by the CPU 10, for example, and waits for the input of the branch destination address of the branch instruction as the basic block start address BSA (step S40: N). When the start address BSA of the basic block is input (step S40: Y), the execution history management unit 210 searches the shared table functioning as the execution history table using the start address BSA as an index (step S41).

  Then, as a result of searching the shared table in step S41, when there is an already registered head address BSA (step S42: Y), the execution history management unit 210 is recorded in association with the head address BSA searched in step S41. The number of executions is incremented and updated (step S43). At this time, the execution history management unit 210 detects whether or not the number of executions updated in step S43 has exceeded a given threshold value TH1 (step S44). When it is detected that the number of executions exceeds the threshold value TH1 (step S44: Y), the execution history management unit 210 determines that a high-frequency repeated execution part exists, and the branch history using the head address BSA is determined. Branch history collection enable is set so as to start the collection (step S45), and a series of processing ends (end).

  On the other hand, as a result of searching the shared table in step S41, when there is no registered start address BSA (step S42: N), the execution history management unit 210 uses the input start address BSA as a shared execution history table. Processing for registration in the table is performed (step S46), and the process returns to step S40. In practice, the head address BSA is compared with the branch destination address BTA, and when the branch destination address is in the return direction, the branch destination address BTA is registered as a newly added head address BSA. At this time, in the shared table functioning as the execution history table, the storage information is replaced as necessary.

  When it is detected in step S44 that the number of executions does not exceed the threshold TH1 (step S44: N), the execution history management unit 210 returns to step S40 and waits for the start address BSA of the next basic block.

  As described above, the execution history management unit 210 collects execution histories, detects execution portions that are repeated frequently based on the collected execution histories, and can instruct to start collecting branch histories. ing.

  FIG. 12 shows a flowchart of a processing example of the branch history management unit 220.

  First, the branch history management unit 220 monitors whether the branch history collection enable is set (step S60: N). When it is detected that the branch history collection enable is set (step S60: Y), the branch history management unit 220 waits for input of the head address BSA of the entry exceeding the threshold value TH1 in step S44 of FIG. Step S61: N). This head address BSA is a branch destination address of the branch instruction. When the head address BSA of the basic block is input (step S61: Y), the branch history management unit 220 searches the shared table functioning as a branch history table using the head address BSA as an index (step S62).

  As a result of searching the shared table in step S62, when there is already registered head address BSA (step S63: Y), the branch history management unit 220 has a plurality of head addresses BSA registered (step S64). : Y), the branch destination address with the largest number of branches is output as hot path information (step S65), and the branch count stored in association with the branch destination address is incremented and updated (step S65). Return (return).

  In step S64, when only one head address BSA is registered (step S64: N), the branch history management unit 220 outputs the hit branch destination address as hot path information and associates it with the branch destination address. The stored branch count is incremented and updated (step S66), and the process returns to step S60 (return).

  On the other hand, as a result of searching the shared table in step S62, when there is no registered head address BSA (step S63: N), the branch history management unit 220 uses the input head address BSA as a branch history table. Processing for registration in the table is performed (step S67), and the process returns to step S60. At this time, in the shared table functioning as the branch history table, the stored information is replaced as necessary.

  As described above, the branch history management unit 220 collects branch histories and outputs a hot path based on the collected branch histories. This hot path is output as hot path information in which branch destination addresses obtained by searching the branch history table are accumulated.

2.2 Configuration Example of Profiler Next, configuration examples of main parts of the execution history table 310, the branch history table 320, the execution history management unit 210, and the branch history management unit 220 in the present embodiment will be described.

  In the present embodiment, the execution history table 310 and the branch history table 320 will be described as storing the stored information by the 2-way-set associative method. However, the present invention is not limited to the number of ways, the execution history table 310, and the branch history table. The configuration is not limited to 320. For example, the execution history table 310 and the branch history table 320 may store stored information using a full associative method. However, since the branch destination of the conditional branch instruction is two locations, the two-way configuration enables the branch destination address when the condition of the conditional branch instruction is “true” and the branch destination address when the condition is “false”. Can be stored efficiently, and it is not necessary to provide a useless storage area.

  FIG. 13, FIG. 14 (A), FIG. 14 (B), FIG. 15 (A), and FIG. 15 (B) show configuration examples of main parts of the execution history table 310 and the execution history management unit 210 in this embodiment. .

  The execution history table 310 stores the start address BSA of the basic block and the execution count COUNT of the instruction at the start address BSA in a 2-way set associative method. Both ways have the same configuration, and storage information of each way is subjected to replacement control by a known LRU (Least Recently Used) method.

  For example, the lower bits of the head address BSA are input to the decoders DEC1 and DEC2. Each decoder selects one entry in each way table based on the lower bits of the head address BSA. The head address of the entry selected in each way and the execution count COUNT are read out. The head address read in this way is held in the head address registers BSA1 and BSA2, and the execution count is held in the execution count registers CNT1 and CNT2.

  The comparator CMP1 compares the head address BSA with the value of the head address register BSA1, and activates the hit signal hita1 (for example, “1”) when they match. The comparator CMP2 compares the head address BSA with the value of the head address register BSA2, and activates the hit signal hita2 (for example, “1”) when they match.

  The value of the execution count register CNT1 is incremented by an incrementer INC1 (counter in a broad sense). The value of the execution count register CNT2 is incremented by an incrementer INC2 (counter in a broad sense).

  The selector SEL1 selects the value of the execution count register CNT1 or the output of the incrementer INC1 based on the selection control signal sel1, and outputs a selection output CNTs1. Then, the execution count COUNT of the entry selected by the decoder DEC1 is updated by the selection output CNTs1. The selector SEL2 selects the value of the execution count register CNT2 or the output of the incrementer INC2 based on the selection control signal sel2, and outputs the selection output CNTs2. Then, the execution count COUNT of the entry selected by the decoder DEC2 is updated by the selection output CNTs2.

  As illustrated in FIG. 14A, the execution history management unit 210 or the execution history table 310 includes a hit determination unit 212. The hit determination unit 212 receives the hit signals hita1 and hita2 and outputs selection control signals sel1 and sel2 and write enable we1 and we2.

  FIG. 14B shows an operation explanatory diagram of the hit determination unit 212 of FIG.

  When the hit signal hita1 is active, the hit determination unit 212 controls the selection control signal sel1 to be active and update the execution history table 310 with the output of the incrementer INC1. The hit determination unit 212 controls the selection control signal sel2 to be active and update the execution history table 310 with the output of the incrementer INC2 when the hit signal hita2 is active.

  Further, when the hit signals hita1 and hita2 are inactive, the hit determination unit 212 performs control so that none of the selectors SEL1 and SEL2 is output, performs LRU control using the LRU control bits LRU1 and LRU2, and starts address When the branch destination address BTA is in the return direction with reference to BSA, one of the write enables we1 and we2 is activated. When the write enable we1 is active, the head address BSA is written to the entry selected by the decoder DEC1, and “1” is written as the execution count COUNT. When the write enable we2 is active, the head address BSA is written to the entry selected by the decoder DEC2, and “1” is written as the execution count COUNT.

  As shown in FIG. 15A, the execution history management unit 210 or the execution history table 310 includes a branch history collection start control unit 214 and a threshold setting register 216 in which a threshold TH1 is set. The branch history collection start control unit 214 receives hit signals hita1 and hita2, selection outputs CNTs1 and CNTs2, and a threshold value TH1, and outputs a branch history collection enable.

  FIG. 15B shows an operation explanatory diagram of the branch history collection start control unit 214 in FIG.

  The branch history collection start control unit 214 compares the selected output CNTs1 with the threshold value TH1 when the hit signal hita1 is active, and sets the branch history enable to active (eg, “1”) when the selected output CNTs1 is equal to or greater than the threshold value TH. To do. The branch history collection start control unit 214 compares the selected output CNTs2 with the threshold TH1 when the hit signal hita2 is active, and sets the branch history enable to active (for example, “1”) when the selected output CNTs2 is equal to or greater than the threshold TH. Set. Further, the branch history collection start control unit 214 sets the branch history collection enable to inactive when the hit signals hita1 and hita2 are both inactive.

  FIGS. 16, 17A, and 17B show configuration examples of main parts of the branch history table 320 and the branch history management unit 220 in the present embodiment.

  The branch history table 320 stores the start address BSA of the basic block, the branch destination address BTA of the branch instruction of the basic block, and the branch count COUNT to the branch destination address in a two-way set associative method. In FIG. 16, it is assumed that the branch instruction address BIA is not recorded in the branch history table 320. Both ways have the same configuration, and the storage information of each way is controlled to be replaced by a known LRU method.

  For example, the lower bits of the head address BSA are input to the decoders DEC3 and DEC4. Each decoder selects one entry in each way table based on the lower bits of the head address BSA. The head address BSA, branch destination address BTA, and branch count COUNT of the entry selected in each way are read. The read start address is held in the start address registers BSA3 and BSA4, the branch destination address is held in the branch destination address registers BTA3 and BTA4, and the branch count is held in the branch count registers CNT3 and CNT4.

  The comparator CMP3 compares the head address BSA with the value of the head address register BSA3, and activates the hit signal hitb1 (for example, “1”) when they match. The comparator CMP4 compares the head address BSA with the value of the head address register BSA4, and activates the hit signal hitb2 (for example, “1”) when they match.

  The value of the branch count register CNT3 is incremented by an incrementer INC3 (counter in a broad sense). The value of the branch count register CNT4 is incremented by an incrementer INC4 (counter in a broad sense).

  The selector SEL3 selects and outputs the value of the branch destination address register BTA3 or the branch destination address register BTA4 based on the selection control signal sel3, is added as hot path information, and is also used as the head address of the next basic block. 320 is input.

  The selector SEL4 selects the value of the branch count register CNT3 or the output of the incrementer INC3 based on the selection control signal sel4, and outputs the selection output CNTs3. Then, the branch count COUNT of the entry selected by the decoder DEC3 is updated by the selection output CNTs3. The selector SEL5 selects the value of the branch count register CNT4 or the output of the incrementer INC4 based on the selection control signal sel5, and outputs the selection output CNTs4. Then, the branch count COUNT of the entry selected by the decoder DEC4 is updated by the selection output CNTs4.

  As illustrated in FIG. 17A, the branch history management unit 220 or the branch history table 320 includes a hit determination unit 222. The hit determination unit 222 receives hit signals hitb1 and hitb2, selection outputs CNTs3 and CNTs4, and outputs selection control signals sel3, sel4 and sel5, and write enable we3 and we4.

  FIG. 17B illustrates an operation explanatory diagram of the hit determination unit 222 in FIG.

  When the hit signal hitb1 is active, the hit determination unit 222 controls the selection control signal sel4 to be active and update the branch history table 320 with the output of the incrementer INC3. Further, when the hit signal hitb2 is active, the hit determination unit 222 controls the selection control signal sel5 to be active and update the branch history table 320 with the output of the incrementer INC4.

  Furthermore, the hit determination unit 222 selects the way having the larger branch count when the hit signals hitb1 and hitb2 are active. Therefore, when the selection output CNTs3 is equal to or higher than the selection output CNTs4, the hit determination unit 222 sets the selection control signal sel4 to active and sets the selection control signal sel5 to inactive. When the selection output CNTs3 is smaller than the selection output CNTs4, the hit determination unit 222 sets the selection control signal sel4 to inactive and sets the selection control signal sel5 to active. Further, the hit determination unit 222 outputs the selection control signal sel3 by the same control as the selection control signal sel4.

  Furthermore, when the hit signals hitb1 and hitb2 are inactive, the hit determination unit 222 performs control so that none of the selectors SEL3 and SEL4 is output, and performs LRU control using the LRU control bits LRU3 and LRU4. One of the write enables we3 and we4 for writing the input head address BSA is activated. When the write enable we3 is active, the head address BSA is written to the entry selected by the decoder DEC3, and “1” is written as the branch count COUNT. When the write enable we4 is active, the head address BSA is written to the entry selected by the decoder DEC4, and “1” is written as the branch count COUNT.

  As described above, the branch history table 320 stores the storage information by the set associative method. In each way (set), the start address of the basic block and the branch destination address (target address) of the branch instruction included in the basic block are stored. ), And the number of branches is stored. Then, the branch destination address of the branch instruction of the way (set) having the largest number of branches among the branch instructions stored corresponding to the branch instruction can be output.

3. Others The present invention is not limited to the above embodiment.

  FIG. 18 shows a block diagram of a modification of the information processing apparatus of FIG.

  18, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In the information processing apparatus 500 in this modification, the hot path processing unit 120 is provided in the information processing apparatus 500. Then, the hot path processing unit 120 performs optimization processing based on the hot path information from the profiler 30, and outputs the optimization processing result to the accelerator 20. Here, the optimization processing result is the instruction sequence in which unnecessary codes are deleted from the instruction sequence in the hot path, the instruction sequence changed to operate the instruction sequence in the hot path in parallel, or the hardware configuration of the accelerator 20. Hardware configuration information to be changed.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The block diagram of the example of composition of the information processor in this embodiment. Explanatory drawing of the basic block in this embodiment. The figure which shows the outline | summary flow of an example of a process of the information processing apparatus of FIG. Explanatory drawing of the execution command part repeatedly performed with high frequency in this embodiment. Explanatory drawing of the hot path of FIG. The figure which shows the outline | summary of a structure of the profiler of FIG. The figure which shows the outline | summary of a structure of the execution history table of FIG. The figure which shows the outline | summary of a structure of the branch log | history table of FIG. FIG. 9A and FIG. 9B are explanatory diagrams of the management table unit in the present embodiment. The figure which shows the flow of the outline | summary of the process of the profiler in this embodiment. The flowchart of the example of a process of an execution history management part. The flowchart of the example of a process of a branch history management part. The figure which shows the structural example of the principal part of the execution history table and execution history management part in this embodiment. FIG. 14A and FIG. 14B are diagrams showing a configuration example of main parts of an execution history table and an execution history management unit in the present embodiment. FIG. 15A and FIG. 15B are diagrams showing a configuration example of main parts of an execution history table and an execution history management unit in the present embodiment. The figure which shows the structural example of the principal part of the branch history table and branch history management part in this embodiment. The figure which shows the structural example of the principal part of the branch history table and branch history management part in this embodiment. The block diagram of the modification of the information processing apparatus of FIG.

Explanation of symbols

10 CPU
20 accelerator 30 profiler 50 bus 100, 500 information processing apparatus 110 memory 120 hot path processing unit 200 control unit 210 execution history management unit 212, 222 hit determination unit 214 execution history collection start control unit 216 threshold setting register 220 branch history management unit 300 management Table unit 310 Execution history table 320 Branch history table

Claims (19)

An execution path detection device for detecting an execution path of an instruction sequence having a high execution frequency,
An execution history table in which the number of executions of the instruction at the head address of the instruction sequence block in which an instruction sequence including a branch instruction is one block is stored;
A branch history table storing a branch history of the branch instruction;
A branch history management unit that performs a process of collecting a branch history of the branch instruction,
On the condition that the number of executions exceeds a given threshold, the branch history management unit starts collecting the branch history, and path information for identifying the execution path is based on the branch history. An execution path detection device characterized by: In claim 1,
A counter that counts the number of times the instruction at the head address of the instruction sequence block is executed;
The execution history table is
An execution path detection apparatus for storing the number of executions for each instruction at the head address. In claim 1 or 2,
An execution path detection apparatus characterized in that at least a part of a storage area of the execution history table overlaps with a storage area of the branch history table. In claim 1 or 2,
An execution path detection apparatus, wherein at least part of information to be registered in the branch history table is written in a storage area of the execution history table. In any one of Claims 1 thru | or 4,
In the execution history table,
An execution path detection device for storing the number of executions of an instruction at a branch destination address in the return direction of a branch instruction. In any one of Claims 1 thru | or 5,
The execution history table stores the start address and the number of executions,
The branch history management unit
The execution path detection apparatus, wherein the branch history collection is started using a head address stored in association with the number of executions exceeding the threshold. In any one of Claims 1 thru | or 6.
The branch history table is
Memorize memorized information by set associative method,
Each set includes
The start address, the target address of a branch instruction included in the instruction sequence block, and the number of branches are stored.
An execution path detecting apparatus for outputting a set of target addresses having the largest number of branches among the target addresses stored corresponding to the branch instruction. In any one of Claims 1 thru | or 7,
The branch history management unit
An execution path detecting apparatus, wherein a target address obtained by searching the branch history table using a branch destination address of the branch instruction as an index is output as path information. In any one of Claims 1 thru | or 8.
When the branch destination of the branch instruction does not become the start address recorded in the execution history table, or when the predetermined number of executions of the branch instruction does not reach within a given sampling time,
The branch history management unit
An execution path detection device that invalidates storage information of the branch history table. The execution path detection device according to any one of claims 1 to 9,
A central processing unit that executes and executes an application program,
An information processing apparatus, wherein processing of the application program is optimized based on the path information from the execution path detection apparatus. The execution path detection device according to any one of claims 1 to 9,
A central processing unit that executes application programs;
An information processing apparatus comprising: a path processing unit that optimizes processing of the application program based on the path information from the execution path detection apparatus. In an information processing apparatus having an execution history table, a branch history table, and a control unit, an execution path detection method for detecting an execution path of an instruction sequence having a high execution frequency,
A step wherein said control unit is, for registering the number of times of execution of the instruction of the start address of the instruction sequence blocks that 1 block instruction sequence including a branch instruction to the execution history table,
Wherein the control unit comprises the steps of the execution count begins collecting branch history of the branch instruction on condition that exceeds a given threshold, it registers the branch history in the branch history table,
The control unit includes a step of outputting path information for specifying the execution path based on the branch history. In claim 12,
An execution path detection method, wherein at least a part of a storage area of the execution history table overlaps with a storage area of the branch history table. In claim 12 or 13,
The start address is
The branch destination address in the return direction of the branch instruction,
The execution history table stores the start address and the number of executions,
The execution path detection method , wherein the control unit starts collecting the branch history by using a head address stored in association with the number of executions exceeding the threshold. In any of claims 12 to 14,
The branch history table is
Memorize memorized information by set associative method,
Each set includes
The start address, the target address of a branch instruction included in the instruction sequence block, and the number of branches are stored.
An execution path detection method, comprising: outputting a set of target addresses having the largest number of branches among the target addresses stored corresponding to the branch instruction. In any of claims 12 to 15,
An execution path detection method , wherein the control unit outputs a target address obtained by searching the branch history table using a branch destination address of the branch instruction as an index, as path information. In any of claims 12 to 16,
When the branch destination of the branch instruction does not become the start address recorded in the execution history table, or when the predetermined number of executions of the branch instruction does not reach within a given sampling time,
The execution path detection method , wherein the control unit invalidates the storage information of the branch history table.   A program for causing a computer to execute the execution path detection method according to any one of claims 12 to 17.   A computer-readable recording medium on which the program according to claim 18 is recorded.

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