JPH1124942A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start execution of an instruction without waiting for the storage of an instruction code in an instruction queue with a prefetch operation and to improve the response speed of restoration to a main routine from an interruption sub-routine. SOLUTION: A first instruction queue 1 to become operable at the time of a main routine processing and a second instruction queue 2 to become operable at the time of an interruption sub-routine processing are provided. An interruption controller 10 is operated by switching the first instruction queue 1 or the second instruction queue 2 according to whether the present processing is the main routine processing or the interruption sub-routine processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer, and more particularly, to a microcomputer having an interrupt processing function.

[0002]

2. Description of the Related Art As shown in FIG. 12, a conventional microcomputer of this kind includes a bus control unit 7 including a prefetch pointer 4, a program storage memory 8, an instruction queue 1, an instruction decoder 1, 9
And the control signal line 14, the address signal line 1
1, each unit is connected by data signal lines 12 and 13. The program storage memory 8 may be configured as an external memory instead of the internal memory of the microcomputer.
Is installed outside, and the overall configuration is the same as described above.

Next, the operation will be described with reference to the flowchart of FIG. In the processing in the main routine, when a vacancy occurs in the instruction queue 1 (step S30), the prefetch control of the bus control unit 7 is activated (step S31), and the bus control unit 7
The control signal is output through the control signal line 14 and the address is output through the address signal line 11 from the prefetch pointer 4. When these control signals and addresses are input to the program storage memory 8, data (instruction code) is output through the data signal line 12 (step S32), and the output instruction code is taken into the instruction queue 1. It is stored (step S33). The operation from step S30 to step S33 is called a prefetch operation, and when there is a free space in the instruction queue 1,
The prefetch pointer 4 is updated each time the prefetch operation is completed and the prefetch operation is completed once.

[0004] The instruction code stored in the instruction queue 1 in step S33 is transferred to the instruction decoder through the data signal line 13 as necessary (step S34), and after being decoded (step S35), the instruction is executed. (Step S36).

Next, the processing of an interrupt subroutine will be described. As shown in the flowchart of FIG.
When an interrupt occurs (step S40), the interrupt is accepted at a suitable timing according to the state of processing in the main routine, and a program counter (hereinafter, referred to as PC) and a program status word (hereinafter, referred to as PSW). Is saved (step S41), and the address of the interrupt branch destination is set in the PC (step S42). This PC value is stored in the prefetch pointer 4 provided in the bus control unit 7.
(Step S43), the instruction code stored in the instruction queue 1 at the time of the previous main routine processing is invalidated, and after the instruction queue 1 is emptied, as in the main routine processing, the instruction code shown in FIG. The processing from step S30 to step S36 is performed (step S44).
Thereafter, when the return instruction is executed (step S45),
The saved PC and PSW values are restored (step S46), and the process proceeds to the main routine (step S47). When the process shifts to the main routine, the process is restarted from step S30.

Also, when an interrupt with a higher priority level is accepted during the processing of an interrupt with a lower priority level (interruption nesting occurs), as in the case where an interrupt is accepted during the processing of the main routine, FIG. The processing shown in the flowchart of FIG. In addition, the technique described in Japanese Patent Application Laid-Open No. 4-367941 is provided with an instruction buffer for storing a predetermined number of instruction codes constituting the head of an interrupt subroutine in addition to the above-described configuration. A technique for improving the response speed at the time of interrupt branch is described.

[0007]

Since the conventional microcomputer is configured as described above, the instruction code stored in the instruction queue by the prefetch operation at the time of the main routine processing is interrupted when the interrupt is accepted. In the subroutine processing, the instruction is invalidated. Therefore, when returning from the interrupt subroutine to the main routine, the instruction cannot be executed unless the instruction code is re-prefetched into the instruction queue 1. For this reason,
At the time of returning from the interrupt subroutine processing to the main routine processing, there is a problem that the start of instruction execution is delayed.

[0008] Also, in the case of interrupt nesting, an interrupt subroutine when an instruction code stored in the instruction queue 1 by a prefetch operation at the time of interrupt processing with a low priority level receives an interrupt with a higher priority level. Since the processing is invalidated in the processing, when returning from the interrupt processing with the higher priority level to the interrupt processing with the lower priority level, the instruction cannot be executed unless the instruction code is re-prefetched into the instruction queue 1. For this reason, when returning from the nested interrupt subroutine process, there is a problem that the execution of the instruction is delayed.

Further, when an instruction buffer for storing an instruction code forming the head of an interrupt subroutine is not provided as in the technique described in Japanese Patent Application Laid-Open No. 4-367941, an interrupt when an interrupt is accepted is provided. When branching to processing, instruction execution cannot be performed unless the instruction code of the interrupt branch destination is prefetched.
There is a problem that the execution of the instruction of the interrupt subroutine is delayed. Further, in the technique described in Japanese Patent Application Laid-Open No. 4-367941, the response speed at the time of interrupt branch is improved, but an operation of transferring an instruction code to an instruction buffer in advance is required, and the processing efficiency of the microcomputer is reduced. There was a problem that.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem. In addition to improving the response speed of returning from an interrupt subroutine to a main routine, the response speed of returning from an interrupt nest can be improved. It is an object of the present invention to obtain a microcomputer capable of improving the response speed at the time of branching.

[0011]

To achieve the above object,
The microcomputer according to the first aspect of the present invention includes a first instruction queue that is operable during main routine processing and a second instruction queue that is operable during interrupt subroutine processing. Is the main routine processing or the interrupt subroutine processing,
The interrupt controller operates by switching either the first instruction queue or the second instruction queue.

In the microcomputer according to the second aspect of the present invention, a plurality of the second instruction queues are provided within the number of interrupt priority levels, and the second subroutine processing is performed according to the number of interrupt nest processings. Thus, the interrupt controller is operated by switching any one of the second instruction queues.

According to a third aspect of the present invention, the microcomputer causes the return instruction to come immediately before the interrupt branch destination address on the interrupt subroutine program, and the interrupt acceptance number detecting unit detects the return instruction until the first interrupt service. The instruction code in the second instruction queue is invalidated, and in the second and subsequent interrupt services, the instruction code stored in the second instruction queue and held at the interrupt destination is held.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a microcomputer according to the present invention. This microcomputer has a bus control unit including an instruction queue 1 as a first instruction queue, an instruction queue 2 as a second instruction queue, and prefetch pointers 4 and 5.
It comprises a unit 7, a program storage memory 8, an instruction decoder 9, an interrupt controller 10, and an inverter 16. The memory 8 for storing the program may be constituted by an external memory instead of the internal memory of the microcomputer. In that case, however, the memory 8 for storing the program is merely provided outside. The same is true.

Reference numeral 15 denotes a signal line which becomes "1" when an interrupt service is being performed and "0" otherwise. Since this signal is generally held as a flag in the interrupt controller 10, Take out from the interrupt controller 10. However, in some microcomputers, this signal is held in the PSW as a flag. In this case, the signal line 15 is extracted from the PSW. The signal line 17 which passes the signal line 15 to the inverter 16 becomes “0” when the interrupt service is being performed, and becomes “1” otherwise. The operation and stop of the instruction queues 1 and 2 and the prefetch pointers 4 and 5 are switched by these signal lines 15 and 17.

Next, the operation will be described with reference to the flowchart of FIG. At the time of main routine processing,
Since the interrupt service is not being performed, the signal line 15 is "0",
The signal line 17 becomes “1”, and the instruction queue 2 and the prefetch pointer 5 to which “0” is input from the signal line 15
Is stopped, and the instruction queue 1 and the prefetch pointer 4 to which "1" is input from the signal line 17 are in an operable state. Therefore, in the processing of the main routine, the instruction queue 2 and the prefetch pointer 5 are stopped, and the instruction queue 1 and the prefetch pointer 4 are only operated. The operation contents are the same as those of the flowchart of FIG. It is exactly the same. Therefore, the duplicate description will be omitted.

Next, the processing in the interrupt subroutine will be described with reference to the flowchart of FIG. Here, first, when an interrupt occurs (step S6).
0), this interrupt is received at a proper timing in accordance with the processing in the main routine, and when the interrupt service is being performed, the signal line 15 becomes "1" and the signal line 17 becomes "0". Therefore, the instruction queue 2 and the prefetch pointer 5 to which "1" is input from the signal line 15 are in an operable state, and the instruction queue 1 and the prefetch pointer 4 to which "0" is input from the signal line 17 are in a stopped state. The instruction code stored in the instruction queue 1 and the current value of the prefetch pointer 4 are held as they are (step S61). Next, the values of PC and PSW are saved (step S62), and the address of the interrupt branch destination is set in PC (step S63). This PC
Is set in the prefetch pointer 5 (step S64), and the instruction queue 2 is used to execute steps S50 to S5 in FIG.
6 are performed (step S65).

Thereafter, when a return instruction is executed (step S66), the PC and PSW values that have been saved are restored (step S67). When the interruption service is stopped, the signal line 15 becomes "0" and the signal line 17 becomes "1". Therefore, the instruction queue 2 and the prefetch pointer 5 to which "0" is input from the signal line 15 are stopped,
The instruction queue 1 and the prefetch pointer 4 to which "1" is input from the signal line 17 are in an operable state (step S68), and shift to the main routine processing (step S69). At this time, since the instruction code is prefetched during the previous main routine processing and the instruction code is stored in the instruction queue 1, there is no need to wait for the instruction code to be taken into the instruction queue 1 by the re-prefetch operation. Processing can be performed from step S54. In parallel with the processing from step S54, the prefetch operation from step S50 to step S53 is performed using the value held in the prefetch pointer 4.

Next, another embodiment of the present invention will be described. FIG. 4 is a sequence chart showing an example of interrupt processing. In the above embodiment, the response to the return from the interrupt subroutine to the main routine is speeded up at the part A shown in FIG. 4, but here, the part B is also used for the return from the interrupt nest. The response is also speeded up. FIG. 5 shows a microcomputer capable of returning a response from such a nest of interrupts. The microcomputer includes instruction queues 1, 2, 3 and a bus control unit 7 including prefetch pointers 4, 5, and 6.
It includes a program storage memory 8, an instruction decoder 9, an interrupt controller 10, and a decoder 19. The memory 8 for storing the program may be constituted by an external memory instead of the internal memory of the microcomputer. In this case, however, the memory 8 for storing the program is merely provided outside, and the overall configuration is the same as that of FIG. It is.

The signal line 18 is a signal line for notifying which priority level interrupt is currently being serviced. Generally, the signal of the signal line 18 is held in the interrupt controller 10 as a flag. From the interrupt controller 10. This signal line 18 is output by the decoder 19 when the interrupt service is not in progress.
1 ', the signal line 21 which becomes'1' only during the service of the first interrupt received during the main routine processing, and the second signal line 21 which has a higher priority level received during the first interrupt processing. ｀ 1 'only during service of interrupt
And the signal line 22 is decoded.

Next, the operation will be described. First, at the time of the main routine processing, since the interrupt service is not being performed, the signal line 20 is set to {1 ′}, the signal line 21 and the signal line 22 are set.
Becomes "0", the instruction queue 1 and the prefetch pointer 4 to which "1" is input from the signal line 20 become operable, and the instruction queue 2 and the prefetch pointer to which "0" is input from the signal line 21 5 and signal line 2
The instruction queue 3 and the prefetch pointer 6 to which "0" is input from 2 are stopped. Therefore, the operation similar to the operation already described with reference to FIG. 2 is performed using the instruction queue 1 and the prefetch pointer 4.

Next, when the first interrupt is accepted, the signal line 21 becomes "1" and the signal lines 20 and 22 become "0".
, The instruction queue 2 to which プ リ 1 ’is input from the signal line 21 and the prefetch pointer 5 are operable, and the instruction queue 1 to which ｀ 0’ is input from the signal line 20
From the prefetch pointer 4 and the signal line 22
The instruction queue 3 to which 0 'is input and the prefetch pointer 6 are stopped. Therefore, using the instruction queue 2 and the prefetch pointer 5, an operation similar to the operation already described with reference to FIG. 3 is performed.

In this case, in step S65, when a second interrupt having a higher priority level is generated while nesting of interrupts is permitted, the timing is checked in accordance with the state of the first interrupt processing. Second
Is received, the signal line 22 becomes "1", the signal lines 20 and 21 become "0", and the instruction queue 3 and the prefetch pointer 6 to which "1" is input from the signal line 22 are in an operable state. Becomes On the other hand, the signal line 20
The instruction queue 1 and the prefetch pointer 4 to which 0 'is input from, and the instruction queue 2 and the prefetch pointer 5 to which ｀ 0' are input from the signal line 21 are stopped. Therefore, the instruction queue 3 and the prefetch
Using the pointer 6, an operation similar to the operation described with reference to FIG. 3 is performed.

On the other hand, when the return instruction is executed in the second interrupt processing, the processing shifts to the first interrupt processing. At this time, the instruction queue 2 is prefetched in the previous first interrupt processing. Since the stored instruction code is stored, there is no need to wait for the instruction to be taken into the instruction queue 2 by the re-prefetch operation.
The processing can be performed from step S54 in. In parallel with the processing from step S54, the prefetch operation from step S50 to step S53 is performed using the value held in the prefetch pointer 5.

Further, when a return instruction is executed in the first interrupt processing, the processing shifts to the main routine. At this time, the instruction queue 1 stores the instruction code prefetched during the previous main routine processing. Therefore, there is no need to wait for the instruction to be taken into the instruction queue 1 by the re-prefetch operation, and the processing can be performed from step S54. Also, in parallel with the processing from step S54, the value held in the prefetch pointer 4 is used to execute the processing from step S50 to step S5.
Up to 3 prefetch operations are performed.

FIG. 6 shows a circuit example of the decoder 19.
FIG. 6 is a circuit example when the interrupt controller 10 supports two interrupt priority levels.
NOR gate A1, ExclusiveOR gate A
2, and AND gate A3 have signal line 3 as input.
01 and 302 are connected, and the output of each gate is
They are connected to a signal line 20, a signal line 21, and a signal line 22. Therefore, according to this, when the interrupt is not accepted, the signal lines 301 and 302 indicating the service information of the priority level 1 and the priority level 0 are respectively set to {}.
0 ', the output from the decoder 19 becomes ｀ 1' on the signal line 20 and ｀ 0 'on the signal lines 21 and 22.

When either the priority level 1 or the priority level 0 interrupt is accepted, the signal line 3
01 or 302 becomes “1”,
As for the output from the decoder 19, the signal line 21 becomes "1" and the signal lines 20, 22 become "0". When the priority level 0 interrupt is accepted during the priority level 1 interrupt processing (when an interrupt nest occurs), the signals 301 and 302 each become "1" and the decoder 19
Is output from the signal line 22 to “1” and the signal line 2
0 and 21 become '0'.

FIG. 7 shows a circuit example of the decoder 19 when the interrupt controller 10 supports three interrupt priority levels, and shows signal lines 401, 402, and 40.
3 is input to the output of the NOR gate B1.
Are connected, the output of the Exclusive OR gate B2 to which the signal lines 401 and 402 are input, and the signal line 4
ExclusiveOR gate B3 to which 03 is input
Is connected to a signal line 21 and a signal line 40
1, NOR gate B4 to which signal lines 401 and 403 are input, output of NOR gate B5 to which signal lines 401 and 403 are input, and NOR to which an output of NOR gate B6 to which signal lines 402 and 403 are input. The signal line 22 is connected to the gate B7.

In the decoder 19 shown in FIG. 7, when an interrupt is not accepted, signal lines 401, 402, and 403 indicating service information of priority level 2, priority level 1 and priority level 0 are respectively "0",
In the output from the decoder 19, the signal line 20 becomes "1", and the signal lines 21 and 22 become "0". When an interrupt of any one of priority level 2, priority level 1 and priority level 0 is accepted, any one of signal lines 401, 402, and 403 becomes ｀
1 ′, the output from the decoder 19 becomes “1” on the signal line 21 and “0” on the signal lines 20 and 22.

On the other hand, when an interrupt nest occurs and any two of the three priority levels are in service and any two of the signal lines 401, 402, and 403 become "1", or three priority levels Three of the levels are in service, and three of signal lines 401, 402, and 403
When both become "1", the output from the decoder 19 becomes "1" on the signal line 21 and "0" on the signal lines 20 and 22. Here, a configuration has been described in which high-speed return is possible only when the interrupt nest returns from a single state. Therefore, when there are three or more interrupt priority levels and the number of nests is two or more,
Does not speed up. In order to perform high-speed return from all interrupt nests, the instruction queues are set in the number of interrupt priority levels supported by the interrupt control 10 and the instruction queues corresponding to the interrupt priority levels currently processed by the decoder 19 are set. May be switched to operate.

Next, still another embodiment of the present invention will be described. In each of the above embodiments, the case where the response at the time of returning from the interrupt is speeded up is described. Here, the case where the response at the time of branching to the interrupt is also speeded up will be described. FIG. 8 shows a microcomputer for implementing this. As shown in FIG. 1, the microcomputer includes a bus control unit 7 including instruction queues 1 and 2, prefetch pointers 4 and 5, a program storage memory 8, an instruction decoder 9, an interrupt controller 10,
An inverter 16 and an interrupt reception number detection unit 23 are provided. Of these, the program storage memory 8 may be constituted by an external memory instead of the internal memory of the microcomputer. In that case, however, the program storage memory 8 is simply provided outside, and the overall configuration is as follows. This is the same as FIG. FIG. 8 is configured by adding an interrupt reception number detection unit 23 to the circuit of FIG.

FIG. 9 is a circuit diagram showing an example of the number-of-interrupts detecting unit 23. The interrupt reception number detection unit 23 has two flip-flops D1 and D2. When the operation of the microcomputer is started after these resets, the interruption reception number detection unit 23 outputs “1” during interrupt service. Start counting the signal line 15
Until the first interrupt service, “0” is output to the signal line 24, and for the second and subsequent interrupt services, $ 1 is output.
Is output. Therefore, when "0" is input from the signal line 24 to the instruction queue 2, the instruction code stored in the instruction queue 2 is invalidated, and the instruction queue 2 is emptied.
On the other hand, when "1" is input to the instruction queue 2 from the signal line 24, the instruction code stored in the instruction queue 2 is not invalidated, and the instruction code remains stored.

When "0" is input from the signal line 24 to the prefetch pointer 5, the value held in the prefetch pointer 5 is invalidated. When "1" is input to the prefetch pointer 5 from the signal line 24,
The value held in the prefetch pointer 5 is not invalidated and remains held. FIG. 10 shows a program showing an example of an interrupt processing routine in this embodiment. In this interrupt processing routine program, FIG.
As seen from 0, the return instruction is arranged immediately before the address of the interrupt branch destination. With this program and the number-of-interrupts-detection unit 23, the speed of branch processing of the first accepted interrupt cannot be increased, but the instruction code of the branch destination is held in the instruction queue 2 after the second accepted interrupt branch. Therefore, the execution of the instruction does not have to wait until the prefetch operation is completed, and the speed can be increased.

Next, the operation will be described. In this embodiment, the operation other than when the interrupt is branched is the same as the operation in the first embodiment, and therefore only the operation when the interrupt is branched will be described. The operation at the time of this interrupt branch is
The operation differs between when the first interrupt is received and when the second and subsequent interrupts are received. When the first interrupt is received, “0” is output from the interrupt reception number detection unit 23 to the traffic light 24. When "0" is input from the signal line 24 to the instruction queue 2 and the prefetch pointer 5, the instruction queue 2 and the prefetch pointer 5 perform the same operation as that shown in FIG. Do. Here, at the time of execution of the return instruction (step S66), the return instruction is executed immediately before the interrupt branch destination in the interrupt subroutine program as shown in FIG. Instruction code is stored in the prefetch
The current value is held in the pointer 5.

Next, the operation when the second and subsequent interrupts are accepted will be described. FIG. 11 is a flowchart showing the operation when the second and subsequent interrupts are received. The second and subsequent interrupts occur (step S7).
0), when the interrupt is accepted and the interrupt service is being performed, the signal line 15 is set at $ 1 as described in the first embodiment.
Since the signal line 17 is set to "0", the instruction queue 2 to which the signal line 15 is input and the prefetch pointer 5 are operable, and the instruction queue 1 and the prefetch pointer 4 to which the signal line 17 is input are stopped. It will be in a state (step S71). Next, the values of PC and PSW are saved (step S72), and the address of the interrupt branch destination is set to PC.
Is set to (step S73). The operation so far is the same as the operation described with reference to FIG.

Further, in the operation shown in FIG.
Is set in the prefetch pointer and instruction execution cannot be started unless the instruction code of the interrupt branch destination is prefetched. However, when the first interrupt is processed, Are stored, and the prefetch pointer 5 holds the current value at that time, so that these values can be used. That is, when the second and subsequent interrupts are received, “1” is output from the interrupt reception number detection unit 23 to the signal line 24, and the instruction queue 2 and the prefetch
When the instruction code is input to the pointer 5, the instruction code stored in the instruction queue 2 and the current value of the prefetch pointer 5 are not invalidated, and the instruction code stored in the instruction queue 2 is used. The process is started from Step S54 of Step 2 (Step S74). Until the return instruction is executed, if necessary, the value held in the prefetch pointer 5 is used to execute step S50.
The prefetch operation from step S53 to step S53 is performed in parallel with the processing from step S54 described above (step S75). Thereafter, the processing (step S79) from the execution of the return instruction (step S76) to the shift to the processing in the main routine is the same as that described with reference to FIG.

In this embodiment, when the cause of the interrupt is 1
The configuration that enables high-speed branching in only one case is shown. Most microcomputers have a plurality of interrupt sources. To speed up each branch, an instruction queue, a prefetch pointer, and an interrupt acceptance number detection circuit are provided for each interrupt source. The configuration may be such that the instruction queue is switched and operated according to the interrupt factor currently being processed.

[0038]

As described above, according to the first aspect of the present invention, the first instruction queue which becomes operable during the main routine processing and the second instruction queue which becomes operable during the interrupt subroutine processing. The interrupt controller switches between the first instruction queue and the second instruction queue to operate according to whether the current processing is the main routine processing or the interrupt subroutine processing. Therefore, the instruction execution can be started without waiting for the instruction code to be stored in the instruction queue by the prefetch operation, and the effect of improving the response speed of returning from the interrupt subroutine to the main routine can be obtained.

According to the second aspect of the present invention, the second
A plurality of instruction queues within the number of interrupt priority levels are provided, and the interrupt controller switches one of the second instruction queues to the interrupt controller in accordance with the order of the interrupt nest processing in the current subroutine processing. Since the configuration is made to operate, the instruction execution can be started without waiting for the instruction code to be stored in the instruction queue by the prefetch operation, and the response speed of returning from the interrupt nest can be improved. Can be

According to the third aspect of the present invention, the return instruction comes immediately before the interrupt branch destination address on the interrupt subroutine program, and the interrupt acceptance number detection unit performs the following until the first interrupt service. Since the instruction code in the second instruction queue is invalidated, and the second and subsequent interrupt services are configured to store the instruction code stored in the second instruction queue and the branch destination of the interrupt, the prefetch operation is performed. Instruction execution can be started without waiting for the instruction code to be stored in the instruction queue, and the effect of improving the response speed at the time of interrupt branch can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the microcomputer in FIG.

FIG. 3 is a flowchart showing an operation of the microcomputer in FIG. 1;

FIG. 4 is a sequence chart showing an interrupt processing method according to the present invention.

FIG. 5 is a block diagram showing a microcomputer according to another embodiment of the present invention.

FIG. 6 is a circuit diagram showing an internal configuration of a decoder in FIG.

FIG. 7 is a circuit diagram showing an internal configuration of a decoder in FIG.

FIG. 8 is a block diagram showing a microcomputer according to another embodiment of the present invention.

9 is a circuit diagram showing an internal configuration of an interrupt reception number detection unit in FIG.

FIG. 10 is an explanatory diagram showing a program of an interrupt processing routine of the microcomputer shown in FIG. 8;

11 is a flowchart showing an operation of the microcomputer shown in FIG.

FIG. 12 is a block diagram showing a conventional microcomputer.

13 is a flowchart showing the operation of the microcomputer in FIG.

14 is a flowchart showing the operation of the microcomputer in FIG.

[Explanation of symbols]

 Reference Signs List 1 instruction queue (first instruction queue) 2 instruction queue (second instruction queue) 10 interrupt controller 23 interrupt number detection unit

Claims (3)

[Claims] 1. A first instruction queue which becomes operable at the time of main routine processing, a second instruction queue which becomes operable at the time of interrupt subroutine processing, and the current processing is a main routine processing or an interrupt subroutine processing. The first instruction queue or the second
And an interrupt controller that operates by switching any one of the instruction queues. 2. The interrupt controller according to claim 2, wherein a plurality of said second instruction queues are provided within the number of priority levels of the interrupts. 2. The microcomputer according to claim 1, wherein the microcomputer operates by switching one of the instruction queues. 3. An interrupt subroutine program in which a return instruction comes immediately before an interrupt branch destination address, and an interrupt reception number detecting unit detects an instruction in the second instruction queue until the first interrupt service. 2. The microcomputer according to claim 1, wherein the instruction code is invalidated and stored in the second instruction queue to hold the instruction code of the branch destination of the interrupt in the second and subsequent interrupt services.