JPH06161752A - Branch control system - Google Patents

Abstract

PURPOSE:To minimize the disorder of a pipeline at the time of the execution of a branch instruction by executing a following instruction first through a pipeline if there is contention about a resource between a conditional branch instruction and a precedent instruction, and carrying on the execution of the pipeline if a branch condition is met and no branching is performed and canceling the instruction when branching is performed. CONSTITUTION:A pipeline control part 3 decodes instructions and if the contention about the resource 4 is caused between the conditional branch instruction and precedent instruction, the branch instruction is reported to a branching decision part 2 and operation is instructed first without keeping the following instruction wait to feed the instruction to the pipeline of a pipeline processing part 1. When the branching decision part 2 determines the branching of the branch instruction, the pipeline control part 3 informs the pipeline processing part of that, and cancels the execution of the following instruction in the pipeline and also feeds the instruction at a branch destination to the pipeline. When no branching is determined, on the other hand, the instructions in the pipelines are executed as they are.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch control system for controlling a branch when an instruction is executed in a pipeline.

In recent years, in order to increase the instruction execution speed of computer systems, instruction execution by pipeline has become popular. Since this pipeline executes a plurality of instructions, resource (register, arithmetic unit, etc.) contention may occur. For this reason, in these pipeline control processors, resource conflicts are detected in each pipeline, data bypass, and execution of subsequent instruction pipelines are stopped until the preceding instruction releases the resource. There is. Bypassing the data causes a large increase in hardware, which may cause a decrease in the machine cycle of the processor as the gate size increases.
Further, when the execution of the subsequent instruction is stopped, the execution cycle of the subsequent instruction directly increases. Therefore, it is required to reduce the contention of resources as much as possible.

In addition, when a branch instruction is executed, it is necessary to invalidate the instruction that is being executed earlier in the pipeline and reinject the branch destination instruction into the pipeline, which delays the start of execution of the branch instruction. It is a branch instruction penalty. For this reason, if there is a resource conflict between the branch instruction and the preceding instruction, a considerable penalty occurs and the performance is effectively reduced, and it is necessary to reduce this penalty as much as possible.

[0004]

2. Description of the Related Art A conventional processor for pipeline control has a pipeline of instructions after a branch instruction when there is a resource conflict between the branch instruction and an instruction preceding the branch instruction so that data cannot be bypassed. It had stopped running on the line. For example, cycle → 0 1 2 3 4 5 6 instruction O L A S branch instruction J next instruction B 0 L A S next instruction B 1 L A S, next instruction B 0, B 1 has an instruction O preceding the branch instruction. In this case, the next instruction B0 and B1 after the branch instruction
Was stopped until the execution by the preceding instruction O was completed. In this example, the execution of the next instruction B0 in cycle 2 and the execution of the next instruction B1 in cycle 3 are stopped for 2 cycles each, and executed in cycles 4 and 5.

Here, L: pipeline load stage A: pipeline operation stage S: pipeline store stage

[0006]

As described above, in the conventional pipeline control, the branch instruction is a conditional branch instruction,
Even if the succeeding instruction does not have a resource conflict with other preceding instructions, the succeeding instruction cannot be executed, which causes a problem that the performance of the processor is deteriorated.

The present invention solves these problems.
If there is a resource conflict with the instruction that precedes the conditional branch instruction, the instruction that follows the conditional branch instruction is pipelined first, and if the branch condition is fixed and the branch does not occur, the pipeline is executed as it is. The purpose is to cancel the instruction in the pipeline when continuing and branching, and to minimize the disturbance of the pipeline when executing the branch instruction.

[0008]

FIG. 1 shows a block diagram of the principle of the present invention. In FIG. 1, a pipeline processing unit 1
Is to execute processing in a pipeline.

The pipeline control unit 3 decodes an instruction to determine a branch when it is a branch instruction, gives an operation instruction, gives an instruction to interrupt a subsequent instruction, and the like. The branch determination unit 2 determines whether or not a branch instruction branches.

The resource 4 is a resource such as a register.

[0011]

According to the present invention, as shown in FIG. 1, when a pipeline control unit 3 decodes an instruction and a contention of a resource 4 occurs between a conditional branch instruction and an instruction preceding it, a branch instruction is detected. Whether the branch determination unit 2 is notified and the instruction subsequent to the conditional branch instruction is instructed to be put into the pipeline of the pipeline processing unit 1 without waiting and the branch determination unit 2 branches the branch instruction. When it is determined that the branch is determined, the pipeline control unit 3 receives a notification to that effect and notifies the pipeline processing unit 1 to cancel the execution of the subsequent instruction in the pipeline and to execute the instruction at the branch destination. The instruction is put into the pipeline, and on the other hand, when it is decided not to branch, the execution of the instruction in the pipeline is continued.

Therefore, when there is contention of the resource 4 with the instruction preceded by the conditional branch instruction, the instruction following the conditional branch instruction is executed in the pipeline first, and the branch condition is determined and the branch is not taken. By continuing the execution of the pipeline as it is and canceling the instruction in the pipeline at the time of branching, it is possible to minimize the disturbance of the pipeline at the time of executing the branch instruction.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of the principle. In FIG. 1, a pipeline processing unit 1 executes processing in a pipeline, and according to an instruction from the pipeline control unit 3, reads a resource 4, performs an operation, etc. It is to make changes.

The branch determination unit 2 holds a branch condition,
For example, the branch determination of the branch condition is performed. The pipeline control unit 3 holds and decodes instruction codes, detects contention of resources 4 between instructions, performs bypass control of pipeline data in the pipeline processing unit 1, and controls pipeline transitions. The branch determination unit 2 is instructed to set a branch condition, the branch determination result by the branch determination unit 2 is fetched, and the instruction execution by the pipeline is canceled (interrupted) at the time of branching.

The resource 4 is a resource such as a main memory or a general-purpose register. Next, the operation of the configuration of FIG. 1 will be described. (1) The fetched instruction sequence is stored in the pipeline control unit 3
Store and hold in. The pipeline control unit 3 decodes the held instruction code and determines whether or not it is a branch instruction. If it is not a branch instruction, the pipeline processing unit 1 is given an operation instruction based on the instruction decoding result. The pipeline processing unit 1 reads out the resource 4 according to the operation instruction, performs an operation or the like according to the instruction, and then changes the resource 4 according to the instruction.

(2) On the other hand, the pipeline controller 3 is
If it is a branch instruction, the branch determination unit 2 is notified of the branch condition and the execution of the branch instruction is delayed until there is no conflict of the resources 4 used for the determination of the branch instruction. During this time, when the next instruction reaches the pipeline stage for rewriting the resource 4, the pipeline processing unit 1 is instructed to hold the execution of the instruction. When there is no competition for the resources 4 used in the branch instruction, the branch determination signal sent by the branch determination unit 2 is fetched, and if the branch condition is not satisfied, the pipeline processing unit 1 continues the pineline processing. . When the branch condition is satisfied, the pipeline processing by the pipeline processing unit 1 is interrupted (cancelled), and an operation instruction of the branch destination instruction is given.

As described above, in the conditional branch instruction, even if there is contention of the resource 4 between the conditional branch instruction and the instruction preceding it, if the branch does not occur,
It is possible to continue the pipeline processing by the pipeline processing unit 1 without any disturbance (in the case of (d) in FIG. 2). This will be described sequentially below.

FIG. 2 shows a block diagram of an embodiment of the present invention.
This is the pipeline processing unit 1 of FIG.
1 is a configuration of an embodiment of a pipeline control unit 3 and a resource 4.

In FIG. 2, the resource 4 is a general-purpose register 4
-1 and a selector 4-2. Selector 4
Reference numeral -2 is a selector that outputs the contents of the general-purpose register 4-1 designated by the pipeline control unit 3.

The pipeline processing section 1 is composed of three stages of pipelines. Load stage 1-1 is general purpose register 4
Load -1 data. The operation stage 1-2 generates an operation result based on the contents of the general-purpose register held by the load stage 1-1. The changing stage 1-3 is a stage for changing the general-purpose register 4-1.
General-purpose register 4 for storing the operation result generated in -2
Transfer to -1.

The branch judgment unit 2 holds the data of the general-purpose register 4-1 in the register 2-1 and the pipeline control unit 3
The determination condition output from the register is held in the register 2-2.
Depending on the condition judging circuit, the register 2-1 and the register 2-2
The branch determination signal 2-3 is output according to the output of.

The pipeline control unit 3 has instruction code holding registers 3-1, 3-2, 3-3 corresponding to each stage of the pipeline processing unit 1. The instruction decoding unit 3-4 decodes the input instruction code, and gives the branch determination unit 2 a branch condition sending and setting instruction. The branch number register 3-5 holds a general-purpose register number referred to by a branch instruction. Conflict detection circuit 3-6
Detects that the register number held in the branch number register 3-5 is changed by the instruction held in the instruction code holding registers 3-1, 3-2, 3-3. When it is confirmed by the conflict detection circuit 3-6 that there is no conflict and the branch determination signal 2-3 is ON, the branch control unit 3-7 suspends the instruction execution of the pipeline processing unit 1 and A branch signal 3-7 is sent to the line processing unit 1 to instruct the input of a branch destination instruction.

Next, the operation will be specifically described with reference to FIG. FIG. 3 shows an example time chart of the present invention. FIG. 3A is a time chart when there is no resource competition, and shows a case where the branch condition is satisfied.

In FIG. 3A, the instruction O is an instruction executed before the branch instruction, and the L / A / S instructions are the load stage 1-1 and the operation stage 1-2, respectively.
/ Store (change) Indicates that the stage is in stage 1-3. When the branch signal is turned on by the judgment of the branch instruction, the instructions J0 and J1 of the branch destination are executed. In this example,
There is no branch penalty.

FIG. 3B is a time chart when there is no resource competition, and shows the case where the branch condition is not satisfied. In FIG. 3B, the instruction O is an instruction executed before the branch instruction, and the L / A / S instructions are the load stage 1-1 / operation stage 1-2 / store (change) stage, respectively. It is shown in 1-3. Since the branch signal is not turned on by the determination of the branch instruction, the instructions B0 and B1 are executed after the branch.

FIG. 3 (c) is a time chart when there is competition for resources, and shows the case where the branch condition is satisfied. That is, it is a time chart when the instruction O immediately before the branch instruction rewrites the general-purpose register 4-1 used for the determination by the branch instruction.

The determination of the branch instruction is delayed until the time (Time) 3 when the execution of the instruction O is completed, but the next instruction B0, B
1 starts execution without waiting. At time 3, since the branch signal is turned on, the execution of the next instructions B0 and B1 is stopped and the instructions J0 and J1 at the branch destination are executed. The branch instruction penalty in this case is 2 cycles, and the next instruction B
The cycles in which 0 and B1 are executed are wasted.

FIG. 3 (d) is a time chart when there is competition for resources, and shows the case where the branch condition is not satisfied. The determination of a branch instruction is made at the time (T
(image) 3 is waited, but the next instruction B0, B1 starts execution without waiting. At time 3, since the branch signal is not turned ON, the next instructions B0 and B1 are continuously executed. In this case, there is no branch penalty, even though the execution of the branch instruction has been delayed for two cycles.

Next, referring to the flow chart of FIG.
The operation of the above configuration will be described in detail. Here, the pipeline control unit 3, the branch determination unit 2, and the pipeline processing unit 1
Corresponds to FIG. 1 and FIG. 2, respectively.

In FIG. 4, in S1, the pipeline control unit 3 decodes the instruction code. In S2, decoding of S1 is performed, and it is determined whether or not there is resource competition. If yes, wait until there is no conflict of resources. On the other hand, in the case of NO, since there is no resource conflict, the process proceeds to S3 and the branch determination unit 2 is notified of the set signal at the time of a branch instruction.

In step S11, the branch determination unit 2 which receives the notification of the branch instruction from the pipeline control unit 3 sets the branch determination data (branch determination result data), and the pipeline determination signal is pipeline controlled according to the branch determination. Notify Part 3.

In S3, it is determined whether or not the pipeline control unit 3 which has received the branch determination signal according to the branch determination from the branch determination unit 2 in S12 is a branch taken. In the case of YES, since it is determined that the branch determination is made, the suspension instruction is notified to the pipeline processing unit 1. Then, the process returns to S1 and is repeated.

In S21, the pipeline processing unit 1 fetches subsequent instruction data. In S22, the subsequent instruction fetched in S21 is calculated. In S23, it is determined whether or not there is an interruption instruction. This is because the pipeline processing unit 1 receives the interruption instruction when it is found that the branch instruction is branched in (c) of FIG. 3 described above, and determines whether there is an interruption instruction. In the case of YES (when it is determined that there is an interruption instruction), the subsequent instruction is interrupted in S24 (for example, the next instruction B0 or B1 in (c) of FIG. 3 is stopped), and the branch destination instruction data is fetched in S25 ( For example, the branch destination instructions J0 and J1 in FIG. 3C are fetched) and the process returns to S22. On the other hand, in the case of NO, there is no interruption instruction, so the resource is rewritten in S26 and S21
Return to.

As described above, the instruction code fetched by the pipeline control unit 3 is decoded, and at the time of a branch condition instruction, the instruction following it (next instruction) is input to the pipeline and executed, and the branch condition instruction is executed. When it is determined that the branch condition does not branch, the pipeline processing continues as it is. On the other hand, when the branch condition is determined to branch, the subsequent instruction is canceled and the branch destination instruction is input to the pipeline. Then run. As a result, even if there is contention of the resource 4 between the branch conditional instruction and the instruction preceding it, the next instruction is put into the pipeline and executed, and if the branch is not taken when the condition is determined, it is executed as it is. Therefore, the instruction can be executed at high speed without any penalty.

[0036]

As described above, according to the present invention,
If there is a resource conflict with the instruction that precedes the conditional branch instruction, the instruction that follows the conditional branch instruction is executed first in the pipeline, and if the branch condition is fixed and the branch is not executed, the pipeline is executed as it is. Since it adopts a configuration that cancels the instruction in the pipeline when branching,
It is possible to minimize the disturbance of the pipeline when executing a branch instruction.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a time chart of a specific example of the present invention.

FIG. 4 is an explanatory diagram of the operation of the present invention.

[Explanation of symbols]

 1: Pipeline processing unit 2: Branch determination unit 3: Pipeline control unit 4: Resources

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Watanabe Inventor Toru Watanabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Maruyama 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Takeno 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Shinya Kato, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Pawnshai Chon Swan Napaisan 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Satoshi Satagawa, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. A branch control method for controlling a branch when an instruction is executed in a pipeline, wherein a conditional branch instruction follows a conditional branch instruction when a resource conflict occurs between the conditional branch instruction and an instruction preceding the conditional branch instruction. The instruction to be executed is first put into the pipeline and executed without waiting, and if the conditional branch instruction is determined not to branch, it continues as it is. A branch control method characterized by being configured so that the preceding instruction is put into a pipeline and executed.