JP2636566B2 - Pipeline control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for performing a pipeline process, and a process for executing an instruction process at a high speed when it is detected that there is register interference between a preceding instruction and a following instruction. About the method.

[0002] The pipeline processing is a processing method in which one instruction processing is divided into a plurality of processings (states) and a plurality of instruction processings are executed in parallel. FIG. 5 shows an example of the pipeline processing composed of six stages. The plurality of divided processes are distinguished by the name of each state. In FIG. 5, the pipeline processing is performed by sequentially passing each state of D state, A state, T state, B state, E state, and W state.

Here, in the D state, instruction decoding,
In the A state, the address is calculated, in the T state, the index of the address translation buffer (TLB) is read, in the B state, the cache is read, in the E state, the operation is executed, and in the W state, the operation result is stored in the register.

The same state is not set between a plurality of instruction processes. Information used for processing performed in each state is called a pipeline tag, and is constituted by a shift register that is sequentially shifted as the processing proceeds.

[0005] The time for processing one state is called one machine cycle. If pipeline processing operates ideally, N instructions appear to end in N machine cycles.

However, in the pipeline processing,
Register interference may occur between the preceding instruction and the succeeding instruction. Even in such a case, it is required that the N instructions can be controlled so as to end in N machine cycles.

[0007]

2. Description of the Related Art FIGS. 6 to 9 are diagrams for explaining a conventional pipeline processing method. FIG. 6 is an operation time chart in a case where pipeline processing is interrupted by a pipeline interlock. FIG. 8 shows an operation time chart when the operation state is pipelined.
FIG. 9 shows an operation time chart when an instruction for performing pipeline processing of an operation state and an instruction for not performing pipeline processing of an operation state follow. FIG. 9 shows register interference between an instruction with a V state and a V state variable instruction. 5 shows an operation time chart in the case where an error occurs.

In an information processing apparatus that performs pipeline processing, there is a pipeline interlock as a factor that hinders the ideal operation of pipeline processing. A typical example is an E-state interlock for preventing an operation from being completed in one cycle. In the processing of a floating point instruction or the like, an instruction cannot be processed every cycle as shown in FIG. Therefore, as shown in the figure, when the E-state interlock is applied, the subsequent instructions are applied with the B-state interlock, the T-state interlock, the A-state interlock, and the D-state interlock. As shown, for example, the start of the sixth instruction is delayed by one cycle as compared with FIG.

However, in an information processing apparatus that requires high speed, instruction processing for each cycle is realized by pipelining the operation state. In the example of FIG. 7, by dividing the operation state into the E state and the V state, pipeline processing for each cycle is realized as illustrated.

[0010] Even in the above technique, if the instruction with the V-state (instruction 1) and the instruction without the V-state (instruction 2) are executed in succession, a loss time will occur. FIG. 8 shows this example. In this example, since the instruction 1 is an instruction with a V state and the instruction 2 is an instruction without a V state, the W state is controlled by the B state interlock so as not to overlap.

As a result, as shown in the figure, the start of the sixth instruction is delayed by one cycle. In such a case, in order to reduce the loss time, a technique for executing an instruction without a V-state immediately after an instruction with a V-state as an instruction with a V-state is disclosed in Japanese Unexamined Patent Application Publication No. Hei 2-069825.
No. 6,086,045.

In the above technique, since the instruction 1 in FIG. 8 is an instruction with a V state, an ideal pipeline operation can be performed by executing the instruction 2 as an instruction with a V state. Further, in this technique, whether a V state is added or not is made variable (however, a floating point data load instruction), and if an instruction without a V state is executed before the instruction, a V state variable instruction is executed. Is executed as a V-stateless instruction to reduce the loss time.

[0013]

In the above technology,
The purpose is to reduce the loss time when an instruction without a V state is executed before and after the instruction by variably attaching the V state. If register interference occurs in between, loss time still occurs.

This example is shown in FIG. 9 (a). As shown in FIG. 9 (a), according to the above technique, the L immediately after the AD instruction is used.
The PDR instruction (load positive register instruction: load instruction) is unconditionally executed as an instruction with a V-state, but attempts to read the result register of the AD instruction with the LPDR instruction (that is, the result of the AD instruction and the LPDR instruction). When there is a register interference between the two), the LPDR instruction interlocks in the B state until the timing at which the result of the AD instruction can be bypassed. As a result, the execution of the next AR instruction is delayed. FIG. 9 (b) shows the LPD
The case where the R instruction is executed as an instruction having no V cycle is shown. The execution of the AR instruction is one cycle faster than the case of FIG. 9A.

In the example of FIG. 9B, the subsequent AR instruction is V
Since it is processed as a stateless instruction, A in FIG.
The R instruction is one cycle later than the AR instruction in FIG. 9B. However, since the AR instruction is an instruction for updating a general-purpose register, it cannot be easily set as an instruction with a V state. That's why.

That is, as described above, since the instruction with the V-state is intended for a floating-point operation instruction whose operation cycle does not end in one cycle, the above-mentioned AR instruction or the like which updates a general-purpose register is used. In the case where the general-purpose register is configured to operate as the V-state instruction, the general-purpose register is different from the floating-point register,
Since it is used not only for the operand of the operation but also for the address calculation for memory access, if the register update cycle is delayed by attaching the V state, the configuration such as the means for bypassing data to the address calculation circuit becomes very large. It becomes complicated.

In the above prior art example, the operation execution state has been described as two states, E and V. However, it is possible to further define these states as E, V ₁ , V ₂ , V ₃ ,. It can be realized relatively easily as long as the addition of the quantity is allowed.

In the device having such a configuration, as shown in the above-mentioned technology, not only a load-related instruction (LPDR instruction) to a floating-point register is set as an operation execution state variable instruction but more general instructions are used. Since a typical floating-point instruction can be an operation execution state variable instruction, the case shown in FIG. 9A, that is, the preceding instruction is an instruction with a V state, and the preceding instruction and the V state variable instruction (LPDR If the instruction has a register interference, the processing time of an instruction (AR instruction) that cannot be added with the subsequent V state becomes longer in many cases.

FIGS. 10A and 10B are diagrams for explaining the problem of the floating-point load instruction. FIG. 10A shows a case where a B-state interlock exists, and FIG. In the case where there is register interference between these instructions.

In the above technique, as described above, the purpose is to reduce the loss time when an instruction without a V state is executed before and after the instruction by variably attaching the V state. If the register interference occurs between this instruction and the immediately preceding instruction with a V-state, a loss time still occurs, as is apparent from FIG.

That is, as shown in FIG. 10A, according to the above technique, an LDR instruction (migration instruction between long precision registers) immediately after an AD instruction is unconditionally executed as an instruction with a V state. Sets the result register of the AD instruction to L
If an attempt is made to read with a DR instruction (ie, there is register interference between the AD instruction and the following LDR instruction), the A
The LDR instruction is interlocked in the B state until the timing at which the result of the D instruction can be bypassed. As a result, the execution of the next AD instruction is delayed due to the interlock in the T state.

Therefore, for example, as shown in FIG.
When control is performed to suppress the B-state interlock of the LDR instruction, when there is register interference between the LDR instruction and a subsequent AD instruction, the timing at which the result of the LDR instruction can be bypassed Until then, there remains a problem that an AD instruction described later interlocks in the B state.

The present invention has been made in view of the above-mentioned conventional drawbacks, and is an information processing apparatus provided with an operation execution state including a plurality of machine cycles and configured to perform a pipeline of the operation execution. When an instruction for ending the operation execution state in N (= 1) cycles is input to the pipeline immediately after the instruction for ending the operation execution state, if M> N, an instruction for ending the operation execution state in N cycles is issued. An information processing apparatus comprising: a control unit for forcibly executing an operation in M cycles; and a B-state interlock signal generation unit for performing a B-state interlock when register interference is detected between the two instructions. To eliminate the delay in the execution time of a subsequent instruction caused by forced M-cycle execution calculation or B-state interlock It is an object to provide a pipeline control method capable of.

[0024]

FIG. 1 is a view showing an embodiment of the present invention, and FIGS. 2 and 3 are views showing another embodiment of the present invention. FIG. 2 shows an example in which the V state of a V state variable instruction is suppressed when there is register interference with the preceding instruction. FIG. 2 shows the register interference between the register register moving instruction (LDR instruction) and the preceding instruction. FIG. 3 shows an example of suppressing the B-state interlock operation in the case where there is an instruction.
R instruction) and its preceding instruction have register interference, and the register-to-register move instruction (LDR instruction)
If there is register interference with the following instruction,
An example is shown in which the operation result of the preceding instruction is bypassed to the subsequent instruction.

The above problem is solved by a pipeline control system configured as follows. (1) Operation execution state consisting of multiple machine cycles
An information processing device provided with (E, V) and configured to perform a pipeline process for execution of an operation, wherein the operation execution state is terminated in N cycles immediately after an instruction for terminating the operation execution state in M cycles. An information processing apparatus provided with control means 802 for forcibly executing an instruction for ending the operation execution state in N cycles in M cycles if M> N when an instruction is input to the pipeline. In the above, when interference occurs between the write register and the read register between the two instructions, the control means 802 causes the instruction to end the operation execution state in N cycles to execute the operation in M cycles. Is controlled so as to suppress the situation.

(2) Operational operation consisting of a plurality of machine cycles
Set the row state (E, V) to pipeline the execution of operations.
Operation execution state in M cycles
Operation execution state in N cycles immediately after the instruction to end
If an instruction that terminates is entered into the pipeline, M
If> N, the operation execution state ends in N cycles
Instruction is forcibly executed in M cycles.
Control means 802 and register interference detected between two instructions
When the interlock signal generates the interlock signal
In the information processing apparatus including the signal generation unit 806, the N
An instruction that terminates the operation execution state in a cycle
A movement command, wherein the control unit
N cycles immediately after the instruction to end the operation execution state
Register between instructions that end the execution state
When interference is detected, information indicating the register interference
That is, while holding the interlock control bit,
Based on the interlock control bit,
B state interface generated by lock signal generation section 806
The lock signal is suppressed, and the operation execution
Register transfer instruction that terminates
Control to run.

(3) In the information processing device of the above item (2),
A register that completes the operation execution state in the above N cycles
Register interference between the move instruction and the preceding instruction
And the operation execution state ends in the above N cycles.
The instruction following the register-to-register move instruction
Instruction to end the operation execution state
When it detects that it is trying to use the result register
Register to end the operation execution state in the above N cycles
The operation result of the preceding instruction of the
Move instruction between registers to end operation execution state
Bypass means for bypassing to subsequent instructions
The register for ending the operation execution state in the above N cycles
In the instruction following the inter-star move instruction, the bypass
Control is performed so as to calculate using the result register information.

[0028]

According to the present invention, when an instruction for ending the execution state in N (= 1) cycles is input to the pipeline immediately after the instruction for ending the execution state in M (= 2) cycles, M> If N, in the information processing apparatus provided with control means 802 for forcibly executing an instruction to end the operation execution state in N cycles in M cycles, a write register and a read register If there is interference between the control means 802
, The execution of an instruction that ends the operation execution state in N cycles is prevented from being executed in M cycles.

In the case as shown in FIG. 1, when register interference is detected between the AD instruction (instruction 1) and the LPDR instruction (instruction 2), the control means 802 controls the operation execution state variable instruction LPDR The instruction (instruction 2) is executed in the original shortest operation execution cycle, that is, one cycle of the E state.

Therefore, as shown in FIG.
The effect that the execution cycle of the AR instruction following the DR instruction (instruction 2) can be shortened by one cycle as compared with the conventional method shown in FIG. 9A is obtained.

In the present invention, as shown in FIG.
When an instruction (LDR instruction) for ending the operation execution state in N (= 1) cycles is input to the pipeline immediately after an instruction (AD instruction) for ending the operation execution state in (= 2) cycles, M> If N, in the information processing apparatus provided with the control means 802 for forcibly executing an instruction to end the operation execution state in N cycles in M cycles, the N-cycle instruction is an instruction for moving between registers. (LDR instruction)
When the interference between the write register and the read register between the instructions is detected, the information is held as an interlock control bit, and the inter-register-register movement instruction (LDR
M) (= 2) cycles having a V state by controlling the B-state interlock signal generation means 806 by causing the B instruction to generate the B state interlock signal due to register interference with the preceding instruction (AD instruction). It is intended to be executed by.

A register-to-register movement instruction (LDR)
Instruction) and its preceding instruction (AD instruction) cause register interference, and the register-to-register move instruction (LD
As shown in FIG. 3, when the instruction following the R instruction) (AD instruction) attempts to use the result register of the register-to-register transfer instruction (LDR instruction) (that is, when there is register interference), At 807, using the retained information of the above description, ie, the interlock control bit, a move instruction between registers (LDR instruction)
The result of the preceding instruction is transferred to the register-to-register instruction (LD
A means for bypassing to the instruction following the R instruction is provided.
Instruction) to obtain the same effect as using the result register, without causing a B-state interlock even when register interference occurs, and using M (=
2) The speed of pipeline processing is increased while maintaining the cycle instruction.

[0033]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing one embodiment of the present invention.
2 and 3 are diagrams showing another embodiment of the present invention.
FIG. 4 shows a basic configuration example of the pipeline processing.

According to the present invention, there is provided an information processing apparatus having an operation execution state (E, V) comprising a plurality of machine cycles and performing a pipeline process of the execution of the operation by, for example, the E and V states. Immediately after the instruction for ending the operation execution state in the cycle, when an instruction for ending the operation execution state in the N cycle is input to the pipeline, if M> N, the operation execution state is changed in the N cycle. In an information processing apparatus provided with a control means 802 for forcibly executing an instruction to be completed in M cycles in an M cycle, when interference occurs between a write register and a read register between the two instructions, Control means for execution Means for suppressing 802. When the N-cycle instruction is a register-register move instruction (LDR instruction), and register interference between the two instructions is detected,
A signal (interlock control bit) for suppressing the B-state interlock signal is provided, and the B-state interlock signal generated by the B-state interlock signal generating means 806 is a signal for suppressing the B-state interlock signal. Means to suppress and execute in M cycles. Further, when there is register interference between the above-mentioned register-register movement instruction (LDR instruction) and its preceding instruction, and there is also register interference between the register-register movement instruction (LDR instruction) and the following instruction, Using the B-state interlock suppression signal, the register-to-register move instruction (LDR instruction)
Means for bypassing the operation result of the preceding instruction to the succeeding instruction of the register-to-register move instruction (LDR instruction) is a means necessary for implementing the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

The pipeline control system of the present invention will be described below with reference to FIGS. In this embodiment, the pipeline processing is performed in six states or seven states for simplicity.

The main processing in each state will be described with reference to FIG. In the D state, the operation code is decoded, the data for address calculation is read from the register stack (including the general-purpose register GR and the floating-point register FR), and the register 701 (base register) and the register 70 are read.
2 (index register).

In the A state, the registers 701, 70
2 is added by the address adder 703, and the result is set in the register 704 as an effective address. T
In the state, the effective address is translated into a real address by a TLB (translation index buffering mechanism: the above-described address translation buffer) and set in the register 705.

In the B state, LBS is determined by a real address.
Data is read from (local buffer storage: a copy of main memory data is held and can be accessed at high speed) and set in the register 706.

In the E state, an operation is performed, and the result is set in the register 708. In the W state, the above operation result is written to the register stack. The contents of these registers can be set in the register 707 by the register operand bus 709 and sent to the arithmetic unit.
When there are multiple operation execution states, be sure to
The operation unit is adjusted so that the operation result is stored in the register 708 in the W state.

FIG. 2 shows an embodiment of the main control section of the present invention. The register 801 is a register for holding the instruction code of the A cycle, and receives the output thereof to
Then, a control signal for setting the registers 803, 804, and 805 is output.

The register 803 is a register indicating that the instruction to be processed writes in the register.
A register 804 holds a write register number, and a register 805 indicates the number of cycles (M, N described above) of the operation execution state of the instruction to be processed.

The contents of the operation execution cycle number register 805 are sent to the operation control unit in the T state to instruct the operation control unit to execute a predetermined number of operation execution state processes. In the example of FIG. 1, the instruction 1 changes the operation execution state to two states (E, V
State) indicates that the instruction is required. 1
Instruction 2 is executed with a cycle delay. In the A state of the instruction 2, the number of operation execution states of the own instruction is determined with reference to the contents of the operation execution cycle number register 805 indicating the number of operation execution states of the instruction 1.

That is, if the instruction 2 is an instruction that requires at least three or more operation execution states, the number is shown, and otherwise the same two operation execution states as the instruction 2 (described above). The contents of the operation execution cycle number register 805 are set so as to indicate the (E, V state). At that time, the registers 803 and 804
It is checked whether there is register interference between the write register and the read register from the contents of the register and the register read number decoded from the contents of the operation code register 801 holding the instruction code of the own instruction.

As a result of the register interference check, if there is a register interference, the contents of the operation execution cycle number register 805 are set so as to indicate the shortest operation execution state number of the instruction 2. As described above, in the present invention, the contents of the operation execution cycle number register 805 include the number of operation execution states of the previous instruction, the write register address of the previous instruction,
It is determined so that the loss time is shorter than the shortest operation execution state number of the instruction and the read register address of the instruction.

Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows a time chart and a control circuit section of another embodiment according to the present invention. In the A state, the operation code of the instruction set in the operation code register 801 is decoded to obtain an operation instruction code and a write register address, and are set in the operation instruction code register and the write address register 804, respectively.
In addition, a write control bit for controlling register writing is generated and set in the write control register 803.

In the A cycle of the LDR instruction, the above AD
The instruction write address register 804, write control register 803, and read register address and read control bit obtained by decoding the operation code of the LDR instruction are input to the control circuit 802.

When the control circuit 802 detects register interference between the AD instruction and the LDR instruction, it instructs the operation instruction code to be set to no operation so that the LDR instruction does not move between registers.

Further, the interlock control bit is turned on by detecting the condition of the register interference.
In the B state of the LDR instruction, the write register address of the AD instruction (contents of the register 804) and the read register address of the LDR instruction are input to the B state interlock signal generation circuit 806. When the register interference is detected, the B state interlock signal Generate However, when the interlock control bit generated by the control circuit 802 is “ON”, control is performed so as not to output the B-state interlock signal.

Therefore, when there is register interference, L
The DR instruction proceeds to the W state without any operation and without performing the B state interlock executed when there is a normal register interference.

Since the operation result of the preceding AD instruction is held as it is, it is written to the register stack according to the write register address indicated by the write address register 804 of the LDR instruction.

FIG. 3 shows another embodiment of the present invention.
7 shows a time chart and an embodiment of a control circuit unit when register interference occurs between a DR instruction, a preceding instruction, and a subsequent instruction.

The operation at the time of register interference between the preceding AD instruction and the LDR instruction is as shown in FIG. In this case, a bypass route is provided to bypass the operation result of the preceding AD instruction to the operation state E of the instruction following the LDR instruction.

The control circuit 807 for the subsequent AD instruction includes:
The write address of the LDR instruction, the interlock control bit, and the read address of the subsequent AD instruction are input. Writing the LDR instruction and the subsequent AD
When register interference occurs during instruction reading and the interlock control bit is “on”, the bypass control latch 902 is turned on.

As a result, the bypass means is selected for the input of the arithmetic unit so that the result of the AD instruction preceding the LDR instruction is selected. If the interlock control bit is "off", the preceding AD instruction and the L
Since it means that there is no register interference with the DR instruction, the B-state interlock of the LDR instruction is performed until the result of the LDR instruction can be bypassed.

Further, if no interference occurs between the LDR instruction and the subsequent AD instruction, the register 90 in which the contents of the register stack selected by the read register address are set is set.
3 is input to the arithmetic unit.

As described above, in the present invention, the operation execution state (E, V) including a plurality of machine cycles is provided.
An information processing apparatus for performing a pipeline process for execution of an operation, wherein an instruction to end the operation execution state in N cycles is input to the pipeline immediately after an instruction to end the operation execution state in M cycles. If M> N, in an information processing apparatus provided with control means 802 for forcibly executing an instruction for ending the operation execution state in the N cycles in the M cycle, a write register is provided between the two instructions. When the interference occurs between the read registers, the control means 802 for executing the operation in the M cycle is suppressed, or the N cycle instruction is a register register move instruction (LDR instruction) and the two instructions are Means for suppressing the B-state interlock signal when register interference is detected between the B-state interlock signals. Then, the B-state interlock signal generated by the B-state interlock signal generating means 806 is suppressed to be executed in M cycles, or the register-register movement instruction (LDR instruction) and the When there is register interference between the preceding instruction and register interference between the register-to-register move instruction (LDR instruction) and the subsequent instruction,
Using the signal of the state interlock inhibiting means, the operation result of the preceding instruction of the register-to-register movement instruction (LDR instruction) is transferred to the register-to-register movement instruction (LDD instruction).
A characteristic is that the instruction is bypassed to the instruction following the (R instruction).

[0057]

As described in detail above, the pipeline control system of the present invention has an operation execution state (E, V) consisting of a plurality of machine cycles, and information for executing the operation by pipeline processing. A processing device, wherein when an instruction for ending the operation execution state in N cycles is input to the pipeline immediately after the instruction for ending the operation execution state in M cycles, if M> N, The instruction to end the operation execution state in N cycles is forcibly set to M
In the information processing apparatus provided with the control unit 802 for performing the operation in the cycle, the control unit 802 for performing the operation in the M cycle is suppressed when the interference occurs between the write instruction and the read register between the two instructions. Or,
Further, when the N-cycle instruction is a register-to-register movement instruction (LDR instruction) and a register interference between the two instructions is detected, means for suppressing a B-state interlock signal is provided. Means for suppressing the lock signal, suppressing the B-state interlock signal generated by the control means 806, and executing it in M cycles; There is register interference between the preceding instructions, and the move instruction between registers (L
When there is register interference between the DR instruction and the subsequent instruction, the operation result of the preceding instruction of the register-to-register transfer instruction (LDR instruction) is obtained by using the signal of the B-state interlock inhibiting means. Since the instruction is bypassed to the instruction following the register-to-register move instruction (LDR instruction), even if there is register interference between instructions, pipeline processing of each instruction is performed without loss time. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 shows another embodiment of the present invention (part 1).

FIG. 3 shows another embodiment of the present invention (part 2).

FIG. 4 is a diagram showing a basic configuration example of pipeline processing;

FIG. 5 is a diagram showing an example of a pipeline processing composed of six stages.

FIG. 6 illustrates a conventional pipeline processing method (part 1).

FIG. 7 illustrates a conventional pipeline processing method (part 2).

FIG. 8 illustrates a conventional pipeline processing method (part 3).

FIG. 9 illustrates a conventional pipeline processing method (part 4).

FIG. 10 is a diagram illustrating a problem of a floating-point load instruction.

[Explanation of symbols]

701, 702, 704 to 708 Register 703 Adder 801 Operation code register 802 Control circuit 803 Write control register or write control bit 804 Write address register 805 Number of operation execution cycles register 806 B state interlock generation unit 807 Control circuit Operation instruction code B state interlock Signal bypass route or bypass means interlock control bit or interlock control register

Claims (2)

(57) [Claims] An arithmetic execution switch comprising a plurality of machine cycles.
State, so that computation execution is pipelined
And terminates the operation execution state in M cycles
The operation execution state ends in N cycles immediately after the instruction
M> N if the instruction is entered into the pipeline
Instruction to end the operation execution state in N cycles
Control means for performing arithmetic execution in M cycles
When register interference is detected between two instructions,
An interlock signal generator for generating a lock signal is provided.
In the information processing apparatus, the instruction for ending the operation execution state in the N cycles is
An inter-register movement command, wherein the control means outputs the M
N cycles immediately after the instruction to end the execution state
Registers between instructions that end the operation execution state on a cycle
When interference is detected, information indicating the register interference is given.
While maintaining the interlock based on the information.
The interlock signal generated by the
Register to end the operation execution state in the N cycles.
Control to execute the inter-star movement instruction in M cycles
A pipeline control method characterized by the following. 2. The information processing apparatus according to claim 1, wherein
The register for ending the operation execution state in the above N cycles
Register interference between the star move instruction and the preceding instruction
And the operation execution state ends in the above N cycles.
The instruction following the register-to-register move instruction
The result of an inter-register move instruction that ends the operation execution state
A register that terminates the operation execution state in the above N cycles when detecting that the register is about to be used.
In the above N cycles, the operation result of the instruction preceding the
Subsequent to an inter-register move instruction that ends the operation execution state
A register for providing a bypass means for bypassing an instruction and ending the operation execution state in the N cycles
In the instruction following the inter-move instruction, the result
It is controlled to operate using the register information.
Pipeline control method.