JPH04326425A - Loop processing control system - Google Patents

Abstract

PURPOSE:To actuate both branch and non-branching operations with no time loss of a CPU and to improve the performance of a loop processing control system by fetching the instruction of a branching destination right after a branch instruction in a branch state. CONSTITUTION:The information which estimates a branch instruction for loop processing is added to the microinstruction that is stored in a memory 1. A counter value detection mechanism 11 activates the output signal of a loop processing counter 12 when the value of the counter 12 is not equal to 1. A 3-input adder 8 adds a constant, i.e., the process number of a single loop held by a constant register 7 and a relative address 9 between the branch instruction and the instruction of a branching destination to the value of a microinstruction counter 6 which holds the address of the microinstruction under execution. Then the output result of the adder 8 is fetched as the address of the memory 1 when both the signal showing the information that estimates the branch instruction and the output signal of the mechanism 11 are active.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer control system, and more particularly to microinstruction execution control that performs loop operations.

0002

[Background Art] Conventionally, in a microprocessor that performs pipeline processing using microinstructions, when executing a microinstruction that instructs a conditional branch, if the branch condition is not satisfied, the flow of the pipeline is continued without changing the flow of the pipeline. However, if the branch condition is satisfied, that is, if a branch is to be taken, it is necessary to re-fetch from the branch destination instruction, so the flow of the pipeline is temporarily stopped and the branch destination instruction is executed. I had to wait until the instructions flowed down the pipeline. This waiting time results in a loss of CPU time, so one way to solve this problem is to place an instruction that does not depend on the branch immediately after the branch instruction and execute it even when a branch occurs.
There is a non-branch priority control method that performs optimization to eliminate time loss. But if there is no such command,
Loss of CPU time is unavoidable.

With this conventional control method, if the probability of branching is low, the loss of CPU time may not be that great. When the probability of branching is high, such as in a loop-type program that is repeatedly executed, the loss of CPU time becomes large. A branch-priority control system is being considered as a solution to this problem, in which a branch destination microinstruction is always fetched after a branch instruction is fetched. However, in this case, contrary to the non-branch-priority type control method shown above, if the branch condition is not satisfied, that is, if the branch does not take place, the microinstruction following the branch instruction must be re-fetched, and the pipeline C because it is necessary to stop the flow and wait.
A loss of PU time occurs. Regarding optimization, it is similar to the example shown above.

Furthermore, in the case of a program with large variations in branching probabilities, there is almost no difference in performance no matter which method is used, and very little effect can be expected.

[0005]

[Problems to be Solved by the Invention] In the microprocessor that performs pipeline processing using the conventional microinstructions described above, when executing a loop-type conditional branch instruction, in the case of non-branch priority branch control, the CPU In the case of branch-priority branch control, there is a loss of CPU time when exiting from the loop without branching, and if the number of loops is small, even if branch-priority branch control is performed, the effect is not so much. The drawback is that it doesn't come out.

An object of the present invention is to provide a loop processing control method that can perform both branching and non-branching operations in loop processing without any loss of CPU time, and can improve performance. .

[0007]

[Means for Solving the Problems] The present invention provides a loop processing method for a microprocessor that performs pipeline processing using microinstructions. , a counter value detection mechanism that detects whether the value of a loop processing counter is a constant, a three-input adder that adds a constant and a relative address of a branch instruction and a branch destination instruction to the value of a microinstruction counter; Fetching the output result of the three-input adder as an address of the memory when a signal indicating information predicting a branch instruction for performing loop processing included in the instruction is active and an output signal of the counter value detection mechanism is active. The invention is characterized in that it has a mechanism for performing this.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a hardware diagram of an embodiment of the present invention, FIG. 2 is a flowchart of microinstruction execution of the present invention, FIG. 3 is a time chart when the instruction group of FIG. 2 is executed in the present invention, and FIG. 5 is a time chart when the instruction group shown in FIG. 2 is executed in the conventional non-branch priority control system, and FIG. 5 is a time chart when the instruction group shown in FIG. 2 is executed in the conventional branch priority control system. be.

The loop processing control system shown in FIG. 1 includes a memory 1 that stores microinstructions having information for predicting branch instructions for performing loop processing, an instruction register 2, a decoder 3, and a pipeline register 4. , a loop processing counter 12, and a counter value detection mechanism 11 that detects whether the value of this loop processing counter (not shown) is a constant.
, a microinstruction counter 6 that holds the address of the microinstruction being executed, a constant register 7 that holds a constant that is the number of processes in one loop, and a constant, a branch instruction, and a branch destination instruction in the value of the microinstruction counter 6. When the 3-input adder 8 that adds the relative address of the 3-input adder 8 and the signal indicating information for predicting a branch instruction for performing loop processing included in the microinstruction are active and the output signal of the counter value detection mechanism 11 is active, The AND gate 10 instructs to fetch the output result of the input adder 8 as an address in the memory 1.

Further, the loop processing control operation will be explained with reference to FIGS. 2 and 3. As shown in FIG. 2, each microinstruction 21-26 has a loop branch prediction bit 27. The condition for setting this bit to “1” is that the subsequent microinstruction must subtract 1 from the counter used in the loop operation (loop processing counter), and the next instruction must be such that the value of the loop processing counter is If it is not 0, the instruction will branch to an address with a smaller value than the address of the instruction, and if it is 0, the instruction will not branch and control will be transferred to the next instruction. In FIG. 2, it is assumed that the counter decrement instruction 24 and the counter conditional branch instruction 25 perform the respective operations. In this case, the loop branch prediction bit 27 of the register BX2 addition instruction 23 is set to "1". The programming method for performing basic loop processing is to load the number of times a certain process is looped into the loop processing counter 12, and each time the process is completed, the loop processing counter 12 is decremented by 1, and the number of times a certain process is looped is decremented by 1. In FIG. 2, the counter load instruction 21 returns the number of times N.
(>1) to the loop processing counter, register AX1 addition instruction 22 and register BX2 addition instruction 23.
An example of programming that performs one process N times is given. Until the Nth processing is completed, the condition of branching is satisfied if the value of the loop processing counter 12 is not 0 in instruction 25, so the branch is made to instruction 22. However, when the Nth processing is completed, the value of the loop processing counter 12 is Since the value becomes 0, the instruction 25 no longer satisfies the condition, and the loop processing ends and control shifts to execution of the register AX2 addition instruction 26.

The above operation will be explained with reference to FIGS. 1 and 3.

At timing T1 in FIG. 3, the instruction 21 is fetched from the microinstruction storage memory 1 and loaded into the instruction register 2. At timing T2, the instruction 21 is decoded by the decoder 3, and its control signal is loaded into the pipeline register 4. Instruction 22 at the same timing T2
is fetched from the microinstruction storage memory 1 and loaded into the instruction register 2. Instruction 21 at timing T3
In other words, the number of loops N is input to the loop processing counter 12.
is loaded. At this time, since the runtime loop branch prediction bit 5 receives the value of the loop branch prediction bit 27 of the instruction 21 as is and is 0, no branch operation is performed. At the same timing T3, instruction 22 is decoded and instruction 23 is fetched. At timing T4, the instruction 22 is executed, the instruction 23 is decoded, and the instruction 24 is fetched. At timing T5, the runtime loop branch prediction bit 5 becomes 1 at the same time as instruction 23 is executed, and the counter outputs 0 when the counter value of the loop processing counter is 1, and outputs 1 when the counter value is other than 1. The value detection mechanism 11 outputs 1 in response to the counter value N (>1). Therefore, the output of the AND gate 10 becomes 1, and a branch operation is performed. The branch destination address at this time is the branch destination relative address 9 of the instruction 25, the address of the microinstruction being executed, that is, the value of the microinstruction counter 6 that holds the address of the instruction 23 in this case, and the number of processes in one loop in this case. a certain constant 2
The value of constant register 7 holding
This is the value added in . Since the branch target relative address 9 is -3 here, the output of the three-input adder 8 is the address -1 of the instruction 23, that is, the address of the instruction 22. The microinstruction 22 stored at this address will be fetched at the next timing T6. Furthermore, when N=1,
Since the counter value detection mechanism 11 outputs 0, there is no branching. At the same timing T5, instruction 24 is decoded and instruction 25 is decoded.
is fetched. In this way, when branching, the branch destination instruction is fetched immediately after the branch instruction, so the CP
There is no loss in the execution time of U.

[0014] Next, the operation when the process is executed N times and the loop process ends will be explained. At timing T11 in FIG. 3, the N-th instruction 23 is executed, and at this timing, the value of the loop processing counter 12 is 1 because only (N-1) subtractions have been performed. Therefore, the output of the counter value detection mechanism 11 becomes 0, and the output of the AND gate 10 becomes 0, so no branching operation is performed. timing T
At step 12, instruction 26, which is the next instruction after branch instruction 25, is fetched. In this case as well, since the flow of the pipeline is not stopped at all, there is no loss in CPU execution time.

[0015] The timing when loop processing is performed using this microinstruction using the prior art will be explained. In Figure 4,
Although this is a non-branch priority type, the branch destination address is generated and fetched only after the branch instruction 25 is executed at timing T7, so the branch destination instruction 22 is fetched at timing T8. In this case, the CPU must stop the flow of the pipeline and wait until timing T10 when instruction 22 is executed. As shown in the figure, there is a loss of 2 cycles. If there is no branch, timing T11-T
There is no problem because the pipeline operates without stopping as in 13.

In FIG. 5, the branch priority type is shown, but at timing T5 when the branch instruction 25 is fetched, it is detected that it is a branch instruction, and the instruction 2 at the branch destination is executed regardless of whether the branch is branched or not.
2 is fetched at the next timing T6. In this case, there is no problem because the pipeline operates without stopping. However, when exiting the loop after completing N processing, the decision cannot be made unless it is time to execute instruction 25 at timing T11.
Since the subsequent instruction 26 is fetched for the first time at T1
2. The execution cycle of T13 must stop the flow and wait until instruction 26 can be executed. Therefore, there is still a loss of two cycles.

[0017]

As explained above, the present invention provides a microprocessor that performs pipeline processing using microinstructions, which includes a memory that stores microinstructions having information for predicting branch instructions for performing loop processing, and The microinstruction has a counter value detection mechanism that detects whether the value of the counter for the microinstruction is a constant, a three-input adder that adds a constant and the relative address of the branch instruction and the branch destination instruction to the value of the microinstruction counter. When the signal indicating information for predicting a branch instruction for performing loop processing is active and the output signal of the counter value detection mechanism is active,
By having a mechanism for fetching the output result of the 3-input adder as an address in the memory, both branching and non-branching operations in loop processing can be performed without CPU time loss, improving performance. effective.

[Brief explanation of drawings]

FIG. 1 is a hardware diagram of one embodiment of the present invention.

FIG. 2 is a flow diagram of microinstruction execution of the present invention.

FIG. 3 is a time chart when the instruction group of FIG. 2 is executed in the present invention.

[Figure 4] Figure 2 in the conventional non-branch priority control system
This is a time chart when executing a group of instructions.

[Fig. 5] In the conventional branch priority control system, Fig. 2
This is a time chart when executing a group of instructions.

[Explanation of symbols]

1 Memory for storing microinstructions 2 Instruction register 3 Decoder 4 Pipeline register 5 Runtime loop branch prediction bit 6 Micro instruction counter 7 Constant register 8 3-input adder 9 Branch destination relative address 10 And Gate 11 Counter value detection mechanism 12 Loop processing counter 21-26 Micro instructions

Claims (3)

[Claims] 1. A loop processing control method for a microprocessor that performs pipeline processing using microinstructions, comprising a memory that stores microinstructions having information for predicting branch instructions for performing loop processing, and a value of a loop processing counter. A counter value detection mechanism that detects whether or not is a constant, a 3-input adder that adds a constant and the relative address of the branch instruction and the branch destination instruction to the value of the microinstruction counter, and performs loop processing that the microinstruction has. When a signal indicating information for predicting a branch instruction for a branch instruction is active and an output signal of the counter value detection mechanism is active, the third
A loop processing control method comprising: a mechanism for fetching an output result of an input adder as an address in the memory. 2. In the loop processing control method according to claim 1, the condition for activating a signal indicating information for predicting a branch instruction for performing loop processing included in a microinstruction is such that the following microinstruction is This is an instruction that decrements the loop processing counter by 1. If the next instruction does not have the value of the loop processing counter 0, it will branch to an address with a smaller value than the address of that instruction, and if it is 0, it will not branch and will proceed to the next instruction. A loop processing control method characterized by an instruction that means that control is transferred to an instruction. 3. The loop processing control method according to claim 2, wherein the counter value detection mechanism activates its output signal when the value of the loop processing counter is not 1. method.