JPH0298735A - Instruction pre-fetch system - Google Patents

Abstract

PURPOSE:To reduce the number of times of a memory access operation due to a software error and to suppress contention in memory access by an execution part by stopping a pre-read function at the time of generating the software error. CONSTITUTION:A software error signal line 12 which informs the software error to a control part 3 is further added in addition to a memory part 1, an address conversion part 2, a program buffer part 4, instruction fetch signal lines 60 and 61, a data line 10, a signal line 7 representing a null status, and an initialization signal line 8. Also, the control part 3 is provided with a function to stop the pre-read function by a software error signal inputted from the software error signal line 12. Therefore, at the time of receiving the software error signal 12, the control part 3 interrupts an instruction pre-fetch operation hereafter. In such a way, it is possible to omit a meaningless instruction pre-fetch operation after recognizing the software error, and to prevent a required operation from being disturbed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a computer instruction prefetching method.

[Prior Art] Conventionally, this type of instruction prefetching method has been performed as follows.

As shown in FIG. 3, a memory section 1, an address conversion section 2,
In the instruction prefetch mechanism consisting of a control section 3' and a program buffer section 4, the control section 3 looks at the signal 7 indicating the empty status of the program buffer and issues a command using the instruction fetch signal line 61 for prefetch operation. Send the address to the address translation section 2. In addition to converting a logical address into a physical address, the address conversion unit 2 also detects soft errors such as non-existence of the table or infringement of access rights when drawing a segment table or page table. The address conversion section 2 then sends a command and address to the memory section 1 through the instruction fetch signal line 60 to instruct a prefetch operation. If there is an error, add an error flag to the command. In response, the memory section 1 sends the contents of the main memory address specified by the address conversion section 2 to the program buffer section 4 through data 49110. The program buffer section 4 indicates the empty status of the buffer to the control section 3' through a signal line 7 indicating the empty status, and sends data and flags sent through the data line 10 to a predetermined data field 41 in the program buffer section 4. and are stored in the flag field 42, respectively.

The control unit 3' executes the prefetch operation as long as there is space in the buffer.

[Problems to be Solved by the Invention] In the conventional system, preread data is successively entered into a buffer by a prefetch function that reads the next instruction before executing the instruction. In such a case, even though the soft error flag is not set, data is accumulated in the buffer one after another due to the read-ahead operation, so the contents of the read-ahead data in the buffer after the error flag is recognized are not affected by the soft error. It becomes meaningless due to the interrupt generated by the process, and there is a waste in that it is of no use. Another disadvantage is that the data prefetching operation after error flag recognition may conflict with memory access by the execution unit, resulting in a situation where the execution unit is forced to wait, which may reduce the performance of the device. .

[Means for Solving the Problems] The present invention is an instruction prefetching system having a memory section, an address conversion section, and a program buffer section, in which the control section, upon receiving a soft error signal, performs a subsequent instruction prefetching operation based on the soft error signal. Has a function to cancel. This eliminates a meaningless instruction prefetch operation after recognition of a soft error, and does not interfere with necessary operations.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the relationship of components of an instruction prefetch mechanism according to an embodiment of the present invention.

In FIG. 1, a memory section 1, an address conversion section 2, a program buffer section 4, instruction fetch signal lines 60 and 61, a data line 10, and a signal indicating the empty status! I7 and initialization signal line 8 are similar to the conventional one shown in FIG.

In the present invention, a soft error signal line 12 is added to notify the control unit 3 of software errors. Further, the control unit 3 has a function of stopping the pre-reading function in response to a soft error signal coming from the soft error signal line 12.

FIG. 2 is a diagram showing the control unit 3 in detail. When the prefetch inhibiting flip-flop 14 receives a soft error signal from the soft error signal line 12, it becomes "1" when an error occurs and inhibits the prefetch function.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

When it is clear from the signal line 7 indicating the empty status that there is empty space in the buffer, and when the prefetch inhibiting flip-flop 14 in FIG. 2 is not set,
A command and address for a prefetch operation are sent to the address converter 2 through an instruction fetch signal line 61. The address conversion unit 2 not only converts a logical address into a physical address, but also detects soft errors such as violation of access rights. The address conversion section 2 sends a command and address to the memory section 1 through the instruction fetch signal line 60 to instruct a prefetch operation, but if there is an error, it adds an error flag to the command. In response, the memory section 1 sends the contents of the main memory address specified by the address conversion section 2 to the program buffer section 4 through the data line 10.

The program buffer section 4 stores the sent data and flags in predetermined data fields 41 and flag fields 42, respectively. Also, check the buffer free status,
It is shown to the control unit 3 by f:9 line 7 indicating the availability status. Among the latest data that enters the data field 41 and flag field 42 at the same time, the error field in which the error flag is stored is checked. If it is a soft error, the soft error signal 12 is set to 1.

Then, the prefetch inhibiting flip-flop 14 in the control unit 3 in FIG. 2 is set.

Next, as shown in FIG. 2, among the three signals sent from the control unit 3 to the address conversion unit 2, a request signal 611, an address signal 612, and a command signal 613, the request signal 611 is sent to the prefetch inhibiting flip-flop 14. , the instruction prefetch function stops. The prefetch inhibit flip-flop 14 is activated when the control unit 3 initializes the program buffer 4 (no. 5 is connected to the initialization signal line 8 When sent, it is reset in conjunction with the action.

In the above embodiment, the soft error signal is sent from the program buffer section 4 to the control section 3, but it may be sent directly from the memory section 1 to the control section 3 without going through the program buffer section 4. Further, when a soft error is detected in the address conversion section 2, a software error signal may be sent directly from the address conversion section 2 to the control section 3.

[Effects of the Invention] As explained above, the present invention provides the following advantages when a soft error occurs:
By stopping the read-ahead function, it is possible to reduce the memory access operations that occur thereby, suppress contention in memory access with the execution unit, and eliminate meaningless waiting time for the execution unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus to which an instruction prefetching method according to an embodiment of the present invention is applied, FIG. 2 is a block diagram showing the detailed configuration of the control unit 3 in FIG. The figure is a block diagram showing the configuration of a conventional information processing device. 1...Memory section, 2...Address conversion section, 3...
Control unit, 4... Program buffer unit, 41... Data field, 42... Flag field, 60.
...Instruction read signal line, 61...Instruction read signal line,
7... Signal line indicating free status, 8... Initialization signal line, 9... Command word (sent to execution unit), 10... Data line, 11... Branch operation instruction signal, 12... Soft error signal line, 611... Request signal, 612
... Address signal, 613 ... Command signal, 14
...Lookahead suppression flip-flop.

Claims (1)

[Claims] 1. An instruction prefetch control unit that sequentially issues main memory read instructions for prefetching instructions depending on the free space of the program buffer that stores prefetched instruction words, and a detection means that detects software errors associated with main memory read. An instruction prefetching method, characterized in that the instruction prefetching control section suspends subsequent prefetching operations upon receiving an error signal recognized by the detection means.