JPS61168046A - Microprocessor - Google Patents

Abstract

PURPOSE:To easily discriminate an instruction being executed by means of an external bus monitoring device when a prefetch invalidation designating signal is received from the outside, by invalidating the prefetch of an instruction. CONSTITUTION:If the logic of the prefetch invalidation designating signal on a signal line 15 is '0' and the signal of an instruction prefetch designating signal line 14 is '1' in logic, the output of an AND gate 5 becomes '1' in logic and an instruction prefetch controlling section 3 prefetches an instruction, and then, the instruction is supplied to an instruction prefetching cue 4. If the prefetch invalidating signal on the signal line 15 is '1' in logic, on the other hand, the output of the AND gate 5 becomes '0' in logic. Therefore, no instruction is supplied to the instruction prefetching cue 4 and no instruction exists, since the instruction prefetch controlling section 3 does not make prefetching of any instruction even if the instruction prefetch designating signal line 14 is '1' in logic. When an instruction is requested under this condition from an instruction executing section 2 through an instruction requesting signal line 10, the instruction prefetch controlling section 3 necessarily sends reading designation to an instruction reading designating signal line 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor capable of invalidating preemptive instructions.

(Prior art) In an information processing device using a microprocessor, when testing the device's operation or evaluating a program, the input/output signals of the microprocessor are checked by a bus monitoring device and instructions being executed are monitored. is common.

(Problems to be Solved by the Invention) However, in the microprocessor that has the function of preempting instructions configured according to the prior art, it is impossible to determine which instruction is being executed from the input/output signals of the microprocessor. There was a problem.

An object of the present invention is to eliminate the above-mentioned drawbacks by stopping the function of preempting commands and invalidating the preemption command when receiving a preemption invalidation instruction signal from the outside, and to provide an external bus signal monitoring device. It is an object of the present invention to provide a microprocessor having an instruction prefetching function configured so that the instruction being executed can be easily determined.

(Means for Solving the Problems) A microprocessor according to the present invention includes an input means for receiving a prefetch invalidation instruction signal from the outside, and an instruction prefetch queue means for requesting the next instruction at the end of instruction execution. and an instruction queue control means for disabling instruction prefetching by the prefetching disabling instruction signal and stopping the supply of instructions to the instruction prefetching queue means.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, a microprocessor 1 of the present invention includes an instruction execution section 2 for executing an instruction, and an instruction request signal line 10 that is transmitted when the instruction execution section 2 finishes executing an instruction. an instruction queue control section 3 for requesting the next instruction; and an instruction queue control section 3 when an instruction exists;
The command is sent to the command execution unit 1 through the command supply signal line 11.
It consists of an instruction prefetch queue 4, an AND gate, a receiver 6, and an inverter 7.

When there is no instruction in the instruction prefetch queue 4, an instruction read instruction is sent to the instruction read instruction signal line 12, the read instruction is placed in the instruction prefetch queue 4 via the data bus signal line 13, and then the instruction is supplied. The above command is supplied to the command execution unit 1 through a signal line 11.

From the instruction prefetch queue 4, an instruction prefetch instruction signal line 14 indicating that one or more instructions can be stored is connected to AN
The command is sent to the command preemption control section 3 through the D gate 5. One input of the AND gate 6 receives a signal obtained by receiving a prefetch invalidation instruction from the outside via the signal line 15 at the receiver 6 and inverting it at the inverter. Now, the preemption invalidation instruction on the signal line 15 is logic 1.
01, the instruction prefetch instruction signal line 14 is logic 111, the output of the AND gate 6 becomes logic %11, the instruction prefetch control unit 3 prefetches the instruction, and the instruction is supplied to the instruction prefetch queue 4. Ru.

On the other hand, when the prefetch invalidation instruction on the signal line 15 is logic %11, the output of the AND gate 6 becomes logic 101. Therefore, even if the instruction prefetch instruction signal N14 is logic %11, the instruction prefetch control unit 3 Since no instructions are prefetched in this case, no instructions are supplied to the instruction prefetch queue 4 and no instructions exist. When the instruction execution unit 2 requests an instruction through the instruction request signal line 10 in such a state, the instruction prefetch control unit 3 always sends a read instruction to the instruction read instruction signal line 12. Therefore, the instruction read instruction signal line 12
By monitoring the command with an external bus monitoring device, the next command to be executed can be easily determined.

(Effects of the Invention) As described above, the present invention enables an external bus monitoring device to easily determine which command is being executed by receiving a prefetching disabling instruction signal from the outside and disabling the prefetching of the instruction. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a microprocessor according to the present invention. 1...Microprocessor 2...Instruction execution unit 3...Instruction queue control unit 4...Instruction prefetch queue 5...AND gate 6...Receiver 7...Inverters 10 to 16... Signal line

Claims (1)

[Claims] an input means for receiving a prefetch disabling instruction signal from the outside; an instruction prefetch queue means for requesting the next instruction at the end of instruction execution; and disabling the prefetching of the instruction by the prefetch disabling instruction signal. A microprocessor further comprising: instruction queue control means for stopping supply of the instructions to the instruction prefetch queue means.