JP2685727B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention can process instructions at high speed.
The present invention relates to a data processing device. [0002] 2. Description of the Related Art A conventional data processing apparatus is shown in FIG.
Interface for exchanging data with the storage device 5.
Circuit 7 and an instruction for controlling the instruction to be executedcontrolUni
And an instruction execution unit 4 for executing instructions.
ing. The instruction read from the storage device 5 is the line 73,
Command control unit via interface circuit 7 and line 11.
Command control unit 3 is transferred to
Command is analyzed and the result is sent to the instruction execution unit 4 via line 1.
Transfer via 5 The instruction execution unit 4 uses the analysis result.
As a result, various control signals are generated and these control signals are used.
Open and close each gate in the instruction execution unit 4
Perform processing such as payment and shift. Line 1 depending on the command
4, specify the address via line 74, and
Data via line 13 and line 74, or to main memory 5
Write the calculation result. The command control unit 3
The read address is the line 12, the interface circuit 7,
Instruct the storage device 5 via line 74. A series of these
By repeating the operation, the data processing device 1
The program stored in the device 5 is executed. The present data processing apparatus comprises an instruction control unit 3
And instruction execution unit 4 can operate in parallel
And pipeline control is performed. In this conventional device, the main memory 5
A cache memory 71 is provided for high-speed reading of data.
doing. Cache memory 71 is the address on line 73
The data of the corresponding entry will be searched if
Is read out and the main memory 5 is not accessed. I
Therefore, in the case of a hit, access to main memory is
Time can be omitted and high-speed data reading is possible
It works. As an example of such a device, for example, Iwanami
Course Microelectronics "Microcomputer
Hardware "Issued November 1984, No. 144-14
There is a data processor stored on page 8. However, as described above, the cache memory is provided.
In a data processing device that uses
The cache, that is, access the contents of the cache
A ban is needed. For example, the instructions stored in main memory
Or the contents of the operand data are updated to new contents.
Or instruction cache memory or opera
Logical address stored in the main cache memory
If the correspondence with the stored physical address is no longer guaranteed.
Instruction cache memory or operand cache
Command or operand data stored in the memory
Instruction or operand data whose contents are stored in main memory
If there is a discrepancy with the
It is necessary to invalidate the cache memory. After such a change in state, the following three
The possibility arises. In the first case it is stored in the instruction cache
Only the instructions that are stored do not match the instructions stored in main memory,
In the second case, the operation stored in the operand cache
Operand data in which only land data is stored in main memory
In the third case, the instruction cache and
Instructions and operand data stored in the land cache
Command and operand data stored in main memory
They are inconsistent with each other. Therefore, in order to improve the effectiveness of the cache,
Responds to these three state changes by the instruction cache and
And either operand cache or both
It is effective to disable it selectively. On the other hand, the instruction from the main memory is fetched.
Belongs to the block data including this fetch instruction in between
The next instruction is also fetched from main memory
It will be stored in the instruction cache. Therefore, the current fetched from main memory
After execution of the instruction, the data processor will issue the next instruction from main memory.
Instead of using the instruction cache inside the data processor,
Will be switched. On the other hand, the data formed on the semiconductor LSI chip is
To test the functionality of the data processor from outside the chip
Check whether the data processor executes instructions in a predetermined order.
Need to check. To this end, a data processing device
After execution of the current instruction in the instruction execution part of the
Next instruction appearing on the external bus to and from the data processor chip
Operation code (operation code)
It is necessary to check whether or not (d) is the prescribed one. On the other hand, the variable length instruction set has an immediate
Non-leading code that is
There is an instruction with a short code or an instruction with a long non-leading code.
, The position of the opcode at the beginning of the short instruction and the long instruction
It is difficult to know. Therefore, from the outside of the data processor chip
Immediately after execution of the instruction to facilitate functional testing
In addition, the operation code that is the start code of the next instruction is always stored in the main memory.
It is effective to fetch from and check on the external bus
Becomes [0015] Therefore, the object of the present invention is
Immediately after the execution of an instruction, the beginning code of the next instruction
The operation code that is a code is always fetched from the main memory
By making it possible to check on the bus,
Data processing equipment that facilitates functional testing from outside
To provide. [0016] The invention disclosed in the present application
The outline of a typical invention is as follows. Data processing used with main memory (5)
A device that generates a command address (l31)
Instruction address generator (32), a plurality of instruction addresses, and
Stores multiple instructions corresponding to multiple instruction addresses
The instruction cache memory (31) and the instruction address
In the instruction address (l31) generated from the raw part (32)
Therefore, the main memory (5) or the instruction cache memory is
Decode the instruction read from Mori (31) and
The resulting instruction decoder (35) and the instruction decoder (3
The instruction is executed according to the above decoding result of 5), and the instruction is executed.
Instruction execution that outputs the next instruction request signal (141) at the end of the line
The line section (4) and an external purge signal from outside the data processing device.
Signal (61) is being supplied, the next instruction request signal
Outputs a purge command signal (162) in response to (141)
And a purge control circuit (6) configured to
Then, according to the purge command signal (162), the command key
It is specially designed to invalidate the contents of the cache memory (31).
Sign. [0018] In this typical invention, the start of the instruction is
In the instruction execution unit (4) using the pecode and the non-leading code
When the instruction execution is completed, the instruction execution unit (4) requests the next instruction.
The signal (141) is output. Therefore, from the outside
Signal (l61) is continuously supplied to the purge control circuit (6).
While being supplied, it responds to the next command request signal (l41).
In response, the purge command signal (162) indicates that the purge control circuit
It is output from (6). Then, the operation code at the beginning of the next instruction and the non-preceding
Including the initial code, it is stored in the instruction cache memory (31).
Access to the contents of the stored block data is prohibited
As a result, the data processing device is connected to the external bus (l23, l2
From the main memory (5) via 4)
The new block data, including the
To switch. Especially, the first operation of the next instruction from the main memory (5)
The code fetch timing is the purge control circuit (6)
Synchronized with the purge command signal (162) output from
Non-leading code fetch instruction of the next instruction from memory (5)
Purging command signal (162) or next command in imming
The request signal (141) is not output. Therefore, it is fetched from the main memory (5).
The first operation code of the next command is also the purge command signal (162)
Or the external bus in synchronization with the next command request signal (l41)
Can be easily checked on (l23, l24)
It works. Other objects and features of the present invention are as follows.
It will be clear from the examples. [0022] Embodiments of the present invention will be described in detail with reference to the drawings.
You. In the following description, first, the data processing of this embodiment is performed.
The instructions used for the processing device are explained, and then the device configuration is explained.
The explanation will be given and finally the operation will be explained. 1) Instruction   Basic instruction format FIG. 2 shows the instruction format of this embodiment. The instruction is an operation type (bits 15 to 1).
2), an operation that specifies the addressing mode, etc.
Data (bits 11 to 0), data for address calculation
And has an extension of 32 bits in length. Depending on the type of addressing mode specified
In some cases, no extension part is involved. Bit 11 of the operation word
9 is the data used as one operand of the operation
Indicates the number of the data register to hold. The other operan
Mode depends on bits 5 to 0 of the operation word.
Is specified. That is, bits 2 to 0 are
Indicates the number of the register that should be referred to in order to obtain the perland.
However, bits 5 to 3 indicate the addressing mode.
You. In this embodiment, as described later,
It has eight data registers and eight address registers.
You. Bit pattern of bits 5 to 3 and add
The correspondence of the lessing mode is shown in FIG.
You. In the figure, "Data register" mode and
The “Dress Register” mode is
The contents of the data register and address register are
It is a land mode. Address register indirect
The mode is such that the contents of the specified address register
This mode is used as a memory address of a memory.
"Post-increment" mode and "pre-decremen"
Mode is basically the address register indirect mode
Same as, but for storing or fetching operands
Immediately before and immediately before, respectively, the contents of the address register
The difference is +1 and -1 respectively. Therefore, this model
The operand is the operand data stored in a series of addresses.
Data will be read out one after another and calculated. [Address register with displacement]
"Indirect" mode is the contents of the specified address register.
The value obtained by adding the contents of the extension to the memory address of the operand.
This is the mode used as a
Mode with program counter ”mode
Add the contents of the extension to the dress (contents of the program counter)
Use the added value as the memory address of the operand
Mode. And the "absolute address" mode is
Is used as is as the memory address of the operand.
This is the mode to use. Stack instruction in basic instruction Since the current programs are written in high-level languages,
It has a stack as a data structure. Especially Saburu
When using Chin, variables used in the main routine,
Variables used in subroutines are grouped as separate groups.
It is necessary to store it in the memory. This group with a frame
Say. The stack is a part of the main memory and the stack port.
It consists of an interface. What is the stack pointer?
Address for storing in main memory one after another from address
This is a register that stores the memory. When calling a subroutine,
Move the value of the pointer to the frame pointer. Flame Po
The interface stores the highest address of one frame.
Register. In this embodiment, 8 addresses
One of the registers is the stack pointer and the other is
Is used as a frame pointer. The stack is accessed by 2 bits of the instruction.
Frame pointer or stack point at ~ 0 bit
Addressing mode of 5 to 3 bit instructions.
"Address register indirect", "Post ink"
"Liment", "Pre-decrement" or "Display"
Indirect address register with statement "
Is performed using. Of access to these stacks
These modes are collectively called stack access mode.
Will be called a stack instruction. As described above, in this apparatus, the stack point is
Since the data is set in advance in one register,
Programs that do not specify registers as stack pointers
Performance may decrease. Control command Further, in the data processing device of this embodiment, the general instruction
With control instructions having a different format. In this embodiment, a purge (PURGE) command and
Yes, it is an instruction issued exclusively by this data processing device.
You. However, it is read from the main memory together with the above basic instruction.
In some cases. The function of this command is built into the data processing device.
Invalidate associative memory 21, 31 or 36, 37, 38
It is to be. The reason why this instruction exists is as follows.
You. The data processing device 1 is provided in one chip.
It is stored in. With the address created in this chip
It is to access the outside. However, the current system
In the stem, the address created in the chip and the external
The address actually assigned to the device may differ.
The logical address of the address created in the data processor.
Address, the logical address of the address actually given to the external device
Sometimes called a dress. Generally, logical address and physical
Translation with an address is a special function called an address translation mechanism.
The software can be used as an on-chip output unit of a data processing device, or
Is provided externally. For example, Ibid. No. 14
It is shown on page 5. The data processing device of this embodiment will be described later.
Only refer to the logical address in the chip
So, configure a system to attach an address translation mechanism to the outside
Address, the main memory address referenced by the physical address
Address of the associative memory in the chip that is referenced by the address and logical address.
The dress may be different. In particular, the address space on the main memory is
When switching to the less space, the associative memory in the data processing device 1 is
The address of the information held in memory and the actual main memory
Correspondence with the address cannot be guaranteed. This contradiction is detected by the data processing device in advance.
To disable the internal associative memory
You can solve more. Therefore, the address translation mechanism is used in the system.
If the address space is provided in the
The switching signal is asserted by asserting the purge signal.
I need to teach Oki. In this data processor, the purge control circuit
As described later in the section, the purge message from the address translator is
Issue a purge command based on the number and the purge command
Have been. The above is the reason for providing the purge command. Next, referring to FIG. 3A, the purge command flow
The format will be described. In purge command, contents should be invalidated
Purge code (PURGE COD
According to E). The correspondence is shown in FIG. Purge coat
When bits 7 and 6 of the command are "00", they are not invalidated.
When the purge code is "01000000", the data
Disables the system's associative memory. Data-based associative memory
Corresponds to the associative memory 21 described later. When the purge code is "10000000"
Command, the associative memory of the instruction system is disabled. Command-related association
As the memory, associative memories 31, 36, 37 described later are used.
And 38 are applicable. If the purge code is "11111111"
Then all internal associative memory is disabled. 2) Next, the structure of this apparatus will be described in detail.
I do. In FIG. 4, reference numeral 1 is a data processor,
An interface unit for exchanging data with
Knit 2 and the data from the interface unit
An instruction control unit 3 for analysis, and an instruction control unit
The instruction execution unit for executing the analysis instruction from the unit.
Made of knit. 4 bytes per access from main memory 5
(32-bit) data can be read. The instruction execution unit 4 is required for instruction execution.
Is the data stored in the main memory via the interface unit 2?
Read from Instruction control unit 3 and instruction execution unit 4
And can be operated in parallel and pipeline control is performed. Each circuit will be described below. Command control unit 3 The address generation circuit 32 uses the prefetch address update signal.
No. via line l34 and the branch destination address on line l3
3 via the prefetch address and
H request is output to line l31 and executed by instruction execution unit 4
It is a circuit for outputting the address of the inside instruction to the line l32. FIG. 5 shows the details of the address generation circuit 32.
You. Reference numeral 323 is a selection circuit, which is normally a register 32.
Select the prefetch address from 1 and select the branch address
Is given via line 1332.
Select the space. Reference numeral 325 denotes an adder, which is supplied from the selection circuit 323.
The number given from the constant generation circuit 324 to the instruction address
Is added. The number generated by the constant generation circuit 324 is
Corresponds to the length of the command to be issued. Register 321 receives the signal from line l342.
Thus, the output of the adder 325 is latched. Accordingly
Register 321 is updated each time a signal is received from line l34.
New, prefetch address on line l312 in line l31
Will be output. The update signal of line l34 is
Output as a fetch request from the line 1311 of the line l31
You. Reference numeral 326 is a selection circuit, which is normally an adder 329.
Output from the branch address via line l332
The branch address is selected. cash register
The star 327 transfers the instruction address from the selection circuit 323.
Output the instruction address on line l32. The adder 329 receives the instruction address on the line l32.
The number given by the constant generation circuit 328 is added to the interval.
The number generated by the constant generation circuit 328 is the number of commands to be executed.
Corresponds to the length of the decree. The associative memory 31 stores the instruction address and its
Stores the instruction corresponding to the instruction address in the same entry
It is a memory to keep. The structure of the associative memory 31 is shown in FIG. The entire
Consists of 64 entries, each entry is a search field
Mode 311, valid bit 312 and data field 3
13. The search field is given via line l312.
This is a field for storing the instruction address to be sent. Effectiveness
The bits are the data stored in the data field 313.
This is a bit indicating whether or not it is valid. Data field 31
3 for storing the instructions given via line l35
The field has a length of 4 bytes (32 bits). The search to the associative memory 31 is performed via the line l31.
The instruction address given by Instruction address is
Applicable if present and valid bit set
The instruction stored in the data field of the entry is
Output to 52. Also, a fetch end signal is also sent to the line l351.
Output. If there is a hit, the signal on the line 126 is turned on.
The access to the main memory 5 is prohibited by the selection circuit 22.
You. The associative memory 31 is updated from the line l31.
There is no entry that stores the instruction address, and it is valid.
This is done when the bit is reset. Main memory 5
When the fetch end signal of line l351 from is turned on
Is the read command input via line l35 and is it line l31?
The oldest rewritten ent
Will be written to Validity of newly rewritten entry
The set 312 is set. The associative memory 31 is provided by executing the purge command.
Will be invalidated. Command when purge command is executed
Effective by the signal line (not shown) from the execution unit 4
Bit 312 is reset for all entries. First-in, first-out memo
When the fetch end signal of the line l351 is turned on,
It stores multiple instructions given via line l352.
Memory, the earliest written instruction
It is a memory that can be read easily. The control circuit 33 has a free memory 34.
In this case, the fetch end signal on the line l351 is turned off.
In order to read the next instruction, through line l34
Address update circuit 32 to the prefetch address update signal.
It is a circuit for transmitting the signal. The decoder 35 receives the instruction from the memory 34.
Parse and convert to microprogram instruction address
Output to line l36. The associative memories 36, 37 and 38 are
Branch with a buffer that works to suppress disturbances in the plan
The original address, branch destination instruction, and decode result are the same
Remember it. The structure of the associative memories 36, 37 and 38 is shown in FIG.
Shown in It consists of 4 entries in total, and each entry is
Search field 361, valid bit 362 and data frame
It is composed of fields 363, 37 and 38. Search field 361 is accessed via line l32.
This field stores the given branch source address.
You. Valid bit field 362 is data field 3
Indicates whether the data stored in 63, 37, 38 is valid
It's a bit. Part of the data field 363 is a line
A file for storing the next branch destination instruction given via 138.
Field. The other part 38 of the data field is a line
Stores the branch destination instruction itself given via I38.
Field. The other part 37 of the data field is
The microinstruction address provided via line 136
This is the field to be paid. In addition, in the overall configuration diagram of FIG.
The associative memory 36 includes an address generation circuit 32 and a decoder 35.
And the associative memory 37 is provided between the decoder 35 and the instruction.
It is provided between the execution units 4. The reason is
The location of the source of various information stored in the memory 36
The position of the source of the information stored in the memory 37 is different.
Because it is. In this way, the associative memories 36, 37
The distance between the information source and the associative memory
Chips that can be separated from each other by wiring between them
The occupied area can be reduced. Associative memories 36 and 37 are lines
It is connected to the associative memory 36.
The address of the selected entry is the associative memory 37, 38
To the same entry, and both entries are selected.
Will be lost. The associative memories 36, 37 and 38 are searched for
Performed at the branch source address provided via line l32.
The branch source address exists, and the valid bit 362 is set.
If yes, the data field 36 of the corresponding entry
The information stored in 3, 37, and 38 are the lines l35 and l, respectively.
39 and line 140. The associative memories 36, 37 and 38 are updated by the line
There is an entry that stores the branch source address from l32.
Not present and valid bit 362 is reset
To be done. At this time, branch source address and branch destination address
No, branch destination instruction decode result Branch destination next instruction
Is also written in the old rewritten entry. Newly rewritten
The valid bit 362 of the obtained entry is set. The associative memories 36, 37, 37 have barge life.
It is invalidated when the decree is executed. Barge instruction is executed
Signal line from the instruction execution unit 4 (not shown).
The valid bit 362 is reset for all entries.
Is set. The selection circuit 47 is provided via line l45.
When the branch success signal is received, the line l39 is selected.
You. When the branch failure signal is received, the line l36 is selected.
You. The selection circuit 46 is supplied via line l45.
When the branch success signal is received, the line l38 is selected.
You. When the branch failure signal is received, the line 140 is selected.
You. The register 38 is used as a register from the decoder 37.
The black instruction address is the next instruction given via line l41.
Latch by command request signal. And the latched
The black instruction address is sent to the instruction execution unit. Was
However, the barge command signal and the line l41 are sent via the line l62.
When the next command request signal of
Not via their microinstruction address, but via line l63
Latch the purge command. Register 40 sends the next instruction via line l41.
When the request signal is received, the signal from the selection circuit 46 is changed to
To switch. Instruction execution unit 4 The ROM 41 is arranged on the time axis given via the line 140.
The address of each microinstruction in the sequence of microinstructions
Control sequentially stored and stored at the corresponding address
The information is sequentially read and output on the line 142. The processing circuit 45 outputs the control information on the line l42.
Based on the calculation. Get operand data from main memory
The address for output is output via line 133 and read.
Input operand data via line l43. Another line
The command itself is input via l44. Life on line l41
When the command execution is completed, the next command request signal is output.
If the branch is successful when the branch instruction is executed, the line l
45 Branch success signal, branch failure if branch failed
Output a signal. FIG. 8 is a diagram showing the structure of the processing circuit 45.
You.linel46, l47 and l48 are internal data buses
It is. The register group 452 includes eight data registers, eight
It consists of a book address register. Register group 452 is a line
l422 specifies one or two registers,
Read data to l46, l47 or from bus l48
Data is read. Stack of 8 address registers
Includes pointer and frame pointer. Stack pointer
Is stored in the main memory, so each time it is used
The content is subtracted and incremented by 1 each time it is used for reading
I do. Reference numeral 453 is an arithmetic circuit, which is a bus l46, l
The signal on 47 is added and removed based on the instruction from line l423.
Performs calculations, etc., and outputs the calculation results to the internal data bus l48
I do. Further, the arithmetic circuit 453 controls for one instruction.
Computation ends after all information is input from line l42
Then, the next command request signal is output to l41. When the branch instruction is executed, the condition
Code C. The condition specified by the branch instruction is satisfied by referring to C
If the branch success signal is satisfied, if not satisfied
A branch failure signal is output to the line I45. When the purge command is executed, first, the par
Output Jiclear signal on line l49, indicated by purge code
The signal line that does not show the effective bit of the associative memory
Reset via. Reference numeral 454 is a data designating circuit, which
Increment mode and pre-decrement mode
In this case, the operand size (life
By order, 1 byte, 2 bytes, 4 bytes are specified
The lower 2 bits of the address on line 133 are
Of the 32-bit data on line 144 encoded, the operation
This is the data required as a land and the operand size
The data having the length is interfaced through the line 150.
In step S451. Interface 451 is on line l421
The fetch end signal on line l431 is turned on based on the control information.
Data from the time line l432 to the internal data bus l4
7 and l48, fetch request signal on line l431
Turn off. In addition, the data from the internal data buses l47 and l48
Data to line l432 and fetch request signal to line l43
Output to 1. Bit of data to read on line l50
When the position and length are specified, the data based on that is specified.
Cut out. The associative memory 21 stores operand data.
Operand buffer 24 and bytes to remember
From the line buffer 25 for storing data
You. The structure of the operand buffer 24 is shown in FIG.
You. 22 entries in total, each entry is a search
Field 241, valid bit 242 and data file
Field 243. The search field is given via line 133.
Is stored to store the address of the operand data
It is Ludo. The valid bit 242 is stored in the data field.
A bit that indicates whether the stored operand data is valid
is there. The data field 243 is provided via line 121.
Field for storing the obtained operand data
It is. The update / search of the operand buffer 24 is performed by
The following two types based on the instructions to be executed by the instruction execution unit 4
Is controlled. (A) Stack accessMode,life
The contents of the address register specified by
When it is output to the line l332 as the address of the data
Is the operand buffer 24
Responded to search. Operand data address exists
And the valid bit 242 is set,
Opera stored in the data field of this entry
Band data is output on line l432. Line l43 at this time
The fetch end signal of 1 is turned on. or,hitDid
To the main memory 5 by the selection circuit 22 via the line 125.
Access is prohibited. In addition, as a result of the search
Operand data read from main memory 5
Is input via line l21 and the operan from line l33
The oldest rewritten along with the addressentryWrite to
I will. The valid bit 242 of the newly rewritten entry is
Set. (B) The instruction execution result is obtained and the line l43 is displayed.
The execution result is output, and the execution result is stored in the line l332.
When the address on the main memory 5 to be output is output,
The pellet buffer 24 is searched by that address. So
Address exists and valid bit 242 is set.
Data field of the corresponding entry,
Is rewritten with the execution result on the line l332. Effective Bit
242 is set. Even if you hit at this time,
Nothing is output to the line 125. Therefore, the selection circuit 2
2 is not prohibited from accessing the main memory 5. Also, of search
As a result, if there is a mishit, the operand buffer
Do not rewrite the data. Operanes other than the above (a) and (b)
The search buffer is not rewritten. In the case of (a), the stack is updated and the stack is updated.
This is a case of reading data from the memory. (A)
The operand buffer is updated and rewritten when
The operand buffer is an internal memory for storing stack data.
It can be said that it is Mori. In the case of (b), depending on the instruction, the stack
May be directly addressed and data rewriting may occur.
This is a measure to deal with this. The operand buffer 24 receives the purge signal.
More disabled. When the purge signal is input,
All the valid bits 242 are reset. The line buffer 25 is a post-increment.
Operand mode and pre-decrement mode
When reading byte data of the length specified by the size
4 bytes of consecutive addresses read from main memory 5 at once
Is stored, and successive operand add
This is a memory for speeding up access to addresses. The structure of the line buffer 25 is shown in FIG.
You. The line buffer 25 has eight address registers.
6 excluding stack pointer and frame pointer
It has one-to-one correspondence with the register of the book. did
Therefore, it should consist of 6 entries in total.
become. Each entry has a search field 251, 4
One valid bit 252-255 and four data bits
Fields 256 to 259. Effective bit 25
2 to 255 are data fields 256 to 259, respectively.
Corresponding, and the data of the corresponding data field respectively
Indicates whether is valid. 4 data files of 1 entry
In the field, there are consecutive records read from the main memory 5 at one time.
The 4-byte data of the dress is stored respectively. The line buffer 25 is searched for between addresses.
Of the contact modes, post increment and
ClementWhen in modeTo do. Post increment and pre-decreme
In addition mode, the value of the address register is incremented by 1 or
Subtract the data stored in consecutive addresses
This is a mode in which read processing is performed individually. In this mode, the first data is read
When you search the line buffer, the corresponding entry still exists.
It usually does not exist. Therefore, the line 1 to the main memory 5
The address is sent via 33. At this time, main memory 5
4 bytes of data are read at a time from the
To the address register specified by the instruction in this mode
Written to the corresponding entry. At the same time, the data is selected
It is output from the circuit 22 to the line 143. At this time, a 32-bit data is input to the line l43.
Data is sent, but the data required as an operand is
It is data of the number of bytes specified by the land size. This
Data is cut out by the data designating circuit 454,
And interface 451. When the processing of the first data is completed,
The content of the address register specified by the instruction is incremented by 1, or
Decreases and the next data is read. At this time on line 133
The output address is continuous with the previously output address.
Since it is an address, it was stored in the line buffer first.
The probability that the corresponding address exists in the data is extremely high.
No. If the search results in a hit, the main memory 5
The data of 4 bytes of the corresponding entry is not read.
Output to line l43. Also, output to line l25,
The selection circuit 22 is prohibited from accessing the main memory 5. In the instruction execution unit 4, the instruction execution
The line result is obtained, and the execution result is output to line l43.
Address in main memory 5 where the execution result should be stored in l33
Is output, the line buffer 25
Responded to search. The address exists and is valid
If the entry is set, the data
The field data is rewritten to the execution result on line l33.
You. The valid bit is set. If you hit
However, nothing is output to the line 125. Therefore, select times
The path 22 is not prohibited from accessing the main memory 5. Also, the inspection
If the result of the search is a mishit, the line buffer 2
No data rewriting of 5 is performed. This operation is also an operand
Like the buffer, the contents of the line buffer are stored in the main memory 5
This is a procedure to keep it in agreement with the content. As described above, the line buffer 25 is used.
Post-increment predecremen by
In the main mode, it is recorded once every 4 bytes on average.
You can access the memory and read at high speed.
It works. In particular, the operand size is specified as 1 byte
If four operand data are processed,
It only needs to access the main memory once. Interface unit 2 The selection circuit 22 receives the instruction add provided via the line l31.
Operand or operand data given via line 133
One of the addresses is sent to the main memory 5 via the line 123.
It is what is sent. FIG. 11 shows a block diagram of the selection circuit. Line l3
11 is a read request signal and line 1312 is an address signal
l31. Line l331 is a fetch request signal, line
An address signal l332 constitutes the line l33. AND
Circuit 222 is the logic of the signals on lines 1311 and 126.
Command control when associative memory 31 is hit
Outputs a signal to prohibit access to main memory 5 from circuit 3
I do. AND circuit 226 is on line l331 and line l25
When the logical product of the signals of
Access the main memory 5 from the instruction execution unit 4
Output the prohibition signal. The AND circuits 223 and 227 are used to execute the instruction execution.
Time to prioritize access requests from line unit 4
Road. With AND circuits 223 and 227,
Either flop 224 or 228
Is set. The selector 221 is a flip-flop 224.
Alternatively, one of the address signals selected by 228
This is a circuit for outputting to l232. The OR circuit 230 includes the flip-flop 22.
Obtain the logical sum of the outputs of 4, 228, and output the fetch request signal.
This is a circuit for outputting to the line 1231. Lines l231 and l
The line 232 is constituted by 232. Data from the main memory 5 is sent via the line l24.
can get. The line l241 indicates a fetch end (read end) signal.
It is the issue and informs that the data is ready. Line l
The data itself is input on 242. The AND circuits 225 and 229 are connected to the line 12
It is the instruction control unit 3 that issued the fetch request to 31.
Whether there is an instruction execution unit 4 or not, and issues a request.
End the fetch to the line (l351 or l211)
The completion signal informs that the data is ready. life
The instruction control unit 3 and the instruction execution unit 4 are respectively connected to the line l3.
Look at l351 in 5 or l211 in line l21
Check whether there was a response to the
The request will be turned off. Purge control circuit 6 The purge control circuit 6 inputs the purge signal from the line l61.
Then, the purge command signal is output to the line l62, and the line l6
The purge command is output to 3. FIG. 12 shows a configuration diagram of the purge control circuit 6.
You. When the purge signal is input from the line l61, A
The D terminal of the flip-flop 65 is connected via the ND circuit 64.
turn it high. The next command request signal is input via line l41.
When input, latch the D terminal input at that timing
Then, the purge command signal on line 162 is turned on. Accordingly
And stored the purge command in advance via line 164.
The contents of register 66 are transferred to register 38 via line l63.
Latch (Fig. 1). Also at this time, flip flip
62 is also set. Purge by instruction execution unit 4
When the instruction is executed, the purge clear signal is first sent to the line l49.
Is output to This resets the flip-flop 62
Cut. The delay circuit 63 and the AND circuit 64
The D input of the up-flop 65 is set to Low. Purge command
Is completed, the next command request signal on line l41 turns on.
I do. This sets flip-flop 62
The lip flop 65 is reset. Flip-flop
The output of the amplifier 62 is input to the delay circuit 63. During this time
In the register 38, the instruction decoding result from the selection circuit 47 is
Will be latched. After that, the delay circuit 63
The output goes high. At this time the line l61 is still purged
When outputting a signal, the flip-flop 65
The D input is high. Therefore, the next instruction is required.
When the request signal is input, the purge command signal is again sent to the line 162.
Is output. [0120]When the purge command signal is output, the association memo
Access to the contents of the block data stored in
Access to the external bus 12 because access is prohibited.
From the main memory 5 via 3,124, the first opeco of the next instruction
Code and new block data including non-leading code.
You will have to Therefore, the running program
Which of the instructions in the chip is being executed on the chip
You can observe from. In addition,The lines l61 and l63 show
An address conversion circuit not shown can be connected. The address conversion circuit, as described above,
Addresses used inside the processor and devices outside the data processor
Used for systems with different addresses
It is. In this embodiment, the purge command is reset.
So that it can be alternately latched by the transistor 38
This is a normal instruction to the data processor.
Run the program step by step to check the program.
It is. 3) Description of operation Next, the operation of the data processing device will be described. FIG. 13 shows an example executed in this data processing device.
An example of an instruction sequence to be executed is shown below. Instructions are stored in main memory from No. 1 to No. 11.
Are stored in consecutive addresses. Instructions No. 1 and No. 2 have stack pointers
Data that specifies the data of the indicated address with each instruction
This is an instruction to store in a register. Command No. 3 is command No. 1 and command No. 2, respectively.
Adds the contents of the registers that store the data and returns the result
Is stored in one of the data registers. Command No. 4 is the data record specified by the command.
Register contents in the address register specified by the instruction
It is an instruction stored at the instructed address. Instruction No. 5 is the address specified by the instruction.
Command to jump to the instruction at the address specified by the register
It is a decree. In the case of this example, jump to instruction No. 10.
I am supposed to. Command No. 10 is the two specified by the command.
This is an instruction to add the contents of the data register. When the above instruction sequence is executed, the time check
The chart is shown in FIG. Cycle T₁ The address generation circuit 32 adds the instruction No. 1 to the line l31.
Output the response. The associative memory 31 searches for the address
However, if there is no hit, read the data into main memory 5.
go to. The data read from the main memory 5 is the associative memory 31.
It is also stored in the memory 34. Cycle T_Two Since the memory 34 has a free space, the address generation circuit 32
The address of instruction No. 2 is output. The associative memory 31 is
Similar to the previous instruction No. 1, the address is searched and hit.
If not, the data from the main memory 5 is written. Read again
The stored data is stored in the memory 34. The decoder 35 uses the instruction N from the memory 34.
o.1 is analyzed and the analysis result is stored in the register 38. The instruction No. 1 matrix stored in the register 38
The execution of the black instruction sequence is started in the instruction execution unit 4.
Be started. At execution time, it is stored in the data register.
The address of the operand data for saving to line l33
However, since this instruction is a stack instruction, the associative memory
There is a high possibility that the corresponding entry exists in 24. I
Therefore, the instruction No. 2 is read from the instruction control unit 3.
Request and operand data from the instruction execution unit 4
Read requests are less likely to conflict with each other. On the contrary, the instruction No. 2 is sent to the associative memory 31.
If it exists, the operand data is stored in the associative memory 24.
And the command control unit 3 regardless of whether
Read requests to the main memory 5 with the instruction execution unit 4 compete
Do not match. Cycle T_Three The instruction No. 3 is stored in the main memory 5 in the same manner as the instructions No. 1 and 2.
It is read and stored in the memory 34. In the decoder 35, the solution of the instruction No. 2 is solved.
Analysis is performed. In the instruction execution unit 4, the instruction No. 1 is executed.
The line ends, and the execution of the instruction No. 2 starts. The instruction No. 2 is a stack like the instruction No. 1.
This is an instruction, the associative memory 24 is searched, and
When reading, the line to read the operand data to the main memory 5
Good. In this case, the instruction control unit 3 and the instruction execution unit
The competition with Knit 4 is the same as in the case of instruction No.1.
is there. Cycle T_Four The instruction No. 4 is read from the main memory 5 in the same manner as the instruction No. 1 etc.
It is output and stored in the memory 34. In the decoder 35, the solution of the instruction No. 3 is solved.
Analysis is performed. In the instruction execution unit 4, the instruction No. 2 is executed.
The line ends, and the execution of instruction No. 3 starts. The instruction No. 3 is the data in the instruction execution unit 4.
Main memory because it is an instruction that operates using a data register
The operand data to 5 is never read. Cycle T_Five The instruction No. 5 is read from the main memory 5 in the same manner as the instruction No. 1.
And stored in the memory 34. In the decoder 35, the solution of the instruction No. 4 is solved.
Analysis is performed. In the instruction execution unit 4, the instruction No. 3 is executed.
The line ends and the execution of the instruction No. 4 starts. Instruction No. 4 is a data register in the main memory.
This is an instruction to write data. Write data to line l33
The remaining address is output. Operand buffer 24
Is whether or not this address rewrites the contents of the stack.
Is checked, and if it is to be rewritten, the operand
The contents of the buffer are rewritten to the data on the line l43. Line l
The data on 43 is sent to the main memory 5. Cycle T₆ The instruction No. 6 is read from the main memory 5 in the same manner as the instruction No. 1.
And stored in the memory 34. In the decoder 35, the solution of the instruction No. 5 is solved.
Analysis is performed. On the other hand, the address generation circuit 36 uses the line l32
Address of instruction No. 5 being executed by the instruction execution unit
Output. The associative memory 36 is searched at the address.
It is. If there is no corresponding entry, the association
There is no output from the memories 37 and 38. The corresponding entry is
If it exists, the time chart after (10) described later.
Becomes In the instruction execution unit 4, the instruction No. 4 is executed.
The line ends and the execution of the instruction No. 5 starts. Cycle T₇ The instruction No. 7 is read from the main memory 5 in the same manner as the instruction No. 1.
And stored in the memory 34. In the decoder 35, the solution of the instruction No. 6 is solved.
Analysis is performed. In the instruction execution unit 4, the instruction No. 10
The address is output on the line 133. Further, the instruction execution unit 4 succeeds in branching.
Therefore, the contents of the memory 34 are cleared. Cycle T₈ The address generation circuit 32 receives the instruction No. 10 on the line 133.
Take in the address, and send the address of instruction No. 10 to line l31
Is output. Command No. 10 is command No. 10. Same as 1
And stored in the memory 34. In the decoder 35, of the memory 34
Y is cycle T₇What has been cleared in
There isn't. Instruction execution unit 4 should also execute
Do nothing because the instruction has not been decoded. The command No. 10 itself is stored in the associative memory 38.
Is done. Cycle T₉ The instruction No. 11 is read from the main memory 5 in the same manner as the instruction No. 1.
It is detected and stored in the memory 34. In the decoder 35, the solution of the instruction No. 10
Analysis is performed. The analysis result is stored in the associative memory 37.
It is. The instruction No. 11 itself is also stored in the associative memory 36.
It is. At this time, the associative memory 36 stores the instruction execution unit.
The address of the last executed instruction No. 5 in 4 is stored.
You. Therefore, the branch source address,
Branch destination instruction, branch destination instruction analysis result Branch destination next instruction is stored
Will be. In the instruction execution unit 4, the instruction No.
After the analysis of 10 is completed, execution is performed. (10) Cycle T₇ Cycle T₆In the
When there are birds, associative message is immediately generated as shown in FIG.
Analysis result of instruction No. 10 from instructions 37 and 38
It is read by itself. Further, the instruction No. is sent from the associative memory 36.
11 is also read and stored in the memory 34. Cycle T₇Address generation circuit
32 is an instruction No. 10 instruction given via the line 133.
Add the length of commands No.10 and No.11 to the dress
The address of the instruction No. 12 is calculated and output to the line l31.
You. The read instruction No. 12 is stored in the memory 34.
You. In the decoder 35, the instruction No. 11
Analysis is being done. The instruction execution unit 4 executes the instruction No. 5.
Immediately after the end, it is read from the associative memories 37 and 38.
The executed instruction No. 10 is executed. [0169] As described above, according to the present invention, instruction control
Assuming that the unit and the instruction execution unit operate in parallel
Also, it is less likely that contention for reading data to main memory will occur.
Therefore, instruction processing can be speeded up.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional data processing device. FIG. 2 is a diagram showing an instruction format used in an embodiment of the present invention. FIG. 3 is a diagram showing a format of a special instruction used in the embodiment. FIG. 4 is a configuration diagram of an embodiment. FIG. 5 is a configuration diagram of an address generation circuit 32 used in the embodiment. FIG. 6 is a configuration diagram of an associative memory 31 used in the embodiment. FIG. 7 is a configuration diagram of associative memories 36, 37, and 38 used in the embodiment. FIG. 8 is a configuration diagram of a processing circuit 35 used in the embodiment. FIG. 9 is a configuration diagram of an operand buffer 24 used in the embodiment. FIG. 10 is a configuration diagram of a line buffer used in the embodiment. FIG. 11 is a configuration diagram of a selection circuit 21 used in the embodiment. FIG. 12 is a configuration diagram of a purge control circuit 6 used in the embodiment. FIG. 13 is a diagram showing an instruction sequence executed by the apparatus of the embodiment. FIG. 14 is a time chart when the instruction sequence shown in FIG. 13 is executed by the apparatus of the embodiment. [Explanation of Codes] 1 ... Data processing device, 2 ... Interface unit,
3. Command control unit, 4 command execution unit, 5 main memory, 6 purge control circuit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kunio Uchiyama               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd. (72) Inventor Ikuya Kawasaki               1450 Josui Honcho, Kodaira City, Tokyo Stock Association               Inside the Musashi Plant of Hitachi, Ltd. (72) Makoto Hanawa, the inventor               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd.

Claims (1)

(57) [Claims] A data processing device used together with a main memory, comprising: an instruction address generation unit for generating an instruction address; an instruction cache memory for storing a plurality of instruction addresses and a plurality of instructions corresponding to the plurality of instruction addresses; An instruction decoder which decodes an instruction read from the main memory or the instruction cache memory in accordance with an instruction address generated from an instruction address generating unit and produces a decoding result; and executes the instruction according to the decoding result of the instruction decoder, An instruction execution unit that outputs a next instruction request signal at the end of execution of an instruction, and a purge instruction signal that is output in response to the next instruction request signal while an external purge signal is being supplied from outside the data processing device. And a purge control circuit configured in accordance with the purge command signal. The data processing apparatus characterized by allowed to disable. 2. 2. The data processing device according to claim 1, wherein the data processing device is a microprocessor formed in an LSI chip, and the instruction cache memory is formed in the chip. 3. The data processing device according to claim 1 or 2, wherein the instruction cache memory is an associative memory. 4. 4. The data processing apparatus according to claim 1, further comprising means for outputting the purge command signal each time one command is executed.