JPS63124135A - Data processor - Google Patents

Abstract

PURPOSE:To effectively increase the processing speed of a data processor by obtaining a jumping destination address with the address of an instruction train carried out before an instruction train under analysis as an index and fetching an instruction train starting at said jumping destination address. CONSTITUTION:A branch instruction undergone branch estimation is carried out by an instruction executing part 3 and a jumping destination address is fixed. Then a comparator 5 compares an estimated jumping destination address 9 with an actual jumping destination address 10. An estimation error signal 11 is outputted when no coincidence is obtained from said comparison and the part 3 performs the branch processing to a correct jumping destination address. In case a branch instruction which is not registered into a branch target buffer 4 is carried out and a branching phenomenon occurs, an address 8 of the instruction that carried out immediately before the branch instruction stored in a latch 6 and under execution is used to register an instruction address 12 carried out right before the branch instruction, a branch estimation bit 13 and a jumping destination address 14 of a branch instruction executing device into the buffer 4. As a result, the buffer 4 can be retrieved before the address of the branch instruction is fixed. Thus the instruction data on the jumping destination address can be early fetched and therefore the processing speed is increased with a data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device equipped with a pipeline processing function and a branch instruction jump destination prediction mechanism.

[Conventional technology]

FIG. 3 is a block diagram of a conventional data processing device equipped with a pipeline processing function and a branch instruction jump destination prediction mechanism. In this figure, 1 is an instruction briefetch queue as an instruction pre-fetching device, 2 is an instruction decoding unit as an instruction analysis device, 3 is an instruction execution unit as an instruction execution device, and 5 is a judgment whether the branch prediction was correct 17 or not. comparison circuit, 9
is the predicted destination address, 10 is the actual destination address, 1
1 is the prediction i5[return signal indicating that the prediction is wrong, 15 is the branch target buffer that measures the jump photons of branch instructions, etc., 16 is the address of the instruction being decoded, and 17 is the branch instruction currently being executed. This is the address.

FIG. 4 is a diagram showing the contents of the branch target buffer 15 shown in FIG. a branch prediction bit that predicted whether it would happen or not;
14 is the jump address of the branch instruction, and 18 is the branch instruction address.

Next, the operation of the data processing device will be explained.

When the instruction execution unit 3 is executing a certain instruction, the instruction decoding unit 2 is decoding the next instruction to be executed, and the instruction prefetch queue 1 is ordering multiple instructions by address according to a certain rule. The main memory (hereinafter referred to as main memory), which stores data in a plurality of areas, utilizes the time when it is not being accessed to anticipate and fetch the next instruction to be fetched. In this way, in a data processing device, effective speed can be increased by performing pipeline processing in which each section operates in parallel. However, when the flow of instructions is disrupted, for example when a branch instruction is executed, the decoding result in the instruction decoding unit 2 and the instruction data fetched into the instruction briefetch key 5-1 are canceled and the instruction briefetch queue 1 performs new queuing from the jump destination address. That is, the first instruction to be executed after execution of a branch instruction must be directly fetched from main memory, and the instruction execution unit 3 must suspend instruction execution until the instruction is fetched and decoded. In the data processing apparatus shown in FIG. 3, something called a branch targeter I buffer 15 is used to improve this point. This uses the previously executed branch instruction address 18 as an index and the jump destination address 14 of that branch instruction.
and branch prediction bit 1, which predicts whether or not a branch will occur when the branch instruction is executed again based on the past history.
It is a jump photon N mechanism that predicts the destination address before actually executing a branch instruction. Depending on the prediction method, it is possible to predict the program flow with a fairly high probability. I know.

Next, its operation will be explained.

When the instruction data is fetched from the instruction briefetch queue 1 to the instruction decoding unit 2, the instruction decoding unit 2 starts decoding the instruction, and at the same time, the instruction data is read from the address 16 of the instruction being decoded.
The branch target buffer 15 is searched.

If the address of the instruction is not registered in the branch target buffer 15, or even if it is registered, the branch prediction bit 13 predicts that the branch will not occur, the instruction decoder 2 fetches the instruction from the instruction briefetch key:, -1. Fetch the next instruction and continue processing. However, if the address of the instruction is registered in the branch target buffer 15 and the branch prediction bit 13 predicts that a branch will occur, the instruction briefetch queue 1 will store the instruction that is fetched assuming that a branch will occur. The data is cleared, instruction data is queued in the branch target buffer 15 from the predicted jump destination address 14, and the fetched instruction data is passed to the instruction decoder 2. When the prediction is correct, the instruction execution unit 3 should not take a branch.Since the next instruction to be executed can be retrieved from the main memory in the 9th period, the waiting time until the next instruction is executed can be shortened. can.

When the branch instruction for which branch prediction has been performed is executed by the instruction execution unit 3 and the jump destination address is determined, the predicted jump destination address 9 and the actual jump destination address 10 are compared in the comparator ll55, and as a result, both of them are If they do not match, a prediction error signal 11 indicating that the prediction is incorrect is output, and the instruction execution unit 3 performs branch processing to the correct destination address, even if the branch does not occur. Also, branch target
When a branch instruction that has not been registered in the buffer 15 is executed or the branch prediction is incorrect, the branch target buffer 15 is stored at address 17 of the branch instruction currently being executed.
Processes registration and content changes.

By adding the branch target buffer 15 in this manner, disturbances in pipeline processing after execution of a branch instruction can be suppressed, and the effective calculation speed of the computer can be increased.

[Problem that the invention seeks to solve]

As described above, a data processing device equipped with the conventional pipeline processing function is a branch target.

By providing a buffer 15, the jump destination address is predicted and disturbances in pipeline processing are suppressed, but when instruction decoding is started, the instruction address is determined to be the address of the instruction decoded immediately before, based on the decoding result. Therefore, there is a problem in that it is difficult to obtain the address of the instruction at the time when instruction decoding is started at the same time as instruction decoding is started.

In particular, in a data processing device that has an instruction cell 1- for variable-length instructions, it takes time to determine the instruction length, so there is a problem that it is even more difficult to obtain the address of the instruction when instruction decoding is started. Ta.

The present invention has been made to solve these problems, and an object of the present invention is to obtain a data processing device that can perform jump photon measurement of branch instructions at an early stage. A data processing device according to the invention includes: an instruction execution device that executes a first instruction sequence stored in a main memory device that stores a plurality of instructions in a plurality of areas in an order based on addresses according to a certain rule; an instruction analysis device that analyzes a second instruction sequence following the first instruction sequence while the instruction sequence is being executed by the instruction execution device; and the second instruction sequence is analyzed by the instruction analysis device. An instruction pre-fetching device fetches from the main memory a third instruction string to be analyzed next by the instruction analysis device, and an instruction pre-fetching device that fetches the third instruction string to be analyzed next by the instruction analysis device from the main memory, and the first instruction string that was previously analyzed or the previous instruction when analyzing the second instruction string. The second index uses the column address as the index.
It is determined whether the instruction sequence is a branch instruction, and when it is determined that it is a branch instruction, the pre-stored jump destination address is sent to the instruction prefetch device, and the instruction sequence starting from that address is sent from the main memory. A flying photon measurement device that captures
A comparison circuit that compares the jump destination address determined when the second instruction string is executed with the jump destination address obtained by the jump photon measurement device, and If the comparison result by the comparator circuit does not match, the data processing device consisting of a holding circuit that holds addresses is re-fetched, and the contents of the flying photon measurement device are held in the holding circuit. The configuration is such that the address is corrected using the specified address.

〔Example〕

FIG. 1 is a block diagram of an embodiment of a data processing apparatus according to the present invention. In this figure, the same reference numerals as in FIG. 3 indicate the same parts, and 4 is a branch targeter 1--buffer as a flying photon measurement device for measuring jumping photons of branch instructions, etc.;
6 is a latch serving as a holding circuit for storing the address of the instruction that was executed immediately before the instruction currently being executed by the instruction execution unit 3; 7 is the address of the instruction that was executed immediately before the instruction that is being decoded; 8 is the address of the instruction executed immediately before the branch instruction currently being executed.

Further, FIG. 2 is a diagram without showing the contents of the branch target buffer 4 shown in FIG. 1, and in this diagram,
The same reference numerals as in FIG. 4 indicate the same parts, and 12 is the address of the instruction executed immediately before the branch instruction.

Next, the operation will be explained.

The branch target buffer 4 uses the address 12 executed immediately before the branch instruction executed in the past as an index.
The branch prediction bit 13, which predicts whether or not a branch will occur when the branch instruction is executed again, is stored as a set based on the jump address 14 of the branch instruction and the past history. Before actually executing the instruction, determine whether it is a branch instruction and predict the destination address. When instruction data is fetched from the instruction prefetch queue 1 to the instruction decoding unit 2, the instruction decoding unit 2 starts decoding the instruction and uses the address 7 of the instruction decoded immediately before the instruction being decoded as an index to set the branch target. - Search buffer 4.

If the address is not registered in the branch target buffer 4, or even if it is registered, the branch prediction bit is 1.
3 predicts that the branch will not occur, the instruction decoder 2 fetches the next instruction from the instruction prefetch queue 1 and continues processing. However, that address is registered in branch target buffer 4, and branch prediction bit 1
If 3 predicts that a branch will occur, it is determined that the instruction currently being decoded is a branch instruction and that there is a high probability that a branch will occur this time as well, and the instruction prefetch queue 1 clears the fetched instruction data. Then, instruction data is queued from the jump destination address 14 predicted by the branch target buffer 4, and the fetched instruction data is passed to the instruction decoder 2. That is, when the prediction is correct, the branch target buffer 4 is searched at the address of the instruction executed immediately before the branch instruction, so branch prediction can be performed earlier than when searching at the address of the branch instruction. After execution of a branch instruction, the next instruction to be executed can be fetched from the main memory more reliably, so the waiting time until the next instruction is executed can be shortened. When the branch instruction for which branch prediction has been performed is executed by the instruction execution unit 3 and the jump destination address is determined, the predicted jump destination address 9 and the actual jump destination address 10 are compared in the comparison port wFI5, and as a result, both If they do not match, a prediction error signal 11 indicating that the prediction is incorrect is output, and the instruction execution unit 3 performs branch processing to the correct destination address even if the branch does not occur. In addition, if a branch instruction that was not registered in the branch target buffer 4 is executed and a branch occurs, the address of the instruction executed immediately before the currently executing branch instruction stored in the latch 6 8, the instruction address 12, branch prediction pin), 13, which was executed immediately before the branch instruction is stored in the branch target buffer 4.
The jump destination address 14 after execution of the branch instruction is registered.

At this time, the branch prediction bit 13 predicts that the program will branch the next time it is executed. Furthermore, if the branch prediction is incorrect, the address 8 of the instruction executed immediately before the currently executed branch instruction stored in the latch 6 is used to set the branch prediction bit 13 of the branch target buffer 4 and the branch prediction bit 13 of the branch target buffer 4. The jump destination address 14 is changed after the instruction is executed.

In this way, address 8 of the instruction executed immediately before the branch instruction
By providing a branch target buffer 4 that performs photon measurement for the branch instruction to be executed next, the branch target buffer 4 can be searched as soon as the address of the branch instruction is determined, so the branch target buffer 4 can be searched at an early stage. It becomes possible to take in instruction data at a jump destination address, suppressing disturbances in pipeline processing after execution of a branch instruction, and increasing the effective processing speed of the data processing device.

In the above embodiment, branch prediction is performed at the address of the instruction that was executed immediately before the branch instruction, but branch prediction may be performed at the address of any instruction that was executed as the target of the branch instruction.

〔Effect of the invention〕

As described above, the present invention includes an instruction execution device that executes a first instruction sequence stored in a main memory that stores a plurality of instructions in a plurality of areas ordered by addresses according to a certain rule; an instruction analysis device for analyzing a second instruction sequence in the order subsequent to the first instruction sequence while the instruction sequence is being executed by the instruction execution device; an instruction pre-fetching device that fetches from the main memory a third instruction string to be analyzed next by the instruction analysis device; and an instruction pre-fetching device that fetches from the main memory a third instruction string that is to be analyzed next by the instruction analysis device; It is determined whether the second instruction string is a branch instruction using the address as an index, and when it is determined that it is a branch instruction, the pre-stored jump destination address is sent to the instruction prefetching device and the instruction starts from that address. a flying photon measurement device that imports an instruction sequence from the main memory;
A comparison circuit that compares the jump destination address determined when executing the instruction string with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed. If the comparison result by the comparator circuit does not match, the data processing device consisting of a holding circuit that holds data is re-executed to take in the instruction sequence, and the contents of the flying photon measurement device are held in the holding circuit. Since the configuration is corrected using the address, the jump photon measurement can be performed earlier than when the jump photon measurement is performed at the address of the branch instruction, and the instruction at the predicted jump destination address can be taken into the instruction decoding section more quickly. This has the effect of increasing the effective processing speed of the data processing device by as much as possible.

Furthermore, for branch instructions that depend on the history, branch prediction is performed using the instruction address executed before the branch instruction, which is particularly effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention, and FIG.
FIG. 3 is a block diagram of a conventional data processing device, and FIG. 4 is a diagram showing the contents of the branch target buffer shown in FIG. 3. In the figure, 1 is an instruction briftetch queue, 2 is an instruction decode section, 3 is an instruction execution section, 4 is a branch target buffer, 5 is a comparison circuit, and 6 is a latch. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) 1. Indication of the incident: Patent Application No. 1983-270697 2,
Name of the invention Data processing device 3, relationship to the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Claims column 2 of the specification to be amended, Detailed description of the invention column 6, Contents of the amendment (1) The claims of the specification will be amended as shown in the attached sheet. (2) ``As a 1-instruction prefetch device'' on page 2, lines 19-20 of the specification is deleted. (3) Similarly, on page 6, line 3, 1 predicted by [ is corrected to [ predicted by 1. (4) Similarly, delete "as above," on page 7, line 8. (5) Correct the same (1-target buffer on page 7, line 9) to 1 target buffer. (6) Same as page 8, line 5 to page 9, line 9.
...It is structured as follows. ” is corrected as follows. 1. An instruction execution device that executes a first instruction sequence stored in a main memory that stores a plurality of instructions in a plurality of areas ordered by addresses according to a certain rule, and an instruction execution device that executes the first instruction sequence. an instruction analysis device that analyzes a second instruction sequence following the first instruction sequence while the branch instruction is being executed; The destination address is registered, and when the second instruction string is analyzed, the address of the first instruction string that was previously analyzed or the previous instruction string is used as an index, and the second instruction string is a branch instruction and a branch occurs. Determine whether
a jump photon measurement device that sends out a pre-stored jump destination address when it is determined that a branch will occur and fetches an instruction sequence starting from that address from a main memory;
A comparison circuit that compares the jump destination address determined when executing the instruction string with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed. The data processing device is composed of a holding circuit that holds data, and when the comparison result by the comparison circuit does not match, the instruction sequence is re-fetched and the contents of the flying photon measurement device are held in the holding circuit. When a branch instruction that has been corrected using the address of the instruction sequence stored in the holding circuit is executed and a branch occurs, the address of the instruction string stored in the holding circuit is used to correct the branch instruction that was not stored in the photon measurement device. The configuration is such that the contents are registered in the . 2” (7)
Similarly, 1 is deleted from the 1-instruction prefetch device on page 9, lines 14-15. (8) Similarly, 1 execution 1 in the 10th α4 line is decoded 1-
1 and correct 3, (9) Same ([Executed address 12] on page 10, line 14)
is corrected to "address 12 of the executed instruction." (10) This is also a 1-branch instruction on page 10, line 19. Correct it to 1. (11) Similarly, page 12, line 20, 1 instruction address 12'',
Correct it to "instruction address 12". (12) Similarly, -1, which takes in one instruction data, on page 13, line 14, is corrected to 1, which takes in one instruction data. (13) The same (1 or more I's in line 3 on page 14 to line 6 on page 15) should be corrected as follows. an instruction execution device that executes a first instruction sequence stored in a main memory that is stored in a plurality of areas; and an instruction execution device that executes a first instruction sequence that is stored in a plurality of areas; An instruction analysis device that analyzes a second instruction sequence in sequence, and a branch prediction and jump address are registered using the address of an instruction sequence executed immediately before or before the branch instruction as an index, and the instruction of the second instruction sequence is registered. Determining whether the second instruction string is a branch instruction and a branch will occur by using the address of the first instruction string or the previous instruction string as an index during analysis,
a jump photon measurement device that sends out a pre-stored jump destination address when it is determined that a branch will occur and fetches an instruction sequence starting from that address from a main memory;
A comparison circuit that compares the jump destination address determined when executing the instruction string with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed with the jump destination address obtained by the jump photon measurement device, and a comparison circuit that compares the jump destination address determined when the instruction string is executed. The data processing device is composed of a holding circuit that holds the data, and when the comparison result by the comparison circuit does not match, the fetching of the instruction sequence is re-executed, and the flying photon 7N
When the contents of the device are modified using the address held in the holding circuit and a branch instruction that was not stored in the flying photon measurement device is executed and a branch occurs, the instruction stored in the holding circuit The content is registered in the flying photon measuring device using the column address.'' 2. Claims 2. Storing a plurality of commands in a main memory device in which a plurality of instructions are stored in a plurality of areas ordered by addresses according to a certain rule. an instruction execution device that executes a first instruction sequence that has been executed, and a second instruction sequence that follows the first instruction sequence while the first instruction sequence is being executed by the instruction execution device; An instruction analysis device to analyze and when analyzing the second instruction sequence of the branch instruction, use the address of the first instruction sequence that was analyzed last time or the previous instruction sequence as an index to determine whether the second instruction sequence is a branch instruction. and determines whether or not a branch will occur, and when it is determined that the branch will occur, retrieves the pre-stored Hosei jump destination address and reads the instruction sequence starting from that address from the main memory. a flying photon measuring device to be imported; a comparison circuit for comparing a jump address determined upon execution of the second instruction string with the jump destination address obtained by the flying photon measuring device; and a currently executing instruction string. and a holding circuit that holds an address of an instruction string that was executed immediately before, the data processing device is configured to re-fetch the instruction string if the comparison result by the comparison circuit is a mismatch, and A data processing device characterized in that the content in the flying photon measuring device is modified using an address held in the holding circuit.

Claims (1)

[Claims] an instruction execution device that stores a plurality of instructions in a plurality of areas ordered by addresses according to a certain rule, and executes a first instruction sequence that is not stored in a main memory; an instruction analysis device that analyzes a second instruction sequence following the first instruction sequence while being executed; an instruction pre-fetching device that fetches a third instruction string to be analyzed by the instruction analysis device from the main storage device;
It is determined whether the second instruction sequence is a branch instruction using the address of the instruction sequence or the previous instruction sequence as an index, and when it is determined that the second instruction sequence is the branch instruction, the pre-stored jump destination address is determined. A jump destination prediction device that sends the instruction sequence to the instruction prefetch device and fetches the instruction sequence starting from that address from the main storage device, a jump destination address that is determined when the second instruction sequence is executed, and the jump destination prediction device A data processing device comprising a comparison circuit that compares the obtained jump destination address and a holding circuit that holds the address of an instruction sequence that was executed immediately before the instruction sequence that is currently being executed, the data processing device comprising: If the comparison result by the circuit does not match, the fetching of the instruction sequence is re-executed, and the contents in the jump destination prediction device are corrected using the address held in the holding circuit. data processing equipment.