JPS60179845A - Instruction rereading control system - Google Patents

Abstract

PURPOSE:To reread an instruction from an optional flow and an optional stage by storing instruction length corresponding to an address for prereading the instruction and an instruction address calculated from an instruction pointer in registers consisting of shift registers respectively and calculating a leading address from both the corresponding registers. CONSTITUTION:An address for prereading an instruction in each eight bytes is stored in a prefetching instruction address register 13 and a value of ''8'' is stored in a PFK register. An adder 4 sets up an effective address in a register 5, so that a buffer 6 is retrieved and the instruction is fetched and read out by an instruction register 7. An instruction pointer 14 holds the relative pointer of an instruction to be executed. The output of the adder 15 is an instruction address flowing through a pipe line and sent to the instruction address registers 16-18 constituted of plural shift registers. The contents of the corresponding instruction length register 20 are sent to instruction length register 20 and a pair of instruction length is selected and added to obtain a rereading address.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to an instruction rereading control system, particularly a data processing device that performs pipeline control.
For instructions that require rereading of subsequent instructions such as DS instructions and TS instructions, by having an adder that can calculate the start address of instruction rereading from any stage, it is possible to start instruction rereading early and improve performance. This invention relates to an improved instruction reread control method.

(B) Prior Art and Problems In a data processing device that executes instructions by pipeline control, a C S (Compare and Swap) instruction, known as a so-called serialization instruction,
CD S (Compare and Double
Swap) instructions, TS (Test and 5et) instructions, etc. require all subsequent instructions that have been fetched in advance to be discarded and the instructions to be fetched anew. This behavior is (
It is called ``Ryōsuzudatsu 1''. The above-mentioned command appears quite frequently, especially in the operating system (O3) of a large machine in which a large number of tasks are executed in a time-sharing manner. Therefore, it is extremely important for the performance of the processing device to perform instruction reread operations for these instructions at high speed and to reduce loss.

FIGS. 1 and 2 are diagrams for explaining problems with the conventional method.

FIG. 1 shows an example of conventional instruction rereading in a pipeline-configured computer that requires three stages for instruction fetch and six stages for instruction execution.

Instruction fetch control consists of, for example, a stage (1) that determines the address from which the instruction is fetched, an IT stage that converts the instruction address into a real address, and an IB stage that reads the instruction from the buffer. A D stage for decoding an instruction, an A stage for calculating an operand address, a T stage for converting an operand address into a real address, and a B stage for reading from a buffer managed by a storage control unit.
It consists of control stages: an E stage for arithmetic processing, and a W stage for checking and writing results.

Each of these stages is generally independent and can be controlled in advance, and pipeline processing is performed in high-speed computers. Hereinafter, the case where the control stage described above is provided will be explained as an example, but the present invention is not limited to this.

An instruction that causes instruction re-reading is normally a multi-flow instruction, and a plurality of sets of D stages to W stages constitute one instruction. As shown in FIG. 1, normally there are several flows f2 to f4 after flow 11 in which instruction re-reading is determined. In the conventional method, the intermediate flow f1
After the final W stage of the final flow f4 of the instruction, an address for re-reading the instruction is calculated based on the instruction re-reading information detected in , and the instruction is re-read.

That is, a conventional circuit for calculating an address for re-reading an instruction is, for example, as shown in FIG. In FIG. 2, 1 is an instruction address register, 2 is a half-word counter, 3 is a PFK register, 4 is an adder that generates the effective address of the instruction, 5 is an instruction effective address register, 6 is a counter, and 7 is an instruction word. Represents a register.

In the conventional circuit, the instruction address register 1 is also used as the instruction address section (PSWI8R) of the PSW, and is the same register as a part of the PSW.

During a normal instruction fetch, the instruction address to be fetched is determined by adding the contents of the instruction address register 1 and the PFK register 3 (normally 8).

For example, when an interrupt occurs and the address of the instruction being executed (OLDPSW) is needed, it can be found by subtracting the displacement between the fetch address and the instruction address that is the content of half-word counter 2 from instruction address register 1. It will be done like this.

In such a system, a subsequent instruction can only be fetched after the previous instruction is completed.

That is, since the instruction address register 1 is also used as a part of the PSW, the instruction address register 1 cannot be changed during instruction execution.

Therefore, the address for rereading the instruction is not created until after the final flow of instructions is completed, and the address for rereading the instruction is
There is a problem in that a large amount of loss occurs before execution of the subsequent instruction starts.

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and when it becomes necessary to reread a subsequent instruction, the start address for rereading the instruction is
The purpose is to enable calculations to be made from any stage of any flow, and to enable instruction fetching to be started at an early timing when rereading instructions. That is, the instruction rereading control method of the present invention is an instruction rereading control method for an information processing device that controls execution of instructions using a pipeline, and includes a prefetch instruction address register in which an address for pre-reading an instruction is stored, and a register for pre-reading an instruction. an instruction pointer that indicates the beginning of the instruction to be executed; a circuit that calculates the address of the instruction being executed from the prefetch instruction address register and the instruction pointer; an instruction address register consisting of a multi-stage shift register that receives an instruction address; an instruction length register consisting of a multi-stage shift register storing an instruction length corresponding to the instruction address register; and the instruction address register. and an adder that calculates the start address of the instruction to be executed next to the instruction held at the address held by the instruction address register from one of the above instruction length registers and the corresponding instruction length register, and calculates the instruction reread event. At the time of detection, set the output of the adder to the prefetch instruction address register,
It is characterized by being configured to execute instruction rereading. Hereinafter, embodiments will be described with reference to the drawings.

(D) Embodiment of the invention FIG. 3 is a time chart for explaining the outline of control according to the invention, FIG. 4 is a main part configuration of an embodiment of the invention, and FIG. 5 is an instruction processing circuit using the invention. Here is an example.

In the case of the present invention, the start address and instruction length of the instruction currently being executed are held at each stage, and when it is decided to reread the instruction, based on this information, the address for rereading the instruction, That is, a start address for rereading the subsequent instruction is created, and rereading of the instruction is started. In the example shown in FIG. 3, the instruction reread address is determined based on the T stage address and the instruction length of the instruction, and the instruction is reread without waiting for the end of the final flow. The time loss in the example is reduced. Note that, as will be described later, it is also possible to determine the address for rereading the instruction at another stage.

Therefore, a circuit for creating an address for rereading instructions is, for example, as shown in FIG.

In FIG. 4, numerals 3 to 7 correspond to those in FIG. 2, 13 is a prefetch instruction address register for advance reading, and 14 is an instruction pointer, and the currently executed instruction is at the address indicated by the instruction address register 13. How many half words from (
15 is an adder that calculates the address of the prefetched instruction; 16 to 18 are instruction address registers corresponding to each stage; 20 is an instruction length register for the decoded instruction; 21
23 are instruction length registers corresponding to each stage, 25 is one of instruction address registers 16 to 18 corresponding to the selected stage, and instruction length registers 21 to 2.
represents an adder that adds 3 to its corresponding one.

The prefetch instruction address register 13 contains, for example, 8 by 1.
Addresses for pre-reading instructions in units of ~ are stored. The PFK register 3 has an initial value of 0, and thereafter holds a value of 8.The adder 4 adds the value of the instruction address register 13 and the value of the PFK register 3, and calculates the effective address. -Res is set in the register 5. Based on this address, the memory control unit searches the buffer 6, fetches the instruction, and reads it into the instruction word register 7. From then on, the instruction address is set to "8".
' are added and fetched sequentially.

Note that a configuration may be adopted in which a plurality of prefetch instruction address registers 13, instruction word registers 7, etc. are provided for use when an instruction is branched.

Instruction pointer 14 maintains a relative pointer to where each executed instruction is located within the fetched instruction in 8-byte positions. The output of the adder 15 is the address of the instruction flowing in the pipeline, and the output is the address of the instruction flowing in the pipeline, and the instruction address registers 16 to 18 are composed of multiple stages of shift registers.
are sent out in sequence. Correspondingly, the contents of the instruction length register 20 that holds the instruction length are sent to instruction length registers 21 to 23 provided in a plurality of stages at each stage.

Instruction address registers 16 to 16 corresponding to each stage
18 and instruction length registers 21 to 23 using a multiplexer and adding their contents using an adder 25, it becomes possible to generate an address for rereading an instruction at any stage. ing. When an instruction reread is required, the instruction reread address generated by the adder 25 is controlled to be placed in the prefetch instruction address register 13, so that the instruction fetch sequence is started immediately. There is.

FIG. 5 shows an example of an instruction processing circuit using the present invention, and in the figure, the same reference numerals as in FIG. 4 correspond to those in FIG. 26 is an instruction address register that holds the address of the instruction being executed; 27 is an instruction length register that holds the instruction length of the instruction that is being executed; 28 is an adder that calculates the next instruction address; 30 is a displacement register; 31 32 is a base register, 32 is an index register, 33 is an operand address generation circuit, 34 and 35 are operand address registers, 36 is an operand word register, 37 is an execution circuit, and 38 is a result register.

Initially, when the instruction address to be executed is stored in the PSW instruction address field of the instruction address register 26, the same address is also supplied to the prefetch instruction address register 13. As described above, instructions are sequentially fetched in units of 8 hides according to the address calculated by the adder 4.

The operand address generation circuit 33 has registers 30 to
32 etc., the effective address of the operand is calculated and placed in the operand address register 34.

As a result, the buffer 6 is accessed by the storage control section, an operand word is prepared, and the execution circuit 37, which is the operation unit 71 section, performs the operation. The result is written to result register 38.

In the case of the present invention, as explained with reference to FIG.
An adder 25 is provided to add the contents of 3 and the contents of 3, and its output is guided to the prefetch instruction address register 13, so that rereading of the instruction from the A stage, 'r stage, or B stage is not possible. , has become possible. Furthermore, in this embodiment, the instruction address section (PSW) of the PSW is
an instruction address register 26 which is also used as WIAR);
An adder 28 is provided that calculates the address of the instruction next to the currently executed instruction based on the instruction length register 27 that holds the instruction length of the instruction in the W stage. Since the start address of the next instruction is always calculated by the adder 28 in addition to the address calculation for advance read by the adder 4, this also allows the instruction reread sequence to start earlier. ing.

(E) As described in detail, according to the present invention, the address of the instruction re-read river is created at an early timing, and the address of the instruction being executed is
Since instruction rereading can be started early from any stage of any flow, processing performance is improved.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams for explaining problems with the conventional method, Figure 3 is a time chart for explaining the outline of control according to the present invention, and Figure 4 is a main part configuration of an embodiment of the present invention. , FIG. 5 shows an example of an instruction processing circuit using the present invention. In the figure, 1 is an instruction address register, 2 is a half word counter,
3 is a PFK register, 4 is an adder that generates the effective address of an instruction, 5 is an instruction effective address register, 6 is a buffer, 7 is an instruction word register, 13 is a prefetch instruction address register, 14 is an instruction pointer, and 116 to 18 are each Instruction address register corresponding to each stage, 20
24 to 24 are instruction length registers, and 25 is an adder. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori 1) (1 other person) Fue 3 [21 p A Ding B E

Claims (1)

[Claims] In an instruction reread control method in an information processing device that controls execution of instructions using a pipeline, a prefetch instruction address register stores an address for pre-reading an instruction, a register stores the pre-read instruction, and a register is used to control the execution of the instruction. It consists of an instruction pointer indicating the beginning of an instruction, a circuit that calculates the address of the instruction being executed from the prefetch instruction address register and the instruction pointer, and a multi-stage shift register that receives the instruction address calculated by the adder. one of the instruction address registers and the instruction corresponding to the instruction address register; a long register and an adder that calculates the start address of the instruction to be executed next to the instruction at the address held by the instruction address register, and when an instruction reread event is detected, the output of the adder is used as the prefetch instruction. An instruction rereading control method characterized in that the instruction is read out in an address register and the instruction is read out again.