JPS6131894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device in a data processing device, and more particularly to means for executing software instructions that stores a group of firmware instructions stored in a main memory in a control memory. .

Conventionally, a load firmware instruction, which is a software instruction that stores a part of a group of firmware instructions stored in the main memory in a control memory, is a software instruction that stores a part of the group of firmware instructions stored in the main memory in a control memory. Since the firmware instructions were stored in the control memory and the next software instruction was executed after the storage was completed, subsequent execution from the next software instruction was not executed until a part of the firmware instruction group was stored in the control memory. It was possible.

The present invention has been made in order to eliminate the above-mentioned disadvantages inherent in the conventional technology, and an object of the present invention is to provide a data processing system in which execution control of software instructions is shared between hardware control and firmware control. In the processing device, a load firmware instruction, which is a software instruction that stores a part of the firmware instruction group stored in the main memory in the control memory, is activated, and the execution control of the software instruction is executed by the hardware. By having means for storing a part of the firmware command group written in the main memory in the control memory while the control is being performed, and means for reporting the completion of the storage to the software, It is an object of the present invention to provide a novel microprogram control device capable of parallel processing of execution control of the software instructions and storage of part of the firmware instruction group stored in the main memory into the control memory.

That is, according to the present invention, a rewritable control memory that stores a first firmware instruction group;
storage means for storing a group of firmware instructions;
A load firmware instruction, which is a software instruction stored in the control memory as part of the second firmware instruction group, is provided, and execution control of the software instructions is shared between hardware control and firmware control. In the data processing device, a part of the second firmware instruction group is stored in the control memory while the hardware control is activated by the load firmware instruction and controls the execution of the software instruction. and means for reporting to software the completion of the storage operation of a part of the second firmware instruction group activated by the load firmware instruction into the control memory. , is given.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing the main unit configuration of a data processing device and a main storage device used in an embodiment of the present invention. In the figure, a unit designated by reference number 10 is a main storage device. The unit indicated by reference number 11 is a memory control unit that controls the main storage device 10 in response to requests from the data channel and memory buffer unit 12. The memory buffer unit 12 is a unit that includes a high-speed address conversion buffer and a local memory, and performs conversion from logical addresses to absolute addresses and control of the local memory. The unit designated by reference numeral 13 is a control store unit containing control storage and controlling the firmware, and is the central unit for implementing the invention. The unit designated by reference number 14 is an instruction execution unit that executes software instructions and performs other data processing. The unit designated by reference numeral 15 is an instruction prefetching unit that prefetches software instructions, generates logical addresses, prefetches operands, etc.

FIGS. 2 and 3 are block diagrams around the control memory.

In FIG. 2, the control memory 20 is (8 bytes +
It has a capacity of 1 byte of error check and correction information x 8K words, and inputs the signal line 201 from the register 22. The selector 21 in the figure is a selector of 8 bytes + 1 byte of error check and correction information, and connects the signal lines 211 to 214 from the control memory 20 to the signal line 22.
Select 3 and output. The register 22 is a control storage read register of 8 bytes + 1 byte of error check and correction information, and is connected to a signal line 223 from the selector 21, a signal line 221 from the error check and correction information generation/correction circuit 24, and an external register. The signal line 222 of the register 22 is input, and all operation instructions from the firmware are issued from this register 22. register 2
3 is an 8-byte control storage write register, which is connected to a signal line 231 for main memory read data sent from the memory buffer unit 12 in FIG.
is taken as input. The error check and correction information generation and correction circuit 24 generates error check and correction information and stores it in the control memory 20.
This is a circuit that corrects a 1-bit error in register 2 from error check and correction information.
The signal line 242 from the register 2 and the signal line 241 from the register 23 are input.

In FIG. 3, an address register 30 inputs a signal line 301 from a selector 33 with a 2-byte address of the currently running firmware.
The address register 31 in FIG. 2 is a 2-byte control storage return address register used in firmware subroutine calls, and the signal line 314 from the register 32 is connected to the register 2 in FIG.
Inputs include a signal line 313 from the lower two bytes of the register 22, a signal line 312 from the upper one byte of the register 30 and the lower one byte of the register 22 in FIG. 2, and a signal line 311 from an external register. The address register 32 has 2 bytes in which are set an increment value of the address of the currently running firmware, a start address when the firmware control is activated from hardware control, and an address when storing the firmware in the control memory 20. is a control storage increment address register of the selector 33, and the signal line 321 of the increment value of the selector 33,
Inputs are a signal line 322 for an address generated under external hardware control and a signal line 323 from the address register 41 in FIG. 4. The selector 33 is a 2-byte selector that selects the address of the control memory 20 in FIG. Register 22 in Figure 2
A signal line 331 from the lower 1 byte of , and a signal line 332 from the lower 2 bytes of the register 22 in FIG.
is taken as input. The conditional branch judgment circuit 34 is a circuit that judges 2-way and 4-way conditional branches of the firmware, and inputs a signal line 341 from the lower two bits of the selector 33 and signal lines 342 and 343 of conditional branch judgment information from the outside. , the select signal of the selector 21 in FIG. 2 is output.

FIG. 4 shows the main memory address, control memory address, and The registers for setting and managing the number of firmware load words are shown. In the figure, an address register 40 is a 4-byte register for setting and managing main memory addresses, and is included in the instruction prefetch unit 15 in FIG.
02 is input. address register 41
is a 2-byte register for setting and managing control storage addresses, and inputs a signal line 411 for the increment value of the main address register 41 and a signal line 412 from an external register. Register 42 is a 2-byte register that sets and manages the number of firmware load words.
A signal line 421 for decrementing 2 and a signal line 422 from an external register are input. The AND circuit 43 connects the signal line 43 from the register 42
1 is input, and it is detected that the contents of the register 42 are "0".

FIG. 5 shows (a) the format of the load firmware instruction, (b) the main memory operand given by the load firmware instruction, and (c) the structure of the control memory. In FIG. 5A, a field designated by reference number 501 is an 8-bit instruction code portion used to identify an instruction. The field indicated by 502 is always "0" in the load firmware instruction. The field indicated by 503 is an address syllable portion that specifies the start address of the main memory operand shown in FIG. 5B using 20 bits. Figure 5b
, the main memory operand 511 contains the number of firmware load words, and the main memory operand 512
has a control memory address and a main memory operand 51.
3 has a main memory address set. In FIG. 5c, the control memory structure 52 includes an area 521 where software can freely store and execute a part of firmware instructions in the main memory, and an area 521 for controlling the execution of software instructions and a data processing device. It consists of an area 522 in which a group of firmware instructions that perform necessary control are always stored.

When the load firmware command is issued, the fifth
Main memory operands 511, 512 and 51 in Figure b
3 is read and checked for validity. When main memory operands 511, 512, and 513 are all valid, main memory operand 511 goes to the register in FIG. 4, main memory operand 512 goes to address register 41 in FIG. 4, and main memory operand 513 goes to the register in FIG. The address register 40 is set, and the control whose operation flow is shown in FIGS. 6 and 7 is activated. The load firmware instruction is finished at this point, and the completion of storing the firmware instructions in control memory is reported to another software instruction, the waitload firmware end instruction. If a group of firmware instructions has already been stored in the control memory when the waitload firmware end instruction is issued, the waitload firmware end instruction terminates immediately and there are still firmware instructions in the control memory. If the storage of the group has not yet been completed, the waitload firmware end command waits for the storage to be completed and ends.

FIG. 6 will be explained. When the control shown in FIG. 6 is activated by a load firmware instruction, it is checked whether all words of the firmware instruction group specified by the register 42 in FIG. 4 have been read from the main memory. When all words have been read, the process ends without doing anything, and when all words have not been read, an indicator (RGBSY) indicating the validity of register 23 in Figure 2 is displayed.
Checks whether register 23 is empty. An indicator (EXRQ) that indicates that if it is not empty, it waits until it becomes empty, and if it is empty, a main memory access request is being made for instruction execution control etc.
and an indicator (IFRQ) indicating that a main memory access request is being made under instruction prefetch control are both "0". When it is not "0", it becomes "0", and when it is "0", a main memory read request is made with the address set in the address register 40 shown in FIG. 4, and the read data from the main memory is sent as shown in FIG. is set in the register 23 through the signal line 231. Next, the indicator (RGBSY) indicating the validity of the register 23 in FIG. 2 is set to "1", and the main memory address set in the address register 40 in FIG. 4 is +8.
Then, the number of firmware load words set in the register 42 in FIG. Thereafter, it is checked again whether all words of the firmware instruction group specified by the register 42 in FIG. 4 have been read from the main memory.

FIG. 7 will be explained. When the control shown in FIG. 7 is activated by a load firmware instruction, it is checked whether all words of the firmware instruction group specified by the register 42 in FIG. 4 have been stored in the control memory 20 in FIG. 2. . When all words have been stored, an indicator (LFWED) is set, which is a means of reporting for the waitload firmware end instruction, and when all words have not been stored, the indicator (RGBSY) is used to check whether register 23 in Figure 2 is valid. Check. When it is not valid, it becomes valid, and when it is valid, an indicator (FWBSY) is checked to see if the firmware control is in operation. When it is in operation, it is turned off, and when it is not in operation, the contents of the address register 41 in FIG. 4 are set from the signal line 323 to the address register 32 in FIG. 3. Next, error check and correction information is added and set to the contents of the register 23 from the signal line 221 to the register 22 shown in FIG. Next, the contents of the register 22 are transferred from the signal line 201 to the control memory 20 in FIG. 2 to the address register 3 in FIG.
Store at the address set to 2. Next, the indicator (RGBSY) is set to "0", the contents of the address register 41 in FIG. Thereafter, it is checked again whether all words of the firmware instruction group specified by the register 42 of FIG. 4 have been stored in the control memory of FIG. If the firmware command group has not yet been stored in the control memory when the wait load firmware end command is issued, that is, if the indicator (LFWED) in Figure 7 is "0", firmware control is stopped. Then, the system waits until the indicator (LFWED) in FIG. 7 becomes "1".

As explained above, the present invention includes the operation of storing a part of the firmware instruction group stored in the main memory in the control memory by the load firmware instruction, and the execution of the software instruction following the load firmware instruction. It has the effect of being able to be done in parallel.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the main unit configuration of a data processing device and main memory used in an embodiment of the present invention, Figure 2 is a block diagram of the data path system around the control memory, and Figure 3 is a block diagram of the data path system around the control memory. Figure 4 is a block diagram of the peripheral address path system. Figure 4 is a block diagram of the peripheral area of the register that sets and manages the main memory address, control memory address, and number of firmware load words given by the load firmware command. Figure 5a is a block diagram of the peripheral address path system. A diagram showing the format of the load firmware instruction, b showing the main memory operand given by the load firmware instruction, and c showing the configuration of the control memory,
FIG. 6 and FIG. 7 are flowcharts of control operations for storing a part of the firmware command group stored in the main memory into the control memory, which is activated by issuing the load firmware command. 1...Main storage device, 11...Memory control unit, 12...Memory buffer unit,
13...Control store unit, 14...
Instruction execution unit, 15... instruction preemption unit,
20... Control memory, 21... Selector, 22...
Control memory read register, 23...Control memory write register, 24...Error check and correction information generation and correction circuit, 30-32...Address register, 33...Selector, 34...Conditional branch judgment circuit, 40, 41... ...Address register, 42...Register, 43...AND circuit.

Claims (1)

[Claims] 1: a rewritable control memory for storing a first group of firmware instructions; a storage means for storing a second group of firmware instructions; and storing a part of the second group of firmware instructions in the control memory. In a data processing device that is equipped with a load firmware instruction that is a software instruction, and in which execution control of the software instruction is shared between hardware control and firmware control, the software is activated by the load firmware instruction. means for storing part of the second firmware instruction group in the control memory while the hardware control is controlling the execution of instructions; and the second firmware instruction set activated by the load firmware instruction. A microprogram control device comprising means for reporting to software the completion of storing a part of a group of firmware instructions in the control memory.