SU482738A1 - Arithmetic unit - Google Patents

Description

ka 3 - with the second input of the element OR 6, the third input of which is connected to the nerve output of the local control unit 7, and the output to the first input of the element 8 and 8. The third output of the block 2 is connected to the first input of the element OR 9, the second additional the output of block 3 - with the second input of the element OR 9, the third input of which is connected to the second output of the local control unit 7, and the output - to the first input of the element "AND 10. The second input of the element" And 10 is connected to the third output of the local control unit 7 and to the second input of the element & 8, the output of which is associated with the third input the house of block 2. The output of the element “And 10 is connected to the third input of block 3. The device operates as follows. When performing operations like addition or subtraction, the numbers or their parts are put into the coordinate-address registers 4 and 5. In this case, depending on the length of the digit grid of numbers, the following cases are possible.

1. The bit size of the grid of the first and second components is less than or equal to the bit grid of the coordinate-address registers 4 and 5.

In this case, the numbers are entered in the coordinate-address registers 4 and 5. From the third output of the local control unit 7, an enable signal is output to the control input of the element "And 10", and from the second output of the unit 7, a demand signal is produced, which passes the series-connected element OR 9 and the element "AND 10" and goes to the third input of the permanent storage unit 3. The result of the addition as a sum is taken from the first output of the permanent storage unit 3 and is written to the result register 1.

2. The grid size of the first and second components is larger than the grid size of coordinate addresses 4 and 5.

In this case, the younger part of the first and second terms is entered into the coordinated address registers 4 and 5. From the third output of the local control unit 7, the enabling signal is output to the control input of the elements "And 8 and 10, and from the second output of the unit

7, a polling signal is generated, which, similarly to case 1, passes through the successively connected element "OR 9 and element" AND 10 and enters the third input of the permanent storage unit 3.

The result of the addition of the lowest part of the terms as a sum is removed from the first output of the permanent storage unit 3, entered into the result register 1 and removed from the output of the last. In this case, depending on the value of the result of the addition, a signal is produced at the first or second additional outputs of the permanent storage unit 3. The appearance of a signal at the first additional output means the presence of a transfer; the appearance of a signal at the second additional output is the absence of transfer.

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and the second term is entered into the coordinate-address registers 4 and 5, and depending on the presence of signals at the first or second additional outputs and another storage unit 3, the element 2 or 3 is polled through the element OR 6 or 9.

Similarly, depending on the presence of a signal on the second or third output of block 2, in the case of the latter,

 a polling signal will be generated for the element "OR 6 or 9, and in accordance with the selected scheme, a subsequent call to block 2 or 3 will occur. Thus, the process becomes cyclic and proceeds to those

IS until a prohibitive signal has been generated from the third output of the local control unit 7.

Intermediate results are successively removed from the output of the register of results 1.

Performing operations such as subtracting and preparing one of the items is reduced to performing the operation of addition. In this case, the process begins.

5 from the supply of the permitting signal from the third output of the local control unit 7 to the input of the elements “And 8 and 10 n of the generation of the interrogation signal to the third input of the element“ OR 6

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Subject invention

An arithmetic unit containing a result register whose input is connected to the output of a permanent storage unit,

5, the first input of which is connected to the output of the first coordinate-address register, and the second input - to the output of the second coordinate-address register, and a local control unit, characterized in that

0 increase in speed, it contains an additional constant memory block, the first input of which is connected to the output of the first coordinate-address register, the second input - to the output of the second coordinate 5 but the address register, the first output - to the additional input of the result register, the second output - to the first the input of the first OR element, the second input of which is connected to the first additional output of the memory storage unit, the third input to the first output of the local control unit, and the output to the nerve input of the first element This "And, the third output is with the first input unit: the second element" OR, the second input of which is connected to the second additional output of the permanent storage unit, the third input - with the second output of the local control unit, and the output - with the first input of the second element " And, the output of which

0 is connected to the third input of the permanent storage unit, and the second input is connected to the third output of the local control unit and the second input of the first ' element, the output of which is connected to the third input of the additional permanent storage unit.

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