SU578642A1 - Arithmetic device - Google Patents

Description

5 comparison of codes, command register 6, block 7 of the development of the conditional branch feature, first information bus 8, control bus 9, decoder 10, second information bus 11.

A monos arithmetic device circuit is the presence of a code comparison block. With the help of this block, a special VOC command is executed - a logical processing of the sluglable. The VOC operation provides a comparison of the contents of the part of the register of the arithmetic unit with the constant recorded in the command itself.

Arithmetic unit operates as follows.

On the VOS / bits command, the contents of register 3 are compared in block 5 with the constant K. coming from the register of command 6, and in case of inequality of codes, a sign of the conditional jump from 1 is produced (; block 7).

The number of bits to be compared / is written in the command as a binary code and the converter 4 is converted into a unitary binary code.

The structure of a VOC command is as follows: the VOC operation code is a constant K - the number of bits to be compared /.

In block 5, the code comparison under the influence of the VOC operation code, which enters as control signals from the decoder 10, from the command information from the register of command 6 is extracted the constant / С. Next, the number from register 3 is compared with the allocated constant / С. The number of bits to be compared is determined by the field: "1" in the code from the converter 4, in which the binary code of the command / is converted into a unitary binary code. The result of comparing the numbers from block 5 is supplied to block 7, in which the conditional transition flag is formed.

The proposed arithmetic unit saves the amount of permanent memory (ROM) and reduces the time to solve the problem by 5-10%. The economy of the volume of the ROM is achieved due to the fact that the co-A / C with which the comparison is made is recorded in the field of the command itself, and not in a specially allotted cell. The reduction of the task time in this case is due to the fact that there is no need to choose a special constant ROM, which takes an extra work cycle.

Claims (1)

Invention Formula An arithmetic unit containing a conditional non-spin feature generation unit, a decoder, a command register, a constant-to-unitary binary code converter, a register, a multiplication unit, an adder, whose inputs are connected to the first data bus, respectively, with the output the register of the arithmetic unit, with the output of the decoder and with the output of the multiplication unit, and the output of the adder is connected to the input of the register, whose input is connected to the second information bus, the inputs of the block multiplications are connected respectively to the first data bus, to the output of a constant converter to a unitary binary code, to the output of the decoder and to the register output, the inputs of the constant converter to a unitary binary code are connected respectively to the output of the decoder and to the nerve output of the command register, the second output of which is connected to the input the decoder, and the input is with the control bus, the output The conditional transition feature generation unit is connected to the input of the decoder, characterized in that, in order to improve speed and reduce equipment, a code comparison unit is inserted into the device, the inputs of which are connected respectively to the outputs of the register of commands, the register, the converter of the constant to the unitary binary code and the decoder, and the output - to the input of the block of development of the sign of the conditional transition.