SU557364A1 - Device for correcting basic registers with stack allocation of memory - Google Patents

Description

one

The invention relates to a computing technique.

A device is known for changing addresses in a stack memory, in addition to prtaema, output, acres registers, control unit and arithmetic unit 1.

A disadvantage of the known device is the great complexity and low speed.

The closest technical solution to the Proposed invention is a device for correcting basic registers in case of stack allocation of memory, comprising a receive register, a communication information generation unit, a program information generation unit, a control unit, an arithmetic unit, a basic register unit, the issuance register, the address register, the input of which is connected to the output of the arithmetic unit, and the output is connected to the output address buses of the device, the input of the reception register is connected to the input information bus the device, the inputs of the block forming the .and related information are connected to the outputs of the receive register, the arithmetic

block and block forming software information, the inputs of which are connected to the outputs of the reception register and arithmetic blocks, inputs of which are connected to the outputs of the block of basic registers and the generating unit of program information, the inputs of the block of basic registers connected to the output of the reception register and the output of the block forming software information, input of the register the output is connected to the output of the communication information forming unit, and the output is connected to the output information buses of the device; the inputs of the control unit are connected to the input device control bars and the control output of the base register unit, and outputs with the control inputs of the arithmetic unit, program information generation unit, communication information generation unit, base register unit, reception register, issuance register and address register.

Claims (1)

A disadvantage of the known device is its low response rate when correcting the base address registers. The purpose of the invention is to increase the speed of the device. The goal is achieved by introducing a static peppish display state memory, a decoder, input and output switches into the device, with the output of the program information generating unit through the serial decoder, the display state of the static chain and the output compressor connected to the input of the unit control, the memory of the display of the status of the stetic chain through the input switch is connected to the input of the device, the input of the output switch is connected to the control output of the block base registers. The drawing shows a diagram of the device. The device contains a reception register 1, a communication information generation unit 2, a program information generation unit 3, a control unit 4, an arithmetic unit 5, a base register unit 6, a output register 7, an address register 8, an output switch 9, a display state memory 10 static chain, descrambler 11, input switch 12, input information buses 13, control input buses 14, output information buses 15, output address buses 16 The device operates during static chain correction as follows. Based on the operation code and the control word, received respectively on the control and information input buses 13 and 14 of the device, the corresponding base register is selected in block 6 and the memory indicator 10. The register and indicator number is equal to the level of the program to be started. The base register is written to the address contained in the Stack Token Index, and to the indicator through the switch 12 is written O. The level number is decremented on the level number counter in block 6 by 1, the contents of the N-1st base register are read and compared with the address contained in the control A word is stored in block 6. The M9-.1th indicator is recorded 1. Coordinator 9 receives the address comparison signal from block 6, the level number comparison signal of the triggering subroutine and the contents of the level number counter, as well as the content of the indicator. If there is an address matching signal and a signal that the contents of the level number counter is less than the level number of the triggering procedure from block b, the correction process stops. If the contents of the counter of the number and the level turn out to be more, then it is again reduced by 1 and the indicator cell is requested at the received address. If it contains 1, then the caterer decreases again and the indicator is polled until the contents of the counter are equal to the level number of the triggering subroutine. Then, using the contents of the previous display register register, through register 8, the stack marker of the covering subroutine is requested. After receiving the stack marker on register 1, the base address from it is rewritten to the base address. the level register of the triggering procedure, and in the indicator of the same level through the switch 12 is recorded. The same address is requested to start the stack marker procedure. After receiving the base address from the stack marker, it is compared in block 6 with the contents of the base register. When comparing, the correction process ends. Thus, after the end of the correction in the memory of U, the runner is marked O, and the remaining levels of the static chain are marked 1. The unit in the i-th level indicates that the i + 1-th level is matched with the} th level, i.e. . These levels lie on one branch of the tree of static chains of the problem. Therefore, it is enough to check the contents of the indicators between the levels of the starting and starting subroutines, Zero in the indicator of the I -th ypoBw n means that the i -and and + 1-L levels may not be consistent, therefore, if the indicator O is equal, the query follows the stack marker, writing To the corresponding base register and the indicator of the address and 1, respectively. Further, the correction is performed as described above. The proposed device for controlling the correction of the base registers during the stack allocation of memory allows the analysis of the state zovyh register and find among them those that contain the necessary information and are not subject-compensation. Due to this, the number of calls to the operational memory for information is reduced by an amount equal to the number of base registers that are not subject to correction, i.e. the time for performing the correction is shortened and the speed of the device is improved. In addition, the queue is unloaded into the operative memory. As a result, performance is improved compared with known devices. The invention of the device for the correction of basic registers with stack allocation of memory