SU987624A1 - Device for modification of addresses at program debugging - Google Patents

Description

The invention relates to computing and can be used in specialized devices used in program execution.

A device is known comprising an address generation unit, a program transfer and protection unit, an index number register, a base register, an indicator register, a control unit, and a program start unit til.

The known device allows fast transfer of control from one program to another, which can be considered as a correction first, or as part of debugging commands.

Its disadvantages are the low speed and the need to add the appropriate or transfer control operators to the program text.

A device is known that contains a memory block in which a cell for storing a return address is allocated, an addressing block, an.-Address driver, a trigger, an AND element and a control unit. When a jump to the subroutine address causes blocking of the return address modification ,.

which is the address of the last command executed. Subroutines must have specific addresses, i.e. located in a certain area of memory C23.

The known device transfers control with return to other programs, which can also be considered as debugging groups.

10 commands or correct the text of the source program.

The disadvantage of this device is that to implement

15, a transition to a subroutine must explicitly indicate a transition command in the program, which leads to a slower execution of the program due to recognition and execution

20 of these commands, slows down program debugging due to the fact that the program text needs to be modified (recompiled) when these commands are added and removed, and it makes it very difficult

25 modification of the program recorded in the permanent memory due to the need to replace the ROM with each correction.

The purpose of the invention is to increase the efficiency of the device for modifying program addresses.

This goal is achieved by including the element NOT, the first and second AND elements, the OR element, the associative memory block, and the input of the device command end input connected to the element input and control device for modifying addresses when debugging programs. The input of the associative memory block, whose information output is connected to the first input of the OR element and to the input of the instruction address counter, the information output of the counter is connected to the first, the inputs of the first and second elements, AND to the input The interrogation block of the associative memory, the control output of which is connected to the second input of the second element AND, the output of the element is NOT connected to the second input of the first element AND, the output of which is connected to the second input of the element OR g and the output of the second element AND is connected to the third input of the element OR, the output of which is the address output of the device.

The drawing shows a block diagram of a device for modifying addresses when debugging programs.

The device contains a counter of 1 instruction addresses, a block 2 of associative memory, elements AND 3 and 4, an element OR 5 and an element NOT b. The device has an address output 7 and a control input 8 of the command side. In order to ensure the transmission of multi-bit address codes, elements 3-5 are intended to mean groups of corresponding identical elements.

The device works as follows.

Suppose, -TO, you need to insert a group of commands into the source code of the program, for example, debugging, without violating the source code of the program. For this, the insertion text is recorded in the free space in the program memory, and the address of the program, starting from which the insertion is performed, and the address of the start of insertion are entered in block 2. When the computer works together with the proposed device, after the completion of each command and increasing the content of counter 1 by a signal at input 8 polls block 2 and checks whether this address is the jump address for the insert. If it is, then from the read block 2 the start address of the insertion is transmitted to counter 1 and to address output 7 via the elements OR 5. If the address is not a jump address, then the signal from the control output of block 2 will allow the transfer of the contents of counter 1 to the address output 7 through elements 4 and 5. In the course of executing the same command, the contents of counter 1 are transmitted to output 7 through elements 3 and 5. In this case, block 2 is not polled. When the transition command to counter 1 is executed, the new address is entered, the transition address that is compared (as in the previous case) with the contents of block 2. If there is a match, the transition address is replaced with the new one from block 2, if not, it is transmitted to the address exit 7. The return from the insert is performed using the unconditional command, the transition of which ends the insert. In a similar way, it is possible to bypass a group of commands and replace some commands with others.

If the source program is located at. a fixed memory (ROM), then for the operation of the device it is necessary that a part of the address space of the computer belong to the RAM, i.e. part of the DOLKNR block is an operative memory having a continuous addressing with a constant.

Thus, by introducing into the device a block of associative memory, elements AND, OR, it is NOT possible to modify the addresses of the program during its execution without violating the original text of the program. This increases the speed of the device, since there are no costs for executing jump commands with a return, and the associative memory block is polled only between the execution of commands and can be combined, for example / with a poll of the computer's interrupt register.

The proposed device will make it possible to shorten the debugging times of programs several times, especially when modifying the programs recorded in the ROM, since the corrections will accumulate in the RAM and the ROM will be interchanged once for the whole group of corrections.

 the invention

A device for modifying the address when debugging programs, which contains a command address counter, characterized in that, in order to increase speed, a NOT element is entered into the device, the first and second AND elements, the OR element of the associative memory, and the end of the device command input are connected to the input of the NOT element and the control input of the associative memory block, whose information output is connected to the first input of the OR element and to the input of the command address counter, the information output of the counter is connected to the first inputs of the first and orogo elements and to the input and interrogation of the associative memory block, a control input coupled

to the second input of the second element AND, the output of the element is NOT connected to the second input of the first element AND, the output of which is connected to the second input of the OR element, the output of the second element AND is connected to the third input of the OR element whose output is the address output of the device.

Sources INFORMSCHIU,

taken into account in the examination

1. USSR Author's Certificate No. 479113, cl. G About F 9/40, 1973.

2. USSR author's certificate number 544965, cl. G 06 F 9/44, 1974 (prototype).

Claims (1)

Claim A device for modifying addresses during program debugging, which contains a command address counter, characterized in that, in order to improve performance, the device introduces a NOT element, a first and second AND element, an OR element, an associative memory block, and the input of the device command end connected to the input element NOT and the control input of the associative memory block, the information output of which. connected to the first input of the OR element and to the input of the counter of command addresses, the information output of the counter is connected to the first inputs of the first and second elements And and to the polling input of the associative memory block, the control input of which is connected to the second input of the second AND element, the output of the element is NOT connected to the second the input of the first AND element, the output of which is connected to the second input of the OR element, the output of the second AND element is connected to the third input of the OR element, the output of which is the address output of the device.