JPS6488839A - Addressing circuit - Google Patents

Addressing circuit

Info

Publication number
JPS6488839A
JPS6488839A JP62247090A JP24709087A JPS6488839A JP S6488839 A JPS6488839 A JP S6488839A JP 62247090 A JP62247090 A JP 62247090A JP 24709087 A JP24709087 A JP 24709087A JP S6488839 A JPS6488839 A JP S6488839A
Authority
JP
Japan
Prior art keywords
binary tree
tree search
alu
memory
sign
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247090A
Other languages
Japanese (ja)
Inventor
Yasushi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62247090A priority Critical patent/JPS6488839A/en
Publication of JPS6488839A publication Critical patent/JPS6488839A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform binary tree search processing in a short time by constituting an addressing circuit so that an address generator generates an address signal based on the sign output of an ALU (arithmetic logic circuit) which is generated at each time of the comparison operation of the ALU. CONSTITUTION:The threshold value of binary tree search is transferred from a memory 1 to a register 10, and data performing the binary tree search processing is stored in a register 9. Subtraction between registers 9 and 10 is performed by an ALU 7, and the sign of the subtraction result is stored in a sign flag 8. In case of binary tree search, an address S4 generated by an address generator 4 based on an instruction S1, a value S2 in the flag 8, and a value S3 in a memory pointer 2 is inputted to the pointer 2 through a selector 3. By this addressing circuit constituted in this manner, assignment of an intruction memory of a digital signal processing processor for the binary tree search processing is reduced.
JP62247090A 1987-09-30 1987-09-30 Addressing circuit Pending JPS6488839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247090A JPS6488839A (en) 1987-09-30 1987-09-30 Addressing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247090A JPS6488839A (en) 1987-09-30 1987-09-30 Addressing circuit

Publications (1)

Publication Number Publication Date
JPS6488839A true JPS6488839A (en) 1989-04-03

Family

ID=17158280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247090A Pending JPS6488839A (en) 1987-09-30 1987-09-30 Addressing circuit

Country Status (1)

Country Link
JP (1) JPS6488839A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656599A2 (en) * 1993-11-04 1995-06-07 Licentia Patent-Verwaltungs-GmbH Transponder and data communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656599A2 (en) * 1993-11-04 1995-06-07 Licentia Patent-Verwaltungs-GmbH Transponder and data communication system

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