JPS6341967A - Direct memory access transfer circuit - Google Patents

Abstract

PURPOSE:To attain the transfer with a simple constitution without using a CPU for an address control by executing the direct access transfer between memories with a hardware at a pattern image. CONSTITUTION:In a head address memory circuit 3, first, a head address HA of pattern data by a main memory device 2 is stored, after the transfer is started, only the setting address of an updating address setting circuit 4 is operated and updated from the head address HA and the data are transferred to the main memory device 2. At this time, the updating address setting circuit 4 generates an updating address so that the pattern data of a memory 1 can be preserved. Namely, when the data are stored up to an address width a1 of the pattern data, the updating address setting circuit 4 sets a transfer address width (a2 + a3) of the main memory device 2 except the address width of the pattern data and updates it successively from a new address. Thus, the address control to transfer original picture pattern data to the main memory device 2 can be executed.

Description

[Detailed Description of the Invention] [Summary] The present application provides a direct memory access method that can control the wide area memory area of the transfer destination when original pattern data such as images is transferred to a specific storage area of the main storage device. (DMA
) discloses a transfer circuit.

[Industrial application field]

The present invention relates to a direct memory access transfer circuit, and more particularly to a transfer address control circuit when pattern data such as image data is directly stored in a wide area main storage device.

When reading pattern data such as image data from a memory in which the data is stored, the most common method is to perform processing using data surrounding the data bits. If it is data, it is desirable to transfer it as a pattern image because surrounding data can be easily extracted.

[Conventional technology]

The conventional memory access method for transferring pattern data is to sequentially store each dot while incrementing the transfer destination address under the control of the CPU (firmware).

[Problem that the invention seeks to solve]

However, in such a conventional method, since the pattern image is not considered in any way, it is stored separately in the main memory, and cannot be stored all at once as a pattern image in the main memory. Therefore, it has been difficult to extract data surrounding the bits in the original pattern.

Therefore, an object of the present invention is to obtain a direct memory access transfer circuit that realizes data transfer without destroying the pattern image.

[Means for solving problems]

To achieve the above object, a direct memory access transfer circuit according to the present invention when transferring data from a memory storing pattern data to a main memory device is shown in principle in FIG. Memory, 2 is a main memory, 3 is a start address storage circuit that stores the start address of pattern data in the main memory 2, and 4 is an update that sets an update address of the start address storage circuit 3 to save the pattern data. An address setting circuit 5 is an arithmetic circuit that calculates both the address values of the start address storage circuit 3 and the update address setting circuit 4 and sets them in the start address storage circuit 3.

[For production]

Fig. 1 and Fig. 2 illustrating the transfer image according to the present invention.
In the figure, the start address storage circuit 3 initially stores the start address HA of the pattern data in the main memory 2, and after the start of transfer, the arithmetic circuit 3 only stores the setting address of the update address setting circuit 4 from the start address HA. 5, the data is transferred to the main storage device 2 while being updated. At this time, the update address setting circuit 4 generates an update address so that the pattern data in the memory 1 is saved.

That is, when the address width a1 of the pattern data is stored, the update address setting circuit 4 sets the transfer address width (a2+2) of the main memory 2 other than the address width of the pattern data.
3) and sequentially update again from the new address. This allows address control for transferring the original pattern data to the main memory bag M2.

〔Example〕

Hereinafter, the direct memory access transfer circuit of the present invention shown in FIGS. 1 and 2 will be explained along with the embodiment shown in FIG. 3.

In FIG. 3, the start address storage circuit 3 of FIG. 1 is, for example, a register, and this start address is set in advance by the CPU. The update address setting circuit 4 includes an update register 41 that stores "1" when the pattern data continues, and stores "2" when the pattern data is transferred one by one, and an update register 41 that stores the address width of the pattern data. It is composed of an address width register 42 that stores the transfer address width in the main memory other than the address width register 42, and a selector 43 that switches from the update register 41 to the address width register 42 when only the address width of pattern data is updated. .

Further, the arithmetic circuit 5 is an addition/subtraction circuit that adds and subtracts the output of the head address storage circuit 3 and the output of the update address setting circuit 4.

Next, the operation will be explained.

Now, an area for transferring the original pattern in the memory 1 is secured in advance in the main storage device 2, and the selector 43
A PU (not shown) selects register 41 at the start of transfer, and selects register 42 when transfer reaches end point A of address width a1 of pattern data shown in FIG.

Therefore, at the start of transfer, if "1" is stored in the register 41, for example, "1" is calculated at the start address indicated by the register 3 in the addition/subtraction circuit 5. In this case, if the addition/subtraction circuit 5 is an addition circuit, "1" is added.

When the transfer progresses to point A in this way, the selector 43 is switched from register 41 to register 42 under the control of the CPU, and the address sum of transfer address widths a2 and a3 shown in FIG. 2 is added to the address value of register 3. The data is updated and the series of transfers is performed again.

In this way, the original pattern in memory 1 is stored in main memory 2.
will be transferred as a pattern image.

Note that the address value stored in the update register 41 can be changed in various ways. This means that, for example, when data is transferred from an 8-bit (1 byte) memory memory IJ1 to an 8-bit main memory 2, the stored address value may be "1"; ) configuration, the address is updated after four data transfers, so "4" will be stored.

In addition, when the arithmetic circuit 5 is a subtraction circuit, in FIG. 2, point A is on the opposite side of the start address HA (address width a
3 side), and will be stored in the main storage device 2 as an inverted image. In this case, the data transferred to the main memory device 2 is LSB compared to the case of an adder circuit.
(least significant bit) and MSB (most significant bit) are reversed.

〔Effect of the invention〕

As described above, according to the direct memory access transfer circuit of the present invention, since the direct access transfer between memories is performed by hardware using a pattern image, transfer can be performed with a simple configuration without using a CPU for address control J. Effects can be obtained.

[Brief explanation of the drawing]

Figure 1 is a principle block diagram of a direct memory access transfer circuit according to the present invention, Figure 2 is a diagram showing a transfer image according to the present invention, and Figure 3 is an implementation of the principle block diagram of the direct memory access transfer circuit of Figure 1. 1 is a circuit diagram showing an example. 1 to 3, 1 is a memory, 2 is a main memory, 3 is a start address storage circuit, 4 is an update address setting circuit, 5 is an arithmetic circuit, 41 and 42 are registers, and 43 is a selector. . In the drawings, the same reference numerals indicate the same or corresponding parts. Patent applicant Tsuji Fuji Agent Patent Attorney Co., Ltd.
Mori 1) Hiroshi (1 other person) Figure 2 shows the transfer image for this defense.

Claims (4)

[Claims] (1) A direct memory access transfer circuit for transferring data from a memory (1) storing pattern data to a main storage device (2), the beginning of the pattern data in the main storage device (2). A start address storage circuit (3) that stores an address; and an update address setting circuit (4) that sets an update address of the start address so as to save the pattern data.
A direct memory access transfer circuit comprising: a calculation circuit (5) that calculates values of the start address and the update address and sets them in the start address storage circuit (3). (2) The update address setting circuit (4) stores an update register (41) that stores an address for continuous update.
), an address width register (42) that stores a transfer address width of the main memory (2) other than the address width of the pattern data, and an address width register (42) that stores a transfer address width of the main memory (2) other than the address width of the pattern data; 2. The direct memory access transfer circuit according to claim 1, further comprising a selector (43) for switching from (41) to the address width register (42). (3) Claim 1, wherein the arithmetic circuit (5) is an addition circuit that adds the address of the update address setting circuit (4) to the address from the start address storage circuit.
The direct memory access transfer circuit according to item 1 or 2. (4) Direct memory access according to claim 1 or 2, wherein the arithmetic circuit (5) is a subtraction circuit that subtracts the address of the update address setting circuit from the address from the start address storage circuit. transfer circuit.