JPS63114369A - Picture signal processing device - Google Patents

Abstract

PURPOSE:To facilitate the switching at a high speed by using an input data write end signal and a stored input data read end signal so as to apply connec tion changeover to 1st and 2nd buffer memories. CONSTITUTION:The transfer word number per line of a data 5 inputted from an external device and a maximum accommodated line number of a buffer memory are set respectively to a word counter and a line counter 10. When the count of the word counter 9 is finished, an MPU1 commands the storage address of the next 2nd line to an address register 8 and when the data of the 64th line is inputted similarly, a switching signal 32 is generated from the line counter 10 and the changeover circuit 11 connects the buffer memory 15 to the position of the MPU1 and the buffer memory 14 to the external device side. Moreover, when the data of the buffer memory 15 is transferred to an external computer via a DMA 2, the MPU1 informs a switching signal 31 to the changeover circuit 11 to switch the buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing device such as a facsimile or scanner device.

BACKGROUND ART When a large amount of data is imported into a computer system from a facsimile machine or an external device, careful consideration must be given to how to store the data in the limited memory area of the computer system. For example, if 16 bits of data are collected every 10 μsec, 0.2M data will be collected in 1 second.
The amount of data is in bytes. Since the memory will eventually overflow, the data must be sequentially stored in an external auxiliary memory (for example, a magnetic disk device). Furthermore, data must continue to be captured even during this storage.

In such a case, it is sufficient to prepare two or more data buffer memories in the memory and perform collection and transfer alternately. For example, when operating with DMA, use chain mode etc. to store multiple data buffer memories. Collect data sequentially and seamlessly into a buffer. Each time the transfer to each buffer is completed, storage to the disk starts, but at this time, the input data is
Starting to write to the next buffer. In this way, data collection and transfer is performed by alternately using double buffer memories or by using a plurality of double buffer memories in a ring shape.

The problem that the invention aims to solve As above, using double buffer memory.

In a control configuration in which one side is read while the other side is written, conventional technology does not allow bidirectional access of writing/reading from the external device side and writing/reading from the computer side. unable to do so, and
It was not possible for the external device to notify the computer of the timing of switching buffer memories upon completion of writing to one buffer memory and of connecting to the other buffer memory. In particular, in the case of high-speed data transfer, the above timing during the switching cycle is necessary.

In view of the above problems, the present invention provides an image signal processing device that enables high-speed buffer switching control.

Means for Solving the Problems The present invention provides a method for switching between the first and second buffer memories.
address setting means for setting the storage address of input image information in the buffer memory for each line; word counting means for counting the number of input transfer words for each line; and upon completion of counting by the word counting means, address instruction means for sequentially instructing and updating storage addresses in the buffer memory; line counting means for counting the number of lines upon completion of said word counting; and a buffer switching signal generated upon completion of said line counting means; buffer control means for generating a switching connection request signal in response to a buffer switching signal generated by a control means connected to the buffer memory; and four types of responses generated from each of the buffer memories. The double buffer is switched by the signal via the buffer control means.

Function The present invention uses a buffer control unit that controls switching of a double-configured buffer memory for continuous data input from an external device to count the number of words per line of the input data, and calculates the necessary amount of data by counting the number of words per line of the input data. The first,
The connection of the second buffer memory is switched, and when switching between the first and second buffer memories, the state is managed on the control means side using a connection request signal and a connection response signal, so it is fast and easy. control over buffer memory. Further, since the address for storing the image signal for each line of the buffer memory can be set from the MPU side when the word counter finishes counting, it is possible to freely configure the layout of the buffer memory.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an image signal processing device in an embodiment of the present invention.

In FIG. 1, 1 is an MPU unit, 2 is a DMA unit that controls high-speed data transmission and reception with an external computer, and 3 and 4 are
1 is a system bus of the MPU 1, and 5 is a signal line for inputting data from external equipment and controlling the same. 6 is a buffer control unit that controls switching and connection of the buffer memos 1J14 and 15 in the image buffer memory unit 13; 7 is a data buffer that provides data information to the image buffer memo 9 unit 13; 8 is the image buffer memory unit 13; an address register with a built-in address counter that gives address information to 9;
is a word counter that counts the number of transferred words for each line of input data from an external device; 10 is a word counter 9
This is a line counter that subtracts the number of lines one by one upon completion of counting and generates a request signal for buffer switching. 1
Reference numeral 1 designates a switching circuit for the image buffer memory section 13, which switches the image buffer memory section 13 in response to a switching signal 32 from the line counter 10 and a switching signal 31 from the MPUI.

On the other hand, double buffer memories 14 and 15 are arranged in the image buffer memory section 13. 16.17 is a gate circuit that switches the buffer memory 14.15, 18 is an input data signal line 5 from an external device.
19 is an address bus and data bus signal line necessary for writing to the image buffer memory section 13 from the outside, and 20 to 27 are switching circuits 11. A control signal line 20 is connected to the buffer memory 14 from an external device (EXTRBQO), 21
22 is a connection request signal line (EXTREQl) from the external device to the buffer memory 15, and 22 is a connection request signal line (MPUREQ1) from the MPUI to the buffer memory 14.
O), 23 is a connection request signal line (MPUREQl) from the MPUI to the buffer memory 15, and 24 is a response signal (EX
25 is a response signal (EXTRDYI'') to an external connection request from the buffer memory 15;
26 is a response signal (MPURDYO) to the MPU connection request from the buffer memory 14, and 27 is a response signal (MPtJ) to the MPU connection request from the buffer memory 15.
RDY1). Reference numeral 28 denotes an input signal to the address register 8, which is a strobe signal input together with the input signal 5 from an external device. 29 is the number of words set in the word counter 9 from the MPU 1, and this value is set to the same value as the number of words for each line of the signal input from the external device. 30 is a parameter set in the counter 10 that counts the buffer switching period; 31 is a buffer switching signal from the MPU 1 and a response signal from the buffer memory;
32 is a buffer switching signal from the line counter 10;
3 is a signal indicating data start storage address information of the buffer memory set in the 7 address register 8 from the MPUI;
34 is a signal by which the MPUI monitors the completion of counting from the word counter 9. The operation of the above configuration will be described in detail below.

Now, input data from the external device to image buffer memory section 1.
3, the buffer memory 14 is first transferred to the MPUI from the MPU 1 side via the switching circuit 11 of the buffer control unit 6.
and connect the buffer memory 15 to the external device side.

In this case, the connection request signal is (MPUREQO)2
In response to this, a response signal (MPURDY O) 24 is sent from the buffer memory 14 to the MPU1.
will be notified.

On the other hand, since the buffer memory 15 is not connected to the external device side, a response signal (EXTRDYl) 25 is notified to the MPUI in response to the connection request signal (EXTREQ 1 ) 21. At this time, the number of words transferred per line of data input from the external device and the capacity of the buffer memory are
Word counter 9 indicates the maximum number of lines that can be accommodated.
is set in the line counter 10. For example, the buffer memory capacity is 128KBYTE and the transfer word is IKW.
If it is ORD, the value of the line counter lO will be a maximum of 64 lines.

In such a state, when input data signal 5 is taken into image buffer memory section 13 from an external device, the storage address of the buffer memory of the first line is set from MPU 1 to address register 8 via signal line 33. . Therefore, in response to the input data write strobe signal 28, the address counter in the address register 8 operates to store data at a predetermined address in the buffer memory 14 via the bus signal line 19. When input data continues to arrive in this manner, the word counter 9 is decremented and the trigger pulse when the value becomes 0'' causes the line counter 10 to decrement.
In this case, the MPUI is monitoring the control signal line 34,
When the word counter 9 completes counting, it indicates the storage address of the buffer memory for the second line of the primary. Similarly, when 64 lines of data are input, a buffer switching signal 32 is generated from the line counter 10 and is notified to the switching circuit 11. Therefore, from the switching circuit 11 to the buffer memory section 13, the buffer memory 15 is
At the same time as connecting to the I side, connect the buffer memory 14 to the external device side.

In this case, the connection request signal is the aforementioned (EXTREQO)2
0, and in response, a response signal (BXTRDYO') 24 from the buffer memory 14 is notified to MPtJl. On the other hand, since the buffer memory 15 is connected to the MPU 1 side, its connection request signal (MPUREQl) 23
In response, the response signal (MPURDYl”) 25 is
will be notified.

When the MPU 1 finishes transferring the data in the buffer memory 15 to the external computer via the DMA unit 2, that is, when it finishes reading the contents of the buffer memory 15, the MPU
A switching signal 31 from I to the buffer is notified to the switching circuit 11, the buffer memory is switched, and the storage address of the buffer memory for each line is sequentially set from the MPUI in the same way as described above. By sequentially repeating this operation, it is possible to transfer a large amount of data at high speed to an external computer system via the MPU.

Figure 2 shows input data from an external device and buffer switching control. In Figure 2, 40 is a synchronization signal that accompanies input data, 41 is input image data,
42 is the end output signal of the word counter, 43 is the line count value, 44 is the end output signal of the line counter and a buffer switching request signal, 45 is the state in which buffer 7 memory 1 is connected, 46 is the state in which buffer memory 2 is connected This indicates the state in which the As is clear in the same figure.

According to the number of words and number of lines parameters set from the MPU side, the storage start address of the buffer memory is set sequentially for each output of the signal 42, and the line end signal 4 is set.
4, the double configuration buffer 7 memories are switched and controlled respectively. In the figure, first, the buffer memory 1 is connected, and the line end signal 44 indicates that the buffer memory 2 is connected.

As described above, according to this embodiment, even though two buffer memories are prepared, only one buffer memory is connected from the MPU side via the system bus in terms of hardware.
Since it is a surface, buffer switching control can be performed at high speed in accordance with reading and writing speed signals from the MPU side and the external device side, respectively.

Furthermore, in the case of the above embodiment, the image buffer memory section 13 is used only for writing from the external device side and for reading only from the MPU side, but it is also possible to use it in the opposite manner, and the image buffer memory section 13 Bidirectional access is possible.

Furthermore, the system shown in this embodiment is most suitable for receiving input data from devices such as scanners and facsimile machines, and the buffer switching cycle is based on the management of the number of input transfer words per line and the number of lines described above. can be easily controlled.

Effects of the Invention As described above, the present invention allows data input from an external device to be buffered using the number of transfer words for each line, parameters managed by the number of lines, and storage start address parameters of the buffer memory for each line. Drive the control unit,
In addition, the collection and transfer of input data through the interaction of the double-configured buffer memory can be carried out quickly and easily by the write end signal of one buffer memory and the read end signal of the other buffer memory generated in the buffer control unit. It is possible to control the

Furthermore, by sequentially setting the storage start address in the buffer memory for each line from the MPU side, it is possible to arrange the input image data in the buffer memory in a free layout structure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of an image signal processing apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing the timing of main parts of the apparatus. 1... MPtJ, 2... DMA, 6... Buffer control unit, 7... Data buffer % 8... Address register, 9... Word counter % 10...
Line counter, 11... Switching circuit, 13... Image buffer memory, 14.15... Buffer memory, 1
7.18 ---Priority gate circuit.

Claims (1)

[Claims] When switching between the first and second buffer memories, an address setting means for setting a storage address in the buffer memory for each line of input image information, and a word counting means for counting the number of input transfer words for each line. , address instruction means for sequentially instructing storage addresses in the buffer memory for each line upon completion of counting by the word counting means;
Upon completion of the word counting, a line counting means counts the number of lines, a buffer switching signal generated upon completion of the line counting means, and a buffer switching signal generated by a control means connected to the buffer memory. , a buffer control means for generating a switching connection request signal, and each response signal generated from the first or second buffer memory causes the first and second buffer memories to be connected via the buffer control means. An image signal processing device that switches between two buffers.