JPS6346630B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal conversion method that converts the signal form of data between input and output using a plurality of buffer memories.

Conventionally, in order to retrieve data by performing signal conversion and speed conversion of data between the input and output using multiple buffer memories, each buffer memory is conventionally provided with an input/output address counter, and the input/output control of each buffer memory is controlled separately. I was going to

Therefore, the operation of the address counter must be made different between data input and data output. In addition, the control becomes complicated, and since the control systems for each buffer memory are independent, circuits with the same function are required for each buffer memory, which has the disadvantage of increasing the number of circuit elements and making the device expensive. Furthermore, since the addressing lines of each buffer memory are independent, each buffer memory and its control system cannot be arranged together on a common printed circuit board, resulting in an increase in device volume.

The present invention provides a signal conversion method that eliminates the drawbacks of the prior art, reduces the number of circuit elements, reduces costs, and increases the packaging density of circuit elements configured on a printed circuit board to make the device more compact. The purpose is to provide

In order to achieve this object, the present invention provides a line scanning address counter and a multi-scanning address counter for converting the signal form of data in common in each buffer memory, so that they can be used by switching to each buffer memory. It is characterized by

Hereinafter, an example in which an embodiment of the present invention is applied to a facsimile machine will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block configuration diagram of an embodiment of the present invention, where BM1 and BM2 are buffer memories for orthogonal transformation, AM is an address multiplexer, CD is a chip select decoder, RAC is an address counter for refresh, and ACA is an address counter for multiple scanning. , CCA is a chip specification address counter for multiple scanning, ACB is an address counter for line scanning, CCB is a chip specification counter for line scanning,
RDD is a data distribution circuit, WDS is a data selector,
BMC is a buffer memory write/read control circuit, and CPG is a clock pulse generation circuit.

The facsimile machine to which the present invention is applied includes, at the time of transmission,
The image information is sequentially read in the sub-scanning direction, for example, 32 bits at a time in the main scanning direction, for example, at every 1728-bit position, converted into image information of 1728 bits in the main scanning direction in a buffer memory, compressed, and transmitted. . Also, during reception, the received data for each line is expanded, converted into image information for 32 bits in the sub-scanning direction in a buffer memory, extracted, and sequentially recorded at every 1728-bit position in the main scanning direction.

Therefore, in this embodiment, the buffer memory BM
Each memory chip of BM1 and BM2 is composed of (32×1728) bits, and during transmission, multiple scanning is performed every 32 bits and data is sequentially written. On the other hand, from the buffer memory where the data was written,
Data is read out by line scanning every 1728 bits. Also, when receiving, buffer memory BM
1, data is written to BM2 by line scanning, and data is read by multiple scanning.

Along with this, each buffer memory BM1, BM
Address counters RAC, ACA, and ACB are configured according to their functions and used commonly for each memory in order to write, read, and refresh 2.

Further, the buffer memories BM1 and BM2 are inputted with multi-scan data from the image information reading scanner during transmission and line scan data from the data expander during reception by the data selection circuit WDS.

On the other hand, from buffer memories BM1 and BM2, line scan data is output to a data compressor during transmission, and multi-scan data is output to a recording device during reception via a data distribution circuit RDD.

Each buffer memory BM1, BM2 is switched by the output of the buffer memory write/read control circuit BMC.

The clock pulse generation circuit CPG is a circuit for operating each address counter, multiplexer, etc. at a predetermined timing.

Next, the operation will be explained with reference to the time charts of FIGS. 2 and 3.

The signal conversion operation is almost the same during transmission and reception, the only difference being whether the input/output data of the buffer memory is line scanning data or multi-scanning data, so the operation during transmission will be explained below. do.

During transmission, the data selection circuit WDS transfers data from the image information reading device to buffer memories BM1 and BM2.
Enter. Further, the data distributor RDD outputs data from the buffer memories BM1 and BM2 to the data compressor.

Buffer memory write/read control circuit
The BMC controls the buffer memories BM1 and BM2 in response to the output of the line scanning chip designation counter CCB and the multi-scanning end signal, that is, the effective scanning end signal of the scanner that moves in the main scanning direction while performing batch scanning for 32 lines in the sub-scanning direction. Switch alternately.

As shown in FIG. 2, system clocks a, b, and c, which serve as a reference for operating this system, are input to the clock pulse generation circuit CPG.

Clock a has a cycle twice that of clock b, and one cycle corresponds to one bit of read data. Further, one cycle of clock b corresponds to one bit of write data.

When a data read request d from the data compressor and a data write request from the reader are input to the clock pulse generation circuit CPG at the timing shown in the figure, the multi-scanning clock CP2 is generated from the circuit CPG at the timing CP2=..., and the chip designation counter CCA is generated. Enter. Also, along with this,
As shown in FIG. 3, a signal CP4 is generated every time data is input for one scanning period of multiple scanning, that is, 32 bits, and is inputted to the address counter ACA.

At this time, assuming that the memory BM1 is in the write mode and the memory BM2 is in the read mode by the control circuit BMC, the data WD1 input to the memory BM1 during one cycle of clock b is the memory chip specified by the counter CCA. Written to the address specified by counter ACA.

In addition, a line scanning clock CP3 is generated from the circuit CPG at the timing of CP3=d・a・b・c,
Input to addressing counter ACB. Along with this, the line scanning period is 1728 as shown in Figure 3.
A signal CP5 generated every time a bit of data is output is input to a line scanning chip designation counter CCB.

As a result, the read data outputted from a predetermined address of a predetermined memory chip of the memory BM2 during a logic "1" of CP3 is held for one cycle in the circuit RDD by the strobe signal generated at the timing of CP3, and the data RD1, RD2, Output RD3,... to the compressor.

Further, a refresh clock CP1 is generated from the circuit CPG at the timing of CP1=b. It is input to the address designation counter RAC, and predetermined address data is refreshed while the logic is "1".

Therefore, each addressing counter RAC,
ACA and ACB perform time-division operations based on clocks CP1, CP2, and CP3 at the timing shown in FIG. Line scanning data is read from.

The chip designation counter CCB uses the signal shown in Figure 3.
A count operation is performed at the falling edge of CP5, and memory
The control circuit BMC is informed that BM1 is filled with data and memory BM2 is empty. As a result, the control circuit BMC switches the memory input/output operation mode, and this time switches the memory BM1 to the read mode and the memory BM2 to the write mode. As a result, buffer memory BM is used during transmission.
1. Multiple scan data input to BM2 is orthogonally transformed into line scan data and output.

In this way, the addressing counter RAC, when performing functions such as multiple scanning and line scanning,
By providing ACA, ACB, etc. in common to each buffer memory and performing time-division operation, there is no need to provide redundant circuits with the same function.
The configuration is simple and inexpensive. Also, each memory BM
1. Since the addressing line of BM2 can be shared, the control system and each memory can be placed together, making the layout on the board easier and increasing the packaging density.

In the above embodiment, an example was explained in which the present invention is applied to a facsimile device that performs transmission and reception, but it goes without saying that the present invention is not limited to this, and can be applied to a facsimile device that is only used for sending or receiving.

Further, the present invention can also be applied to the case of converting signal formats between apparatuses with different scanning methods, such as recording apparatuses other than facsimile machines.

In addition, each buffer memory is static RAM.
In this case, a refresh counter is not required. However, in systems that require large amounts of memory, it is more advantageous to use dynamic RAM to increase memory packaging density.

Further, in the above embodiment, all the buffer memories are refreshed at the same time, but the refresh time may be divided and the memories may be divided and refreshed.

Furthermore, the data read from the buffer memory can be read from different addresses.

Furthermore, depending on the input form of each data read/write request, the read/write cycle can be accelerated by intensively performing refresh.

In addition, each address counter RAC, ACA, ACB
Clock CP1 for operating time-divisionally,
It goes without saying that the timing of occurrence of CP2 and CP3 can be set arbitrarily.

As described above, according to the present invention, a line scanning address counter and a multi-scanning address counter for converting the signal form of data are provided in common in each buffer memory, and are used by switching to each buffer memory. Therefore, the circuit configuration is simplified and the number of circuit elements used can be reduced, and each memory and control system can be placed together, increasing the packaging density and making the device compact and inexpensive. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal conversion device showing one embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining its operation. BM1, BM2... Buffer memory, AM...
Address multiplexer, CD...chip select decoder, RAC...addressing counter for refresh, ACA...addressing counter for multiple scanning, CCA...chip specifying counter for multiple scanning, ACB...addressing counter for line scanning, CCB: line scanning chip designation counter, WDS: data selection circuit, RDD: data distribution circuit, BMC: buffer memory write/read control circuit, CPG: clock pulse generation circuit.

Claims (1)

[Scope of Claims] 1. A signal conversion method comprising a plurality of buffer memories, in which data is written in one of the plurality of buffer memories, while data written in the buffer memory is read out from another buffer memory, thereby converting the signal form of the data and extracting the data. , a line scanning address counter and a multi-scanning address counter for signal conversion of the data are provided in common to the plurality of buffer memories, and each of the address counters is switched and used according to the operating state of the buffer memory. This signal conversion method is characterized by the following. 2. The signal conversion method according to claim 1, wherein writing and reading of the plurality of buffer memories is controlled in a time-division manner by operating each of the address counters in a time-division manner. 3. The signal conversion method according to claim 1, wherein the buffer memory is a buffer memory used for both transmission and reception in a facsimile device.