JP2853636B2 - Dual-port image semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dual-port image semiconductor memory device, and more particularly to a dual-port image semiconductor memory device having a plurality of transfer gates and serial registers.

[0002]

2. Description of the Related Art A conventional dual-port image semiconductor memory device has a set of transfer gates and a data register on each of an upper column (column) side and a lower column side. Column (0-2
The serial port at address 55 (or the lower column (addresses 256 to 511)) cannot transfer data to and from the memory cell array unit, but instead stores the serial number of the lower column (or upper column) in a state where data is not input / output. The port had a split data transfer function capable of transferring data to and from the memory cell array unit irrespective of the column on which data is being output. In a serial port that outputs data in response to a clock signal input, the internal address space is divided into n (n is a power of 2 in decimal) equal parts, and the upper and lower columns (or lower columns) are divided by the divided address points. ) Has a binary boundary jump function that can skip an access point to a lower column (or an upper column).

With these two functions, a tile map technique, which is one of the address management methods in the screen display of the host system, can be realized.

An address management method at the time of screen display in a general CRT display device is called a scan line map method, and a scan line on a CRT display screen and a row (row) address of a dual-port image semiconductor memory device are paired. One or one-to-many correspondence is adopted, and as many data as possible on the row address of the dual-port image semiconductor memory device are arranged on the same scan line. However, in this method, when rewriting of pixel data occurs, rewriting in the scan line direction continuously accesses high-speed page mode access of the dual-port image semiconductor memory device or similar data on the same row address. High-speed access is possible by the access method, but when rewriting occurs in the vertical direction with respect to the scan line, the high-speed page mode access or similar access method for successively accessing data on the same row address cannot be used. Random access. At the time of this random access, the precharge time of the word line unique to the dual-port image semiconductor memory device is required in each cycle, so that the rewriting performance of pixel data (hereinafter referred to as drawing performance) is different from that in the scan line direction. It is significantly lower than the comparison.

[0005] A method for preventing the deterioration of the drawing performance is a tile map technique, which is one of address management methods for screen display. This tile map technique can be implemented using the traditional 128K
Consider a case in which a 2M-bit dual-port image semiconductor memory device having a word × 8-bit configuration is used to display data in 256 colors on a 1024 × 768 dot 72 Hz non-interlace CRT display device.

FIG. 3 shows an example of a dual-port image semiconductor memory device used in this CRT display device. Although not shown in FIG. 3, one address specified by a row address and a column address stores 8-bit data for one word, and the data for one word is used as a basic unit for simultaneous and parallel operations. Is transferred, transferred, and input / output.

The dual-port image semiconductor memory device 100 stores two units of data having a predetermined number of bits (256 × 8 bits) as one unit, in the lower row (addresses 0 to 255) and the upper row in the same row. Side (256-511)
And a memory cell array unit 1 for reading and writing two units of data for a selected row including a plurality of rows stored corresponding to the column address of one of the plurality of rows of the memory cell array unit 1 according to a row address signal. Row address buffer circuit 2 and row address decoder 3 for selecting a row
A column address buffer circuit 4 for taking in and outputting a column address signal, an input buffer circuit 11, an input data control unit 12, an output buffer circuit 13, a column address decoder 14, and a sense amplifier circuit 15 constituting a RAM port; A stop register 21 and a TAP register 22 for setting and outputting a stop address Asp and a start address Ast by taking in a column address signal from the column address buffer circuit 4 and a predetermined column address provided in correspondence with a lower column address of the memory cell array unit 1. Correspond to the lower transfer gate TGa and the lower data register DRa for transferring and transferring data to and from the lower column address of the row selected at the timing of the row, and the upper column address of the memory cell array unit 1. Provided and provided An upper transfer gate TGb and an upper data register DRb for transferring and transferring data to and from the upper column address of the row selected by the imaging, and a lower data register DRa and an upper data register DRb. A serial port / column decoder 25 and a serial port / IO bus circuit 26 for transmitting / receiving data between them and inputting / outputting serial data to / from an external circuit via a serial output buffer circuit 27 and a serial input buffer circuit 28; Address A
In accordance with the sp and the start address Ast, and in synchronization with the serial clock signal SCK, input / output control of serial data by the serial port / column decoder 25 and the serial port / IO bus circuit 26, and between lower and upper column addresses And a serial address control unit 23x for controlling the jump operation of the access point.

Using four dual-port image semiconductor memory devices 100, a CRT display system of a higher system as shown in FIG. 4 is constructed. FIG. 5 (A) to (C)
As shown in FIG. 3, the CRT display screen 3 of the CRT display unit 300
01 is divided into a plurality of rows (48 rows) and a plurality of columns (16 columns) of tiles having 64 dots in the horizontal direction and 16 lines in the vertical direction, and as shown in FIG.
Is assigned to one of the lower and upper column addresses of one row of the memory cell array unit 1.
Correspond to the unit data. Also, 64 dots (4 × 1
In order to map to a tile TI of (6 dots) × 16 lines, data of 512 columns is divided into 16 columns (one line of one tile TI), and four dual-port image semiconductor memory devices 100-1 The data of the lower or upper column address of one row of 16 columns × 16 of 100 to 100 to 4 is made to correspond. The binary boundary jump function is executed by performing the delimitation every 16 columns by the stop address Asp from the Stop register 21.

With such a correspondence, each tile TI
Dual-port image semiconductor memory device 1 corresponding to four dots at mutually corresponding positions on the same scan line
Addresses of 00-1 to 100-4 (A8, A7 to A0)
, The lower 8 bits (A7 to A0) have the same address. For example, as shown in FIGS. 5B and 5C, the lower 8 bits of the leftmost address of the uppermost line are (0000, 0000) in all tiles, and (10000) are in the lowermost left.
111,0000).

As described above, since each tile TI is composed of data on the same row address of the dual-port image semiconductor memory device, the high-speed page mode access can be performed in both the vertical and horizontal directions at the time of drawing. And an access method that continuously accesses data on the same row address, which is similar thereto, can be used, and uniform and high-speed drawing in any direction has been realized.

Further, the dual-port image semiconductor memory device 100 can transfer write data because serial data input from a serial port is transferred to the memory cell array unit 1. However, in this tile map technique, Combining write data transfer and read data transfer, data on a row address corresponding to a certain tile is transferred from the memory cell array unit 1 to the data register of the serial port, and then all data in the tile is written using the write data transfer. A certain display space (on-screen) or a non-display space (off-screen) by transferring to a memory cell on a certain row address
Can be copied and moved.

A stop address is defined by a combination of signal levels of addresses A0 to A7 in a CAS-before-RAS refresh cycle, and a start address is defined by column addresses A0 to A7 in a data transfer cycle.

[0013]

In this conventional dual-port image semiconductor memory device, when drawing one line at a time and displaying one field by the tile map technique, the lower column and the upper column are switched. Data transfer is required every time, and 16 data transfer cycles are required for one line. Therefore, since the number of lines in one field is 768 lines, 16 (times / line) × 76
8 (lines) = 12288 (times) data transfer cycles are required. When this is converted into time, the normal RAS cycle of the dual-port image semiconductor memory device is about 140 ns, so that one data transfer cycle occupies 140 ns. Therefore, the occupation time required for displaying the screen of one field is 12288.
(Times / field) × 140 (ns) = 1.7 (ms /
Field). 72Hz no interlace CRT
Since the time required for one field display is about 13 ms, it is occupied by only the read data transfer cycle for about 13% thereof, and there is a problem that the drawing efficiency is reduced as compared with the scan line map technique. . The time required for this display depends on the increase in the number of display dots on the CRT and the CR
It increases in proportion to the increase in the T refresh rate.

Also, when saving data on a tile for an off-screen portion not displayed on the CRT display screen, or moving data on the tile to the on-screen, the data register of the serial port is used to restore the original row. To transfer the data on the address to the data register by read data transfer and then immediately transfer the data from the data register to the memory cell on the destination row address to be copied by write data transfer, use the serial port data input / output. Since the operation must be stopped and then executed,
The above operation cannot be performed during the display period, so that the drawing cycle is occupied and the drawing performance is reduced.

An object of the present invention is to provide a dual-port image-required semiconductor memory device capable of improving drawing performance and saving or moving data without deteriorating drawing performance.

[0016]

According to the present invention, there is provided a dual-port image semiconductor memory device in which two units of data having a predetermined number of bits as one unit are stored in lower and upper column addresses of the same row. A memory cell array section for reading and writing the two units of data for a selected row including a plurality of rows to be stored correspondingly, and a selected and provided memory cell array section corresponding to a lower column address of the memory cell array section. First and second lower transfer gates and data registers for transferring and receiving data at predetermined timings respectively with the lower column address of a row, and the upper column address of the memory cell array unit The first and second upper-side units which transfer and transfer data at predetermined timings respectively with the upper-side column address of the selected row provided in correspondence with An IO bus circuit and a column decoder for transmitting and receiving data between a transfer gate and a data register and the first and second lower and upper data registers and for inputting and outputting serial data to and from an external circuit The lower and upper transfer gates and data registers of one of the first and second transfer and transfer data to and from the memory cell array unit, and the other lower and upper data A register and the IO bus circuit and a column decoder perform input / output of serial data with an external circuit, and a jump operation of an access point between the lower and upper column addresses according to a start address and a stop address. And the CR of the host system
A plurality of pixels forming the T display screen are divided into a plurality of rows and a plurality of columns of tiles having a predetermined number of dots in the horizontal direction and a predetermined number of lines in the vertical direction, and data corresponding to one of the tiles is stored in the memory cell array unit. It is configured to correspond to one unit of data of one of the lower and upper column addresses of one row.

In addition, data transfer and transfer operations between the lower and upper transfer gates and data registers of the first and second ones and the data register and the memory cell array in accordance with the serial port selection signal and the data transfer request signal. And the serial / parallel data between the lower and upper data registers of the other of the first and second data registers and the external circuit in accordance with the start address and the stop address and in synchronization with the serial clock signal. A tile map control unit for controlling a serial / parallel conversion operation, data transfer, and input / output operations, and controlling a jump operation of an access point between lower and upper column addresses according to the start address and the stop address; It has a serial address control unit.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, the serial port and RAM port shared parts such as the memory cell array section 1, the row address buffer circuit 2, the row address decoder 3 and the column address buffer circuit 4, etc., and the input buffer circuit 11 to the sense amplifier circuit 15 The RAM port portion up to this is the same as the conventional dual-port image semiconductor memory device (hereinafter referred to as a conventional example) shown in FIG. 3, and the serial port portion is different from the conventional example.

The serial port of this embodiment is as follows:
The lower column address (0 to 0) of the memory cell array unit 1
255), a first lower-side transfer gate TGa1 and a lower-side data register DRa1, which transfer and transfer data at predetermined timings to and from this lower-side column address of the selected row, respectively. The second lower transfer gate TGa2 and the lower data register DRa2, and the upper column address of the selected row provided in correspondence with the upper column address (256 to 511) of the memory cell array unit 1. Between the first upper transfer gate TGb1 and the upper data register DRb1 and the second upper transfer gate TGb2 and the upper data register DRb2 for transferring and transferring data at predetermined timings between them.
And first and second lower data registers DRa1, Dra
A serial port / column decoder 25 for transmitting and receiving data between Ra2 and the upper registers DRb1 and DRb2, and inputting and outputting serial data to and from an external circuit via a serial output buffer circuit 27 and a serial input buffer circuit 28. And serial port / IO bus circuit 2
6 and a Stop register 21 which takes in a column address signal from the column address buffer circuit 4 and sets and outputs a stop address Asp and a start address Ast.
And the TAP register 22 and the serial port selection signal S
PS, data transfer request signal DTR, serial clock signal SCK, stop address Asp and start address Ast, the first and second lower transfer gates TGa1 and TGa2 and the upper transfer gate T
Gb1, TGb2, first and second lower data registers DRa1, DRa2, and upper data register DRb
1 and DRb2, and a serial address control unit 23 and a tile map control unit 24 for controlling operations of the serial port / column decoder 25 and the serial port / IO bus circuit 26.

The serial address control unit 23 and the tile map control unit 24 include one of the first and second lower transfer gates (eg, TGa1), the upper transfer gate (TG1), and the lower data register ( DRa1), data transfer with the memory cell array unit 1 is performed by the upper data register (DRb1), and the other lower data register (DRa2),
The input / output of serial data to / from an external circuit is performed by an upper data register (DRb2), a serial port / column decoder 25, and a serial port / IO bus circuit 26. Control is performed so as to perform a jump operation of the access point between the upper column addresses.

The tile map control unit 24 receives the serial port selection signal SPS and outputs data from one of the first and second lower and upper data registers, and outputs the data to the other data register. Decide whether to transfer or not. Also, the start address is set in the TAP register 22.
Unless the start address data is newly rewritten, the value of the TAP register 22 is used as it is in the jump of the access point between the lower side and the upper side of one of the first and second data registers.

For example, the first lower data register DR
When the access point jumps at the stop address of a1 and the access jumps to the position of the start address of the first upper data register DRb1, before the access moves to the position of the lower stop address, the tile map control unit 24 At that time, the address already stored in the TAP register 22 is recognized as the upper-side start address, and even if there is no external data transfer request,
Referring to the stop address data and receiving the access jump request signal TJR at the stop address from the serial address control unit 23 that counts the address by the serial clock signal SCK, the tile map control unit 24 internally stores Make access jump to the side.

With the two sets of transfer gates and data registers, data necessary for data display is previously input to the serial port of the upper or lower column during data input / output, which was impossible in the conventional example. It can be transferred to a data register that is not outputting. As a result, while data input / output from the lower side to the upper side of the first data register is being executed, the screen currently displayed from the first data register is displayed on the lower side and the upper side of the second data register. The data on the tile next to the tile can be transferred. Further, when read data is transferred to the second data register, an external data transfer request signal DTR
And the TAP register 22
, The start address of the lower data register (DRa2) is stored, and the tile map control unit 24 controls so that the stop address of the first data register 1 jumps to the start address.

FIG. 2 is a circuit diagram showing an example of a 1-bit readout circuit system (data output system) of a main part of the serial port portion of this embodiment. Note that a circuit of a writing circuit system (data input system) can be similarly configured.

Which of the first and second transfer gates and data registers can be read (output) by the Q output of the D flip-flop FF, and to which transfer gate and data register data can be transferred. It can be recognized by the serial port active mode signal SPA. When an inverted signal of this signal is input as a serial port selection signal SPS, it receives a data transfer request signal DTR from the outside, and controls the opening and closing of the first or second transfer gate that can be transferred next when transferring read data. be able to.

Further, the serial port active mode signal SPA detects which of the first and second transfer gates and the data register is performing data input / output, thereby detecting a transformer not performing data input / output. Using a gate and a data register, saving of data on a tile to an off-screen portion not displayed on the CRT display screen and movement of data on the tile to the on-screen are performed by a combination of read data transfer and write data transfer. realizable. This can be realized because, even when one data register performs data input / output, the other data register can perform read data transfer / write data transfer independently.

In this embodiment, since data of two adjacent tiles on the same scan line can be transferred in the same cycle in one read data transfer cycle, a 1024 × 768 dot 72 Hz non-interrupt In the case of performing CRT-less display, the number of read data transfer cycles required for one field display is つ ま り of the conventional example, that is, 6288 times. Therefore, the time required for read data transfer is reduced to 0.88 (ms / field). You.

[0030]

As described above, according to the present invention, two sets of transfer gates and data registers are provided in correspondence with the lower and upper column addresses of the memory cell array, respectively, and one of the lower and upper columns is provided. The data transfer to and from the memory cell array section is performed by the transfer gate and the data register on the side, and the lower and upper data registers of the other set communicate with the external circuit by the lower and upper data registers with the external circuit. In this configuration, data of two adjacent tiles on the same scan line can be transferred in the same cycle in a single read data transfer cycle, so that the read data transfer cycle is It is possible to improve the drawing performance by halving the example, and one set of data registers For the time of input and output are also other set capable of performing independent read data transfer / write data transfer,
Evacuation of data on tiles for off-screen parts not displayed on the CRT display screen and data movement on tiles to on-screen stop the operation of the serial port due to a combination of read data transfer cycle and write data transfer cycle. In addition, since such an operation can be performed in the same time as two data transfer cycles (this is four times as long as two random access cycles of a random port), the drawing performance can be further improved. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit example of one bit of a read circuit system of a main part of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional dual-port image semiconductor memory device.

FIG. 4 is a block diagram of a host system using the dual-port image semiconductor memory device shown in FIG. 3;

5 is a pixel arrangement diagram of the CRT display screen for explaining the association between pixel data of the CRT display screen of the host system shown in FIG. 4 and data of the dual-port image semiconductor memory device.

6 is a memory map showing a correspondence relationship between tile data on the CRT display screen of the host system shown in FIG. 4 and a storage area of the dual-port image semiconductor memory device.

[Description of Signs] 1 Memory cell array unit 2 Row address buffer circuit 3 Row address decoder 4 Column address buffer circuit 21 Stop register 22 TAP register 23, 23x Serial address control unit 24 Tile map control unit 25 Serial port / column decoder 26 Serial port -IO bus circuits DRa, DRa1, DRa2 Lower data register DRb, DRb1, DRb2 Upper data register TGa, TGa1, TGa2 Lower transfer gate TGb, TGb1, TGb2 Upper transfer gate TI tile

Claims (1)

(57) [Claims] 1. A selected row including a plurality of rows storing two units of data having a predetermined number of bits as one unit corresponding to the lower and upper column addresses of the same row. At a predetermined timing between a memory cell array unit for reading and writing data in a unit and the lower column address of a selected row provided corresponding to a lower column address of the memory cell array unit. First and second lower transfer gates and data registers for transferring and transferring data, and the upper column address of a selected row provided corresponding to the upper column address of the memory cell array unit. A first and a second upper transfer gate and a data register for transferring and transferring data at predetermined timings between the first and second lower gates, respectively. And an IO bus circuit and a column decoder for transmitting and receiving data to and from an upper-side data register and for inputting and outputting serial data to and from an external circuit,
The lower and upper transfer gates and data registers of one of the first and second transfer and transfer data with the memory cell array unit, and the other lower and upper data registers and the IO A bus circuit and a column decoder input and output serial data to and from an external circuit, and a jump operation of an access point between the lower and upper column addresses is performed according to a start address and a stop address. , A plurality of screens forming the CRT display screen of the host system
A predetermined number of dots in the horizontal direction and a predetermined line in the vertical direction
Dividing the tiles having a number into a plurality of rows and a plurality of columns;
Is stored in one row of the memory cell array section.
One unit of one of the lower and upper column addresses
A dual-port image semiconductor memory device, which corresponds to data .