JPH0453991A - Liquid crystal display controller - Google Patents

Abstract

PURPOSE:To accomplish the display of an LCD device even in the case that dot size is different by performing the readout of a display data memory means according to an output signal from an address conversion means and controlling so that the data of an area which is not posted to a liquid crystal display means may not be written. CONSTITUTION:In order to prevent unnecessary data from being written in a part where the data of a display memory 1 is not written in the liquid crystal display device(LCD) part 10, a mask control part 6 and a mask part 7 are provided. When the data held in a display data memory means 1 is posted to the liquid crystal display means 10, readout is performed to the means 1 according to the output signal from the address conversion means 4, and the mask part 7 is controlled by the mask control means 6 so that the data of the area which is not posted to the means 10 is not written. Thus, the same LCD device 10 is used for the display memory 1 of a main body device whose size is same as or smaller than the device 10.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 4) Means for solving the problems to be solved by the invention (Figure 1) Working examples (Figure 2) , Fig. 3) Effects of the invention [Summary] Regarding the liquid crystal display control device, even if the display dot size of the main body of a personal computer etc. and the display dot size of the liquid crystal display are not the same, as long as the liquid crystal side is larger, the main device The present invention is capable of displaying display data on a liquid crystal, and includes a display data memory means, a memory control means, and a liquid crystal display means, and displays the display data written in the display data memory means on the liquid crystal display means. In the display device, address output means outputs an address corresponding to the liquid crystal display means to the display data memory means, address conversion means converts an address signal outputted from the address output means into an address of the display data memory means, and a mask control means. When data held in the display data memory means is transferred to the liquid crystal display means, the display data memory means is read by the output signal of the address conversion means, and an area not to be transferred to the liquid crystal display means is prevented from being filled in by a mask control means. Configure to control.

[Industrial application field]

The present invention relates to a liquid crystal display control device, and particularly to a liquid crystal display control device that is capable of displaying data from a data processing device main body even on a liquid crystal display whose size is larger than the display memory size of the data processing device main body.

[Conventional technology]

In recent years, liquid crystal displays have been required as display devices in data processing devices such as personal computers and workstations in order to save space and energy.

In a conventional liquid crystal display control circuit for a data processing device, as shown in FIG. 4(A), a liquid crystal display device W (
The number of dots that can be displayed on the LCD device (hereinafter referred to as an LCD device) and the number of dots that can be displayed on the main body of the data processing device were the same (for example, 1024×768 dots). The memory was configured according to the number of display dots, and the memory data was transferred to the LCD device on a one-to-one basis.

Note that in an LCD device, the screen is divided into two parts, upper and lower, to form one screen. Therefore, when writing data to the display memory 60 of the main unit, data is written sequentially from the first address of the display memory 60 as shown in FIG. 4(A), but after writing for -frames, This is the LCD section 70
When writing, the LCD section 70 actually writes to the upper LCD section and the lower LCD section at the same time, so in the display memory 10 of the main unit, the upper part is read from the RA position, and the lower part is read from the R8 position. Ru. And above these,
The data read from the lower part is displayed on the upper LC of the LCD section 70.
It is written in the D section and the lower LCD section at the same time.

The configuration will be schematically explained in FIG. 4(B).

The display memory 60 includes a first half memory 60-1 and a second half memory 60.
It consists of two pieces: -2.

When writing data into the display memory 60, the memory control section 61 outputs a write enable signal to the first half memory 60-1, and the address control section 62 outputs an address. After the data is written in the first half memory 60-1, the memory control unit 61 outputs a write enable signal to the second half memory 60-2, and the address control unit 62
The same address as the first half memory 60-1 is output. In this way, data is sequentially written into the first half memory 60-1 and the second half memory 602.

When reading data from the display memory 60 and writing it on the LCD section 70 of the liquid crystal display device 64,
The memory control unit 61 does not output the write enable signal WE, but outputs the output enable OE, and the address is transmitted from the address control unit 62 to the memory 60.

As a result, data is simultaneously sent to the LCD section 70 from the first half memory 60-1 and the second half memory 60-2.

The LCD section 70 each has a data shift register in order to receive data sent from the first half memory 60-1 and the second half memory 60-2.

These data shift registers transfer 8 bits at a time. That is, 8 bits are each transferred to each data shift register of the LCD section 70 according to the address from the address control section 62. At this time, the liquid crystal display control section 63 sends the data shift register clock X5CL, the data line latch clock YSCL, and the scan start signal N to the LCD section 70 in synchronization with the read @ control of the address control section 62. Output. The input data is sequentially shifted into shift registers in one horizontal scanning direction of the display, that is, in the X direction, by the χSCL. When one line of data is input, the YSCL is output,
The data for one line is latched, and X S C
By L, data for the next line is input and shifted. In this way, data for one frame is input. Note that at the beginning of inputting data for one frame,
=s will be input.

The data read out from the display memory 60 in this manner is sequentially held and displayed on the LCD section 70.

[Problem to be solved by the invention]

In conventional liquid crystal display control, the number of displayable dots on the liquid crystal display device and the number of displayable dots in the display memory of the main unit match, that is, the memory size matches, and the number of displayable dots on the LCD is The memory data was transferred from the display memory of the main unit to the LCD section of the liquid crystal display device on a one-to-one basis.

However, the number of display screen dots (display double-sided size) varies depending on the type of main body device such as a personal computer, and conventionally, the LCD section has been selected according to the number of display dots on the surface of the main body device.

In this way, the display size of the liquid crystal display device is selected according to the main device, so if the number of display dots on the main device differs, the number of types of liquid crystal display devices increases accordingly, which raises the problem of higher costs. was.

Therefore, an object of the present invention is to provide a liquid crystal display control method that allows the same liquid crystal display device to be used for the display memory of a main unit of the same or smaller size. The goal is to provide the following.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as shown in FIG.
larger or the same size, and the display data in the display memory l is set to 1.
It is constructed so that <0 can be displayed in the LCDCD section as shown in .

Therefore, as shown in FIG. 1(B), when writing data D into the display memory l of the main unit, the address of the display memory is output from the memory control unit 2, and the multiplexer 5
This address is transmitted to display memory 1 via , and data D is written therein. At this time, the write enable signal WE from memory size 2 is first output to the upper half memory 1-1 to be written, as in the conventional case, and then to the lower half memory l.
-2 is output. Thus, during writing, the same address is output from the memory control section 2 to the display memory 1 twice.

By the way, in order to display on a liquid crystal display device, it is necessary to transfer the data in the display memory l to the LCD section 10, but in this case, since the size of the LCD section 10 is larger than the size of the display memory l, It is necessary to display data zero in the area other than the hatched area 1' in FIG. 1(B). For this purpose, a mask section 7 is prepared.

When display data is transferred from the display memory l to the LCD section 10, an address corresponding to the size of the large LCD section IO is output from the address control section 3. Now, the LCD section 10 of FIG. 1(A) is addressed in a virtual manner, and addresses are sequentially output from A. When the point A of the LCD section 10 is addressed, the address is converted so that the address conversion section 4 outputs the first address of the display memory 1. That is, when counting the line position fYz, the first address Y'o of the display memory 1 is specified, and when the column signal is Xl, the column signal of the display memory 1 is the first address X'o.
is converted to show. After the column signal counts x3 of the LCD section 10, the X-direction address is cleared and the Y-direction address is counted up. Thereby, the data in the display memory 1 can be transferred to a predetermined position on the LCD section 10.

In this case, the LCD section 10 is provided with a mask control section 6 and a mask section 7 in order to prevent unnecessary data from being written in the portion of the display memory l where no data is written. Portion 10-1 of LCD section 10
and 1O-2 are addressed, the mask 7-1 .
Mask off 7-2 and fill in zero. In addition, Figure 1 (
In B), a dotted line portion 10' outside the display memory 1 is a pseudo representation of the size of the LCD section 10.

[Effect]

In this way, even if an LCD section having a different size from the display memory is used, data in the display memory can be displayed at a predetermined position on the LCD section.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 and 3.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a state in which data in a display memory is displayed on an LCD section.

In Figure 2, the same symbols as in Figure 1 indicate the same parts,
1 is a display memory, 2 is a memory control section, 3 is an address control section, 4 is an address conversion section, 5 is a multiplexer, 6 is a mask control section, 7 is a mask section, 8 is a liquid crystal display control section, 10 is an LCD section, 11 is a CRT control section, 12 is a synchronization circuit, 13 is a video shift register, 14 is a data latch, 15 is a mode setting section, 16 is an upper data latch, 1
7 is a lower data latch.

The display memory 1 is composed of a first half memory 1-1 and a second half memory 1-2, and the first half memory 1-1 and the second half memory 1-2 are accessed using the same address.

When writing data, the write enable signal WE is selectively output to one of them, so that data is selectively written into the first half memory 1-1 and the second half memory 1-2, and when reading data, by giving the same address. Data is simultaneously output from the first half memory 1-1 and the second half memory 1-2.

The memory control section 2 includes a read/write control section 2-1 and an address output section 2-2. Read/write control section 2-
1 selectively outputs a write enable signal WE to either the first half memory 1-1 or the second half memory 12 when writing data to the display memory 1. Further, the address output section 2-2 includes a column direction address counter 2-3 and a line direction address counter 2-4, and each address signal output from these is transmitted to the display memory 1 via the multiplexer 5.

The address control unit 3 outputs an address signal when reading data from the display memory l and transcribing it to the LCD unit 10, and includes an X-direction counter 3-1 for outputting a column-direction address and a line-direction counter It is equipped with an X-direction counter 3-2 for outputting an address. The address output from the address control section 3 is used to pseudo-address the LCD section 10. That is, as shown in FIG. 3, 0 to Xn are output as column direction addresses, and O-Ym are output as line direction addresses.

The address conversion section 4 converts the address signal output from the address control section 3 and controls the data in the display memory 1 in FIG. 3 to be displayed in the shaded area 1' of the LCD section IO. It includes an X-direction conversion section 4-1 and an X-direction conversion section 4-2. The X direction converter 4-1 counts up from 0 when the X direction counter 3-1 counts XI, and the X direction converter 4-2 counts up from 0 when the X direction counter 3-1 counts XI.
-2 counts up from 0 when Yl is counted. These output addresses of the address converter 4 are transmitted to the first half memories 1 to 1 and the second half memory 1-2 of the display memory 1 via the multiplexer 5, so that the When the X-direction counter 3-2 points to point A1 on the LCD section 10, data is read from the display memory 1 and is displayed in the shaded area 1' as will be described later.

The multiplexer 5 selectively outputs the address signal transmitted from the address output section 2-2 or the address conversion section 4, and when in the write mode in which data is written to the display memory 1, the address signal transmitted from the address output section 2-2 is output. output what is displayed, read the data from display memory 1, and read the data from display memory 1.
In the read mode for transcribing to the D section 10, what is transmitted from the address conversion section 4 is output.

The mask control section 6 controls the mask section 7 in order not to display noise in a portion other than the hatched area 1' of the LCD section 10 shown in FIG. Therefore, LC in Figure 3
Registers 6-1.6-2.6-3.6-4 holding line direction addresses Y1, Y2 and column direction addresses X1, X2 shown in D section 1O, respectively, and upper mask control section 6
-5, a lower mask control section 6-6 is provided. The upper mask control unit 65 controls the mask off signal until the output of the X direction counter 3-2 reaches Y1, and when the output of the X direction counter 3-1 reaches X2 or higher, the mask off signal becomes upper mask. Output to 7-1. The lower mask control unit 6-6 controls the output of the X-direction counter 3-2 until the output of the X-direction counter 3-2 reaches number 72, until the output of the X-direction counter 3-1 reaches X1, and after X2, and When the output is equal to or higher than Y2, a mask off signal is output to the lower mask 7-2.

The mask section 7 covers the hatched area 1 of the LCD section IO shown in FIG.
' is masked so as not to write the data of display memory I in the part other than ', and outputs 0. Upper mask 7-1
and a lower mask 7-2. The upper mask 7-1 is turned off when a mask off signal is applied from the upper mask control section 6-5 of the mask control section 6, and the lower mask 7-2 is turned off when a mask off signal is applied from the lower mask control section 6-6. It turns off when the

When transferring data from the display memory 1 to the LCD section 10, the liquid crystal display control section 8 uses a data shift register clock X5CL and a data line latch clock YS.
CL and a scanning start signal Di are output to the LCD section 10.

First, 8 is set by the data shift register clock X5CL.
Data is shifted bit by bit, and when the input data for one horizontal scanning direction is set in the data shift register, the data line latch clock YSCL is output, this is latched, and the data for the next one horizontal scanning direction is input again by X5CL. be done. This process is repeated in sequence, and when data for one frame is input, DiN is input at the beginning of the next frame.

The CRT @ control unit 11 performs processing control for displaying data on the CRT screen, and receives the horizontal synchronization signal H3YNC.
1 vertical synchronization signal VSYNC, clock CLK, video data VDO, etc.

This clock CLK is also used as an address counter when writing and reading video data VDO to the display memory 1.

The synchronization circuit 12 sends a control signal to the address output section 2-2, a shift clock to the VD shift register 13, and a control signal to the data latch 14 based on the horizontal synchronization signal H3YNC3 vertical synchronization signal. Send out.

The VD shift register 13 sequentially receives video data output from the CRT control section 11.

The data latch I4 temporarily holds the video data transmitted from the VD shift register 13 and sequentially sends it to the display memory 1.

The mode setting unit 15 outputs a control signal depending on whether the mode is a write mode in which data is written in the display memory 1 or a read mode in which data is read from the display memory 1 and transferred to the LCD unit 10. For example, in the write mode, the multiplexer 5 controls the address signal outputted by the address output section 2-2, or the read/write control section 2-1 outputs the write enable signal WE first. It is output to the first half memory 11 of display memory 1, and when data is written there, it is output to the second half memory 1-2.
Then, the write enable signal WE is output.

In the case of read mode, the multiplexer 5 is controlled to output the address signal from the address conversion section 4, the address control section 3 is operated, the mask control section 6 is operated, and the liquid crystal display control section Controls such as operating 8 are performed. It also controls whether the output of the display memory 1 is latched into the upper data latch 16 or the lower data latch 17.

The upper day clutch 16 is the first half memory 1-1 of the display memory 1.
This is to sequentially latch the data output from the memory.

The lower data latch 17 is the second half memory 1-2 of the display memory l.
This is to sequentially latch the data output from the memory.

Next, the operation shown in FIG. 2 will be explained.

(1) When writing data to display memory, CRT@
The column direction address counter 2-3 of the address output section 2-2 is cleared in synchronization with the horizontal synchronization signal H3YNC output from the control section 11, and the line address counter 2-4 is initialized ( The starting position of the first half memory 1 (for example, zero). When the number of display dots in the horizontal direction of the display memory I has been counted, for example, 960 dots, no further counting is performed. When the horizontal synchronizing signal H3YNC is input, the line address counter 2-4 is counted up and the column direction address counter 2-3 is cleared. At this time, the read/write control unit 2-1 controls the first half memory 1-1 of the display memory 1.
The write input signal WE is output to the multiplexer 5.
is controlled to output the address signal from the address output section 2-2, so the VD shift register 1
3 and data latch 14 are sequentially written into the first half memory 1-1.

And line address counter 2-4 is the first half memory 1
-1 After counting the number of lines in (second half memory 1-2), returns to the initial setting value. In this way, the first half memory 1
After the video data is written in the memory 1-1, the read/write control section 2-1 outputs a write enable signal WE to the second half memory 1-2. Since the address output section 2-2 is controlled in the same manner and outputs the same address as the first half memory l-1, video data is now written into the second half memories 1 and 2.

In this way, the video data write operation is repeated.

(2) When reading data from the display memory and writing data to the LCD section, when the read mode signal R is input to the mode setting section 15 from the control section (not shown), the video written in the display memory 1 is The data is read out and transferred to the LCD section 10, and is displayed on the LCD device.

The multiplexer 5 in turn outputs the address signal transmitted from the address conversion section 4 to the display memory 1, and the address control section 3 is operated.

In the address control section 3, the X-direction counter 3-1 and the Y-direction counter 3-2 are cleared, and then the X-direction counter 3-1 counts up based on the clock CLK. When the X-direction counter 31 counts the number of dots in the horizontal direction of the LCD section IO (for example, 1024), the Y-direction counter 3-2 counts up by 1, and the X-direction counter 3-1 returns to the initial value of zero again. A counting operation is performed in the same way. (The upper memory 1-1 and the lower memory 12 are read at the same time.) By the way, as shown in the right drawing of FIG.
In order to display the video data written in the display memory 1 in the diagonally shaded area 1', the display memory 1 is not read in the area where the X direction counter 3-1 is from 0 to Xi. In the area x1 to Xn, the display memory 1 is read, but the data is controlled to be turned off by the mask section 7. In addition, the counter 3-2 in the Y direction
In the area of 0 to Y1 and Y2 to 2Ym, the mask section 7 controls the data to be turned off.

Therefore, when the X-direction counter 3-1 and the Y-direction counter 3-2 indicate AX(Xi, Y1), the address conversion section 4 performs address conversion so that the display memory 1 can be read. Therefore, the X direction counter 3-1 and the Y
Check the count value of the direction counter 3-2, and
When the value becomes 1, the counter of the X-direction converter 4-1 is operated, and when the value becomes Yl, the counter of the X-direction converter 4-2 is operated. When converted addresses are output from these, the address converter 4 sends these address signals to the multiplexer 5. As a result, data is simultaneously read from the first half memory 1-1 and the second half memory 1-2 of the display memory 1, and is temporarily held in the upper data latch 16 and the lower data latch 17, respectively.

By the way, as mentioned above, the mask control section 6 controls not to write data in the area of the LCD section 10 other than the shaded area 1' in FIG. 3, and therefore the upper mask control section 6-5 and the lower mask It has a control section 6-6 and controls the upper mask '11 and the lower mask 7-2 based on the data written in the registers 6-1 to 6-4 to address the diagonal area 1'. These upper masks 7-
1 and the lower mask 7-2 are turned on to transcribe the data.

When transferring data to the LCD section 10, data is transferred 8 bits at a time, so 8 bits of data are read from the display memory 1,
As described above, data is set in one horizontal direction by the data shift register clock X5CL and latched by the data line latch clock YSCL. and 1
When the transfer control to the LCD unit 10 for one frame is completed,
A scanning start signal D i N is output, and control for the next frame is performed.

In the above description, the display memory 1 and the LCD section 10 are each divided into two parts. However, the present invention is not limited to this, and even in the case of one part, the display memory 1 and the LCD part 10 can be divided into three or more parts. display memory and LC even if
Control can be performed in the same way by keeping the number of screens in section D the same. Furthermore, instead of using a separate mask, a masking function may be added to the upper data latch and the lower data latch so that a fixed value of zero may be output to areas other than the shaded area 1'.

〔Effect of the invention〕

As described above, according to the present invention, even if the dot size of the display memory on the main body side and the dot size of the LCD device are different, it is possible to display on the LCD device, so that the same LCD device can be used for multiple types of main devices. becomes possible.

10-L CD section

Claims (2)

[Claims] (1) Comprising a display data memory means (1), a memory control means (2), and a liquid crystal display means (10), the display data written in the display data memory means (1) is displayed on the liquid crystal display means (10). In a display device for displaying images, an address output means (3) for outputting an address corresponding to the liquid crystal display means (10), and an address output means (
3) Displays the address signal output by the data memory means (
1), and a mask control means (6), when transferring the data held in the display data memory means (1) to the liquid crystal display means (10), A liquid crystal display control device characterized in that the display data memory means (1) is read out by the output signal of (4), and the mask control means (6) controls so that no data is written in the area that is not to be transcribed on the liquid crystal display means (10). . (2) The liquid crystal display control device according to claim 1, wherein the display data memory means (1) and the liquid crystal display means (10) are composed of at least two equal numbers.