JPH0731634B2 - Memory arbitration control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A memory arbitration control device in which a memory access order from a plurality of devices is arbitrated, and then access arbitration of a designated area is performed based on the arbitration result and the number of access area designation words. Correspondingly, a memory adjustment control method is possible in which an access request signal and the number of words to specify an area to be accessed are input to an arbitration section controlled by a program, and which is easily performed with a simple circuit configuration.

[Industrial application field]

The present invention relates to a memory arbitration control device that easily arbitrates simultaneous write / read access to a memory with a simple circuit configuration.

For example, as a terminal device used in an information processing system mainly including a main control device (hereinafter referred to as CPU), there is a device that displays predetermined information or transfers the predetermined information to a higher-level device. The information to be displayed or transferred at is stored and stored in a memory having a predetermined capacity, and the memory is accessed.

On the other hand, the memory may be accessed simultaneously from, for example, a CPU or a cathode ray tube controller (hereinafter referred to as CRTC), and thus a circuit for arbitrating the access order is required. It has been desired to construct such an arbitration circuit at a low cost with a simple circuit configuration.

[Problems to be solved by conventional technology and invention]

As a conventional technique, a terminal device having a CRT will be described as an example.

FIG. 3 is a block diagram illustrating a conventional example, and FIG. 4 is a diagram illustrating a memory configuration.

As shown in FIG. 4, the memory 13 of this example comprises 16 × 24 bit memory banks a to n. Each of the memory banks a to n is composed of a bank-high 13a to 13n and a bank-row 13a 'to 13n' which are composed of 1 byte.

In the case of this example, it is assumed that the memory 13 is composed of the memory banks a and b. Further, the memory 13 stores in advance data necessary for displaying on a CRT or the like, for example, pattern data of kanji, alphabets, numbers, etc.
It should be output by accessing from 3rd grade.

It is assumed that an access request signal for accessing the memory 13 from the CPU 2 and the CRTC 3 is simultaneously sent to the arbitration circuit 11.
At this time, the word number (bit number) data that specifies the access area of the memory 13 from the CPU 2 and the CRTC 3 is the word number determination circuit.
Send to 12.

Normally, the access area of the memory 13 is performed in byte units, that is, in units of bank-high 13a, bank-row 13a ', etc., and the output data is multiplexed (hereinafter referred to as MPX) 1
Select the word number (bit number) data in 4 or 15 and select a predetermined data pattern (data is output in bit units)
Is displayed on CRT16 or transferred to CPU2.

For example, since a Chinese character data pattern is displayed with 24 × 24 dots, all the data (all bit data) are selected by MPX 14 or 15 by accessing the bank-high 13a, 13a ′, 13b.

In addition, since the data pattern of English letters is displayed with 12 x 24 dots, access the bank-high 13a, 13a ', MPX14 or
At 15, the four bits of bank-high 13a and bank-row 13a 'are selected and sent to the CRT 16 or transferred to the CPU 2.

When the access request signals are simultaneously input to the arbitration circuit 11, which is to be preferentially processed is set in advance inside the arbitration circuit 11 and processed according to the setting condition, and the number of words to be preferentially processed also from the word number determination circuit 12 The (number of bits) data is sent to the memory 13, MPX 14, 15 and the like.

In the conventional arbitration control system as described above, since the arbitration circuit 11 and the word number determination circuit 12 are separately provided and processed, these circuits require an input / output section, and the circuit configuration increases accordingly. However, there is a problem that it becomes expensive and complicated.

[Means for solving problems]

FIG. 1 shows a principle block diagram of a memory arbitration control device of the present invention.

That is, a memory (13) which is composed of a plurality of banks and holds data to be written / read by a plurality of devices, and a register (18) which stores state information indicating the current access state to the memory (13). When the access request signal for simultaneously accessing the memory (13) from a plurality of devices and the word number data indicating the access target area in the memory (13) are received, the data is stored in the register (18). In addition to the present state information indicating the present access state, the access arbitration to the memory (13) and the designation of the access area are performed, and the access signal according to the access arbitration and the access area designation is sent to the memory (13). An arbitration control unit (17) that outputs to the register (18) state information indicating the access state to the memory (13), and the arbitration control unit ( The data corresponding to the content of the status information output from the arbitration control unit (17) is selected from the data read by accessing the memory (13) in bank units by the access signal from the (17). It is composed of multiplexers (14, 15) for outputting the output.

[Action]

For example, to display data on CRT16, the memory from CRTC3
When an access request for reading the data pattern stored in 13 and an access request for writing data to the memory 13 from the CPU 2 are simultaneously made, the arbitration control unit 17
Refers to the current state information from register 18 and CRTC3
Alternatively, the stored program is activated by the word number data input from the CPU 2 to quickly perform arbitration for both accesses.

As a result, since the connection part between the word number determination circuit and the arbitration circuit and the input part of the word number determination circuit, which were required in the past, can be shared with the arbitration control unit, it is possible to easily arbitrate access to the memory with a simple circuit configuration. Becomes

〔Example〕

The gist of the present invention will be specifically described below with reference to an embodiment shown in FIG.

FIG. 2 is a block diagram for explaining an embodiment of the memory arbitration control system according to the present invention. The same reference numerals denote the same objects throughout the drawings.

Next, the operation of this embodiment will be described. The memory 13 of this embodiment includes bank-high 13a, 13b and bank-row 13a ', 13b'.
It shall be divided into four.

When the access request signal for the memory 13 from the CPU 2 and the CRTC 3 and the word number data indicating the access target area of the memory 13 are transmitted to the arbitration unit 171, the arbitration unit 171 stores the current state information ′ (( ST0 to ST4), the stored program is activated and arbitration is performed according to the arbitration order pre-installed in the program.
That is, in the memory (ROM) in the arbitration unit 171, the arbitration result is calculated and stored in advance for the combination of the input signals (access request signal, word number data, current state information) of the arbitration unit. When the above access request signal is applied,
State information and bank select signals are generated according to the information stored in this memory (ROM).

Here, the information stored in the memory (ROM) is the type of device (CRT16, C
Character generator (GC) access request has priority over PU access request) and configuration method (DRAM in memory 13)
, The priority is automatically determined by the CG access request and the refresh access request is prioritized.

The current state information '(ST0-4) is returned to the arbitration unit 171 for the following reason. Normally, reading / writing of data to / from the memory can be made only one access within one cycle, but one cycle normally requires time for several operation clocks of the arbitration unit 171 and is used to detect the end of the memory cycle. The arbitration unit 17 provides information on the current memory operation state.
One needs to be aware.

Therefore, by returning this current state information, the timing of access to the memory can be grasped and
For example, return the state of two banks, 13a and 13b,
Information on the vacant banks is notified so that the vacant banks can be accessed immediately. The status information represented by NST0 to NST4 is sent to the register 18 and the MPXs 14 and 15.
The status information indicates the type of access request source that is the result of the arbitration (Kanji access, which is a display access to the CRT16, alphabetic / numeric access, data write / read access from the CPU2, etc.), and as described later. , MPX1
It is also information indicating up to which bit of which bank is extracted for 4,15. Further, the arbitration unit 171 turns on the select signals corresponding to the banks (bank-high 13a, 13b, bank-row 13a ', 13b') to be accessed among the four bank select signals, and stores them in the register 172. The bank (bank-high 13a, 13b, bank-row 13a ', 13b') corresponding to the stored data is accessed.

For example, if you are currently accessing the CRT16 in alphanumeric display access, bank-high 13a and bank-
Row 13a ′ is accessed and the accessed result is MPX14
Sent to. For the data sent to the MPX14, bit-wise "on" and "off" signals are sent.

In the MPX14, of the data of 2 bytes (16 bits), if the display access to the CRT16 is an alphabetic character, only 12 bits are selected by the status information and sent to the CRT16 to be displayed as a visible image.

As described above, the memory arbitration control method that arbitrates the access order of the memory 13 and easily executes the access process based on the state information can be realized with a simple circuit configuration.

〔The invention's effect〕

According to the present invention as described above, there is an effect that access arbitration control for a memory can be easily performed with a simple circuit configuration.

[Brief description of drawings]

1 is a block diagram illustrating the principle of a memory arbitration control device according to the present invention, FIG. 2 is a block diagram illustrating an embodiment of a memory arbitration control device according to the present invention, and FIG. 3 is a block diagram illustrating a conventional example. FIG. 4 is a diagram for explaining the memory configuration, respectively. In FIGS. 2, 3, and 4, 1 is a terminal device and 2 is a terminal device.
CPU, 3 CRTC, 11 arbitration circuit, 12 word number determination circuit, 13
Is a memory, 13a to 13n is a bank high, 13a 'to 13n' is a bank low, 14 and 15 are MPXs, 16 is a CRT, 17 is an arbitration control unit, 1
Reference numeral 71 is an arbitration unit, and 172 and 18 are registers.

Claims (1)

[Claims] 1. A memory (13) comprising a plurality of banks for holding data to be written / read by a plurality of devices, and a register for storing status information indicating a current access status to the memory (13). (18), the access request signal for simultaneously accessing the memory (13) from a plurality of devices, and the word number data indicating the access target area in the memory (13), the register (18) Taking into account the current state information indicating the current access state stored in the memory (13), the access arbitration to the memory (13) and the designation of the access area are performed, and the access signal according to the access arbitration and the access area designation is sent to the memory ( An arbitration control section (17) for outputting to the register (18) state information indicating an access state to the memory (13) while outputting the arbitration to the memory (13); Data corresponding to the contents of the state information output from the arbitration control unit (17) from the data read out by accessing the memory (13) in bank units by an access signal from the control unit (17) And a multiplexer (14, 15) for selecting and outputting the memory arbitration control device.