JPS61259356A - Memory intervention control system - Google Patents

Abstract

PURPOSE:To facilitate intervention control with simple circuit constitution by applying memory intervention control based on an access request signal from plural devices, an access area designation word number and present status information stored in a register in an intervention control section. CONSTITUTION:When access request signals 1, 3 to a memory 13 and number of word data 2, 4 representing the access object area of the memory 13 are sent to the intervention section 171. The intervention section 171 references the present status information 5' stored in a register 18 to start the stored program. Then the intervention is applied according to the order of intervention combined in the program in advance. For example, when the present access is a display access to a CRT6 by an alphabetic character, a bank high 13a and a bank low 13a' are accessed and the result is sent to a multiplexer MPX14. The MPX14 selects only 12-bit by the state information 5 according to the display access to the CRT16 by alphabetic characters in the data by 2-byte and display the result to the CRT16 as a visual image.

Description

[Detailed Description of the Invention] [Summary] A memory arbitration control method that arbitrates the order of accesses from multiple devices to the memory, and then arbitrates access to a designated area based on the arbitration result and the number of designated access area words. Correspondingly, the access request signal and the designated number of words for the access target area are input to the controlled arbitration section by a program, thereby making it possible to easily implement a memory arbitration control method with a simple circuit configuration.

[Industrial application field]

The present invention relates to a memory arbitration control method that easily arbitrates simultaneous write and read access to a memory with a simple circuit configuration.

For example, as a terminal device used in an information processing system based on a main control unit (hereinafter referred to as CPU), there is a terminal device that displays predetermined information or transfers the predetermined information to a host device. Information to be displayed or transferred is stored in a memory having a predetermined capacity, and is performed by accessing the memory.

On the other hand, access to the memory is performed by, for example, CPII
Since access may be made simultaneously from a computer, a cathode ray tube control device (hereinafter referred to as CRTC), etc., a circuit is required to arbitrate the access order. It is desired to construct such an arbitration circuit with a simple circuit configuration at low cost.

[Prior Art and Problems to be Solved by the Invention] As a prior art, a terminal device having a CRT will be explained as an example.

FIG. 3 is a block diagram illustrating a conventional example, and FIG. 4 is a diagram illustrating a memory configuration.

The memory 13 in this example has a size of 16 x 24 as shown in FIG.
It consists of memory banks a-n of bits. Furthermore, each memory puncture a'-n consists of puncture high 13a to 13n and puncture low 13a' to 130' each consisting of one byte.
It is made up of.

In this example, the description will be made assuming that the memory 13 is composed of memory banks a and b. In addition, Memo+J13 is pre-stored with data necessary to display on a CRT, etc., such as pattern data of kanji, alphabets, numbers, etc.
It is assumed that the data is output by access from the PU2, CRTC3, etc.

Assume that access request signals (2) and (2) for accessing the memory 13 from the CPU 2 and CRTC 3 are simultaneously sent to the arbitration circuit 11. At this time, the word number (bit number) data ``2'' and ``2'' specifying the access area of the memory 13 are sent from the CP[12 and the CRTC 3 to the word number determination circuit 12.

Normally, the access area of the memory 13 is accessed in byte units, that is, in units of puncture-high 13a1 bank-row 13a', etc., and the output data is sent to a multiplexer (hereinafter referred to as MPχ
(referred to as) 14 or 15 and the number of words (number of bits) data■,
By selecting (2), a predetermined data pattern (data is output in bits) is displayed on the CRT 16 or transferred to the CPU 2.

For example, the Kanji data pattern is displayed as 24 x 24 dots, so Punk-High 13a, 13a'
, 13b and select all data (all bit data) with liver X14 or 15.

Also, since the alphabetical data pattern is displayed as 12 x 24 dots, access Punk-High 13a and 13a', and select 4 bits of Punk-High 13a and Punk-Low 13a' in MPX14 or 15. CRT1
6 or transfer it to CPt12.

When the access request signals ■ and ■ are input to the arbitration circuit 11 at the same time, which one is to be processed with priority is set in advance within the arbitration circuit 11, and the signal is processed according to the setting conditions, and the signal is also given priority processing from the word count determination circuit 12. Number of words (number of bits)
Data ■ and ■ are sent to the memory 131MPX14.15, etc.

In the conventional arbitration control method as described above, the arbitration circuit 11 and the word count determination circuit 12 are separately provided and processed, so there is a problem that the circuit configuration is increased (and the circuit becomes expensive and complicated). There is a point.

Means for Solving Problem c] FIG. 1 shows a block diagram of the principle of the memory arbitration control system of the present invention.

FIG. 1 shows the memory 13 explained in FIG. 3, and a built-in program that uses the access request signal, the word count data specifying the access area, and the current state information of the access arbitration process to arbitrate the access to the memory 13 and adjust the access area. The arbitration control unit 17 performs the specification, and the current access state to the memory 13 (for example, CRTC
3, access from CPt12, etc.);

[Effect]

For example, for data display on CR, T16, CRT
An access request from C3 to read the data pattern stored in the memory 13 and an access request from the CPU 2 to the memory 13
When an access request for data writing is simultaneously made to , the arbitration control unit 17 refers to the current status information from the register 18 and uses the word count data input from the CRTC 3 or the CPU 2 to determine the stored program content. and quickly arbitrate for both accesses.

This makes it possible to easily arbitrate access to the memory with a simple circuit configuration.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating an embodiment of the memo IJ IN stop control method according to the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Next, the operation of this embodiment will be explained. It should be noted that the memory 13 of this embodiment includes punk-high 13a, 13b and punk-low 1.
Assume that it is divided into four parts, 3a' and 13b'.

When the CPU 2 and CRTC 3 send the access request signals ■, ■ to the memory 13 and the word count data ■, ■ indicating the access target area of the memory 13 to the arbitration unit 171, the arbitration unit 171 receives the current information stored in the register 18. Referring to the status information ■' (STO to 5T4), the stored program is activated and arbitration is performed according to the arbitration order pre-installed in the program.

The arbitration unit 171 sends status information (2) representing the arbitration result as N5TO-NST4 to the register 18 and the MPX 14.15.

The status information (2) refers to kanji access, which is display access to the CRT 16, alphanumeric access, and data write/read access from the CPU 2.

Further, the arbitration unit 171 turns on the select signal ■ corresponding to the puncture to be accessed (punk-high 13a, 13b, puncture-low 13a', 13b') among the four-tree puncture select signal ■ and stores it in the register 172. death,
Punk corresponding to stored data (Punk-High 13
a, 13b + punk-low 13a', 13b
' ) to access.

For example, the one you are currently accessing is a CRT1 with alphabetic characters.
6, the Punk-High 13a and Punk-Low 138' are accessed, and the accessed results are sent to the MPX 14. The data sent to the MPX 14 is sent in bit-by-bit "on" and "off" signals.

In MPX14, out of 2 bytes (16 bits) of data, 1 is required for display access to CRT16 using alphabetic characters.
Only 2 bits are selected according to the status information (2) and sent to the CRTI 6 to be displayed as a visible image.

As described above, it is possible to realize a memory arbitration control method that arbitrates the access order of the memory 13 with a simple circuit configuration and easily executes access processing based on the status information (2).

〔Effect of the invention〕

According to the present invention as described above, there is an effect that access arbitration control for memory can be easily performed with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the memory arbitration control method of the present invention, FIG. 2 is a block diagram explaining an embodiment of the memory arbitration control method according to the present invention, and FIG. 3 is a block diagram explaining a conventional example. FIG. 4 is a diagram explaining the memory configuration. 2, 3, and 4, 1 is a terminal device, 2 is a CPU, 3 is a CRTC, 11 is an arbitration circuit, 12 is a word count determination circuit, 13 is a memory, 13a to 13
n is punk-high, 13a' to 130' are punk-low, 14.15 is MPX, 16 is CRT
. 17 is an arbitration control unit, 171 is an arbitration unit, 172, 1
8 indicates a register, respectively. The origin of the present invention 1 ri bsu 2 z 茅 1 fig. memorio book 5 Lilty 珂 15 fig. 4 &Q

Claims (1)

[Scope of Claims] A method of arbitrating the access order of the memory (13) under predetermined conditions when accessing the memory (13) consisting of a plurality of banks from a plurality of devices at the same time, comprising: an arbitration control unit (17) storing a program for inputting an access request signal for accessing the memory (13) and the number of words specifying an access area and controlling arbitration for accessing a predetermined area of the memory (13); Memory (13
), and the arbitration control unit (17) stores the access request signals from the plurality of devices, the number of access area designation words, and the register ( 18) A memory arbitration control method characterized in that arbitration control of the memory (13) is performed based on current state information ((5)) stored in the memory.