JPS57143655A - Main storage controlling system - Google Patents

Main storage controlling system

Info

Publication number
JPS57143655A
JPS57143655A JP2847481A JP2847481A JPS57143655A JP S57143655 A JPS57143655 A JP S57143655A JP 2847481 A JP2847481 A JP 2847481A JP 2847481 A JP2847481 A JP 2847481A JP S57143655 A JPS57143655 A JP S57143655A
Authority
JP
Japan
Prior art keywords
banks
access
controlling system
main storage
busy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2847481A
Other languages
Japanese (ja)
Other versions
JPS6113265B2 (en
Inventor
Takashi Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2847481A priority Critical patent/JPS57143655A/en
Publication of JPS57143655A publication Critical patent/JPS57143655A/en
Publication of JPS6113265B2 publication Critical patent/JPS6113265B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To improve the performance for access, by issuing an access request to a bank, which is not busy, and giving priority to an access request to other banks in the storage controlling system where banks are accessed by the output of the highest priority level. CONSTITUTION:If access requests to plural banks 13a-13d in a main storage device 12 are issued from an arithmetic device, the access requests are issued to the bank, which is not busy, when at least, one bank, among banks 13a-13d is not busy, and simultaneously, access requests to other banks are exectuted preferentially while suppressing other access requests. By this cntrol, the perfomance for access to plural banks is improved considerably.
JP2847481A 1981-03-02 1981-03-02 Main storage controlling system Granted JPS57143655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2847481A JPS57143655A (en) 1981-03-02 1981-03-02 Main storage controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2847481A JPS57143655A (en) 1981-03-02 1981-03-02 Main storage controlling system

Publications (2)

Publication Number Publication Date
JPS57143655A true JPS57143655A (en) 1982-09-04
JPS6113265B2 JPS6113265B2 (en) 1986-04-12

Family

ID=12249638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2847481A Granted JPS57143655A (en) 1981-03-02 1981-03-02 Main storage controlling system

Country Status (1)

Country Link
JP (1) JPS57143655A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259356A (en) * 1985-05-13 1986-11-17 Fujitsu Ltd Memory intervention control system
JP2002289124A (en) * 2001-03-23 2002-10-04 Noritake Itron Corp Dot matrix phosphor display apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259356A (en) * 1985-05-13 1986-11-17 Fujitsu Ltd Memory intervention control system
JP2002289124A (en) * 2001-03-23 2002-10-04 Noritake Itron Corp Dot matrix phosphor display apparatus

Also Published As

Publication number Publication date
JPS6113265B2 (en) 1986-04-12

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