JPS5793460A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5793460A
JPS5793460A JP16977380A JP16977380A JPS5793460A JP S5793460 A JPS5793460 A JP S5793460A JP 16977380 A JP16977380 A JP 16977380A JP 16977380 A JP16977380 A JP 16977380A JP S5793460 A JPS5793460 A JP S5793460A
Authority
JP
Japan
Prior art keywords
time
bank
busy
channel
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16977380A
Other languages
Japanese (ja)
Other versions
JPS619657B2 (en
Inventor
Hidehiko Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16977380A priority Critical patent/JPS5793460A/en
Publication of JPS5793460A publication Critical patent/JPS5793460A/en
Publication of JPS619657B2 publication Critical patent/JPS619657B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To change the apparent cycle time, by holding non-selection and extending the output of a storage busy circuit, if an access request is not selected with the output of the storage busy circuit. CONSTITUTION:If an access request 6N is not selected at a time t1 of a channel 3N, it is held in an access reserve holding section 7, before a corresponding bank (i) is vacant at a time t3, the busy state is extended until a time t4 at a busy information extending section 8 as to the bank (i) through ''the bank (i) reserve'' information from the section 7. At the time t4, the busy information corresponding to the bank (i) shows busy state and a priority selection circuit 5 causes no selection even if the access request to the bank (i) by the accessed device 3B is preset. At a time t5, the channel 3N having the higher priority is selected with priority, allowing to permit accessing by the channel 3N.
JP16977380A 1980-12-02 1980-12-02 Memory access control system Granted JPS5793460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16977380A JPS5793460A (en) 1980-12-02 1980-12-02 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16977380A JPS5793460A (en) 1980-12-02 1980-12-02 Memory access control system

Publications (2)

Publication Number Publication Date
JPS5793460A true JPS5793460A (en) 1982-06-10
JPS619657B2 JPS619657B2 (en) 1986-03-25

Family

ID=15892589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16977380A Granted JPS5793460A (en) 1980-12-02 1980-12-02 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5793460A (en)

Also Published As

Publication number Publication date
JPS619657B2 (en) 1986-03-25

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