JPH05318983A - Raster plotter - Google Patents

Abstract

PURPOSE:To obtain a raster plotter capable of outputting a figure at a high speed by a method wherein a low costed DRAM is used as an image memory, and an image memory control means which transmits serially its image data to an image recording part at a high speed in non-synchronization with a CPU, is arranged. CONSTITUTION:A principal part of a raster plotter is composed of a printer engine 10 and a controller including a CPU 23 or the like. In that case, an image memory 27 performs writing and reading of an image data according to drawing data. Further, the image data developed on the image memory 27 is transmitted serially to the printer engine 10 being an image recording part with an image data reading counter 28i of a memory control part 28. Furthermore, the read fout parallel image data is converted to a serial data with a register circuit 28j. Besides, respective addresses of start and end of reading are stored with a register 28d. Then, the image data is transmitted serially at a high speed according to a signal from the image recording part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster plotter for inputting character data, image data, vector data and the like.

[0002]

2. Description of the Related Art In a conventional raster plotter, a central processing unit (CPU) that manages an image memory reads image data from the image memory and writes the image data in a parallel / serial out register, or a direct memory access controller. The image data on the image memory is read out one-dimensionally at consecutive addresses from the start address designated by (DMAC), and this is written in the parallel-in / serial-out register.

Further, in order to transfer image data serially at high speed, a dual port memory having a built-in shift register is used, and writing and serial transfer are performed asynchronously to increase the transfer speed.

When an image processor is used,
The main CPU that manages the image processing processor issues a get command to the image processing processor, two-dimensionally reads the image data from the specified address via the image processing processor, and writes it in the parallel-in / serial-out register. ..

[0005]

In the conventional raster plotter described above, when the image data is read by the CPU that manages the image memory and the parallel-in / serial-out register is written, the image is recorded in the image recording section. Transfer speed becomes slow.

Further, in order to transfer the image data on the image memory to the image recording unit two-dimensionally by the direct memory access controller (DMAC), the rows and columns are arranged so that the image data can be represented two-dimensionally. The image memory address control circuit is required. In addition, the cost of using the dual port memory is generally higher than that of the DRAM.

Further, when the image processor is used to issue the get command to read the data on the image memory, the read / write cycle by the main CPU slows down the transfer rate.

[0008]

In order to solve these problems, the present invention provides an image memory for writing or reading image data and image data developed on the image data to an image recording unit at high speed. An image data read counter for serial transfer, a register circuit for converting read parallel image data into serial data, a register for storing a read start address and an end address, and a signal from the image recording unit A raster plotter characterized by comprising a control circuit for serially transferring data at high speed. further,
In the present invention, a refresh control circuit connected to the image memory for performing refresh control is further provided, and the refresh operation mode is changed during a period in which image data is being read to the image recording unit.

[0009]

According to this structure, the image data for one page is generated by the signal from the image recording unit based on the read start address and the end address stored in the register of the image data written in the image memory. High-speed serial transfer is possible. Lower cost DRA
When M is used for the image memory, the refresh control is changed during the period when the image data is being read, so that the normal mode and the high speed page mode are switched, an efficient refresh operation becomes possible, and the image data is transferred at high speed. Transfer is possible.

[0010]

1 shows an embodiment of a raster plotter according to the present invention, which is a printer engine 10
And the controller 20. The controller 20 includes a parallel interface 21, a serial interface 22, a central processing unit (CPU) 23,
Memory (EPROM) 24, memory (EEPROM) 2
5, memory (MASKROM) 26, image memory (DR
AM) 27, a memory controller 28, an engine interface 29, a timer 31, a DIP switch 32, cartridge units 33, 34, and the like.

The parallel interface 21 and the serial interface 22 are interface parts for inputting characters, images, vector data, etc., and the memory 24 is for inputting, analyzing, exchanging data, writing or reading to the image memory 27, and image recording. A program for outputting image data to the printer engine 10, which is a part of
For example, it is a memory in which a program for performing the operation shown in the flowchart of FIG.
The U23 executes the program, is connected to the image memory 27 by an address bus and a data bus, and writes / reads input data and develops character font image data, image data, and the like on the image memory 27.

The character, image and vector data input from the parallel interface 21 or the serial interface 22 is stored in the image memory 2 of the DRAM by a program written in the memory 24.
Written in 7. In this case, the image memory 27 is used as a buffer memory in which data is temporarily written or read. The input data written in the image memory 27 is analyzed and converted, and the character data and the like are converted into character fonts written in the memory 26 and expanded in the image memory 27. The vector data is written as raster data in the area of one page developed on the image memory 27. When the input data is written on the image memory 27 by the CPU 23, the image memory 27 is refreshed by the memory control unit 28.

A concrete example of the memory control unit 28 is shown in FIG. 2 together with its peripheral circuits. In the figure, 28a is a CPU interface, 28b is a multiplexer and row address comparison circuit, 28c is a DRAM interface, 28d is a BC (BUS CONTROL) register, 28e is a refresh time generator, 28
f is a timing generator, 28g is an arbiter, 28
h is a memory address part, 28i is a read counter, 2
8j is a parallel / serial conversion register.

Of the elements constituting each part of FIG. 2, CP
The U interface 28a receives the address and various control signals from the CPU 23 and DACKs the CPU 23.
Has the function of sending and receiving control signals such as signals,
The multiplexer and row address comparison circuit 28b includes
The function for outputting an address to the memory based on the address from the CPU 23 is compared with the internally accessed row address at the time of the previous access and the currently accessed row address, and the result is compared with the timing generator 28f. It has the function of sending to. Further, the refresh time generator 28e has a function of generating a refresh request signal at a set time interval in the internal refresh mode. The arbiter 28g is a CPU
23. The timing generator 28f has a function of arbitrating access from 23 and a refresh request. , CAS, WE signal output timing and a function of generating a row address / column address switching signal.

In addition, the DRAM interface 28c
From the timing generator 28f to the image memory 27
To output the RAS, CAS, and WE signals to the image memory 27, a function to output an address to the image memory 27 generated by the multiplexer 28b, and a function to execute a specified pause, refresh cycle, and test mode after power-on. Have. The memory address unit 28h has a function of outputting an address signal corresponding to a memory addressing set externally, and further enables a weight setting corresponding to each memory, performs weight control according to the setting, and generates a DACK signal. And the function of performing. The BC register 28d is a register for setting the weight for the memory or each element addressed by the address signal, and the CPU 2
3 has the function of controlling the generation of the DACK signal according to the set value written.

The engine interface 28 has a parallel / serial conversion function corresponding to the video interface of the printer engine 10, and outputs bit data expanded in the image memory 27 at high speed asynchronously by a page signal, a line signal and a video clock. Have the function to Further, the read counter 28i is used for the image memory 27.
Is a counter for reading bit data to be output to the engine interface 28 from the image memory 27 by the read start address, the number of dots for one line, the number of lines for one page (read end address) written by the CPU 23. It has a function of reading out the bit data expanded by the video clock.
The parallel / serial conversion register 28j is a register for converting into serial bit data to be output from the engine interface 29 by a video clock.

In such a configuration, the CPU 23 and C
An address bus and various control signal lines are connected to the PU interface 28a, and an address from the CPU 23 is sent to the DRAM interface 28c via the multiplexer and row address comparison circuit 28b.
Alternatively, the address to the memory or the like is output from the memory address unit 28h. The CPU interface 28a that returns a DACK signal to the CPU 23 generates a DACK signal according to the weight setting for each device written in the BC register 28d. The DRAM interface 28c selects various signal outputs from the output timing signal from the timing generator 28f to the image memory 27, various signal outputs to the memory address, a low address (lower bit) of the memory address, and a column address (upper bit). Output.

The timing generator 28f is a CPU
An address strobe, a read / write signal, and a refresh request signal from an arbiter 28g that determines and adjusts the priority order of the read / write cycle and the refresh cycle are received from the CPU side via the interface 28a, and RAS is supplied to the memory side. It outputs CAS and WE signals. The refresh request signal is generated by the refresh time generator 28f at regular intervals and sent to the arbiter 28g. Read counter 28i
From the image memory 27 to the engine interface 29
Is a counter for reading the bit data to be output to the multiplexer and row address comparison circuit 28b.
The image memory 27 is addressed from the DRAM interface 28c via the, and the written data is output to the data bus and input to the parallel / serial conversion register 28j.

The read address to be written in the BC register 28d is a read start address (position) and a read end address (position) corresponding to one page of image data on the image memory 27, and a plurality of line data (raster data) are stored. This is shown two-dimensionally, and is a setting for reading data in units of 16 bits or 8 bits as in the example in FIG. As a setting method for the image data for one page, a read word address and a dot address are written to the BC register 28d as a read start position, and a horizontal length dot number and a line direction, which are the line direction of the image data, are read end positions. Write the number of vertical dots (vertical line length) perpendicular to. in this case,
The BC register 28d requires four lines, and the respective values are preset in the read counter 28i as necessary,
The image data is transferred to the parallel / serial conversion register 28j by the video clock corresponding to the horizontal side long dot number and the line signal corresponding to the vertical side long dot number, and the video data as the serial signal is sent to the printer engine 10. More specifically using FIG. 3, when reading the data in the image memory 27, from the read start position represented by the read word address and the dot address,
It is performed in units of 16 bits (1 word) and is input to the parallel / serial conversion register 28j. In this case, when the data for one line is the number of dots on the horizontal side, for example, 34 dots, only the upper 2 bits of the third read data are valid. The reading end position is determined from the number of horizontal side long dots and the number of vertical side long dots (the number of lines) perpendicular to the line direction in FIG.
Then, it becomes the upper 2 bits of the read data of the 9th time.

Next, FIG. 1 to FIG. 3, FIG. 4 and FIG.
The operation related to the present invention will be described using. First, when outputting the image data expanded on the image memory 27 to the printer engine 10 which is an image recording unit, the image memory 2
7 from the read start position or read start address of the image memory 27 corresponding to the image data for one page to the read end position or read address of the memory control unit 28 (B
C register) 28d (step S in FIG. 4)
1), a start command from the engine interface 29 to the printer engine 10 (START in FIG. 5)
Is sent (step S2 in FIG. 4). Upon receiving the start command, the print engine 10 outputs a page signal (PAGE. SYC in FIG. 5) to the engine interface 29 (step S3 in FIG. 4), and D of the memory controller 28 is output.
RAM refresh mode switching (step S in FIG. 4)
5) and the read counter 28i of the DRAM are set (step S6 in FIG. 4).

Further, the address bus of the image memory 27 is disconnected from the CPU 23 or the like and connected to the read counter 28i of the memory control unit 28. In this case, the image memory 27 is refreshed in the high speed page mode, and the refresh operation is performed intermittently. The memory control unit 28 performs the high-speed page mode / normal access mode of the image memory 27 and the setting of the refresh interval according to the page signal output from the printer engine 10.
Therefore, the refresh operation in the high speed page mode is controlled by the line signal (LINE.SYNC in FIG. 5) output from the printer engine 10. When this line signal is received by the memory control unit 28 (step S7 in FIG. 4), the memory control unit 28 enters the read mode and the parallel / serial conversion register 2
The image data is transferred to 8j (step S8 in FIG. 4).
It In this case, the transfer of the image data is performed by V shown in FIG.
IDEO. Video data (V in Fig. 5) based on CLK
IDEO. Output as DAT). Then, DRA
The M read counter 28i is controlled to count up (step S9 in FIG. 4), and the row is updated (steps S10, S11, S12 in FIG. 4 and step S9).
13). Then, returning to step S7, the read operation of the next line is executed. The memory control unit 28 outputs a page signal (PA in FIG. 5) output from the printer engine 10.
GE. SYC), line signal (LINE.SY in FIG. 5)
C), the video clock (VIDEO.CLK in FIG. 5) is input from the engine interface 29, the parallel / serial conversion register circuit 28j for serial conversion with the read counter 28i is controlled, and the video data (VIDEO.DAT in FIG. 5) is input. Output.

By the page signal (PAGE. SYC in FIG. 5) output from the printer engine 10 in this way, the image memory 27 is switched from the CPU 23 and the peripheral circuits to the memory control unit 28, and the 1 on the image memory 27 is switched.
Image data for a page is read by the read counter 28i of the memory control unit 28 and a line signal (LINE.SY in FIG. 5).
C) and video clock (VIDEO.CL in FIG. 5)
K), it is transferred to the parallel / serial conversion register 28j and sent to the printer engine 10 as line data (serial data) for one page.

The CPU 23 and peripheral circuits are the image memory 2
7 and the memory control unit 28, and has a plurality of bus configurations in which the address bus and the data bus are not shared,
The image data in the image memory 27 is transferred to the parallel / serial conversion register 28j by the memory control unit 28, and while being sent as video data to the printer engine 10, the CPU 23 and the peripheral circuits can perform other operations. It will be possible. For example, when the memory for the input buffer is provided, the data to be expanded next on the image memory 27 can be buffered to reduce the waste of the data transfer time from the outside to the interface section.

When the page signal (PAGE.SYC in FIG. 5) is not obtained in the step of FIG. 4, the refresh mode is switched to the normal mode in step S15, and the normal mode is written in step S16. The read operation will be performed.

[0025]

As described above, according to the raster plotter of the present invention, a low-cost DRAM is used as an image memory, and the image data expanded on the image memory is transferred to the image recording unit at high speed asynchronously with the CPU. By providing the image memory control means capable of serial transfer, a raster plotter capable of high-speed drawing can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a controller and a printer engine showing an embodiment of a raster plotter according to the present invention.

2 is a block diagram of a memory control unit shown in FIG. 1. FIG.

FIG. 3 is a diagram showing image data read out from an image memory.

FIG. 4 is a flowchart when outputting image data.

5 is a timing chart explaining the operation of the engine interface shown in FIG. 2. FIG.

[Explanation of symbols]

 10 Printer Engine 20 Controller 21 Parallel Interface 22 Serial Interface 23 Central Processing Unit (CPU) 24 Memory (EPROM) 25 Memory (EEPROM) 26 Memory (MASKROM) 27 Image Memory (DRAM) 28 Memory Controller 28a CPU Interface 28b Multiplexer and Row Address comparison circuit 28c DRAM interface 28d BC register 28e Refresh time generator 28f Timing generator 28h Memory address 28i Read counter 28j Parallel / serial conversion register 29 Engine interface 31 Timer 32 DIP switch 33 Cartridge unit 34 Cartridge unit S1 to S16 step

Claims (2)

[Claims] 1. An image memory for writing or reading image data corresponding to drawing data such as graphics, characters and images, and image data developed on the image memory is serially transferred at high speed to an image recording section. For reading the image data, a register circuit for converting the read parallel image data into serial data, a register for storing (addressing) a read start address and an end address, and an image by a signal from the image recording unit. A raster plotter comprising a control circuit for serially transferring data at high speed. 2. A refresh control circuit connected to the image memory for refresh control is further provided.
During the period of reading the image data to the image recording unit,
The refresh operation mode is changed.
Raster plotter.