JPH08282053A - Image data converter circuit - Google Patents

Abstract

PURPOSE: To realize high speed HV conversion processing by once storing the data on a DRAM in a read buffer by the quantity of 16 bites to transmit the same to an HV conversion register at a high speed and transmitting the data after HV conversion to a write buffer at a high speed to again rewrite the same on the DRAM as data of 16 bites. CONSTITUTION: A microprocessor 101 performing the control of data is connected to a CDRAM 102 being a memory containing the accumulation of image data and an HV conversion register 103 by an address bus. The CDRAM 102 is constituted by providing a DRAM of 4MBits, an SRAM of 16KBits, a read buffer(RB) capable of reading data of 128 bits at once from the DRAM and a write buffer(WB) capable of rewriting data of 128 bits on the DRAM at once on one chip. Further, an address decoder circuit 104, a CDRAM control signal generating circuit 105 and HV conversion address decoder circuits 107-109 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting print data of a recording apparatus having a recording head of a serial scan printing system, and more particularly to a circuit for converting raster image data horizontally and vertically according to the recording head.

[0002]

2. Description of the Related Art Conventionally, a recording apparatus using a dot impact method, a thermal method, or an ink jet method having a plurality of recording elements as a recording head of a printer or the like moves a recording head in a direction perpendicular to a conveyance direction of recording paper. Generally, a method (serial scan method) in which printing is performed while printing one line and a recording sheet is conveyed by the width of the recording head at the stage when printing of one line is completed and recording is repeated is performed. As image data to be recorded, data corresponding to the width of the recording head is sequentially transferred to the recording head, and the recording element is driven every time the distance corresponding to one pixel is moved to form an image.

However, the image data sent from the host computer is often continuous data in the raster direction, and it is necessary to change the horizontal data to vertical data (hereinafter referred to as HV conversion).

Conventionally, as a conversion processing means for raster data, there are a method by software and a method by hardware, and in each case, a means for converting the raster data from the horizontal direction to the vertical direction for each bit is used. . However, such a method requires a long conversion time, and as a coping method therefor, Japanese Patent Laid-Open No. 63-20067.
As shown in Japanese Patent Laid-Open No. 4 (1994), there has been proposed a special memory for storing data to be HV converted, which is provided for one band scan of the head and is used for sequential conversion at high speed. However, since the circuit scale becomes large in this method, a method has been proposed in which data setting for HV conversion is performed by the MPU and the conversion itself is performed by hardware. Further, in order to perform HV conversion at a higher speed, the MPU simply specifies the address of the memory in which the data to be converted is stored, and the control circuit performs the control of reading data from the memory, converting the data, and writing back the data. The circuit configuration is Japanese Patent Application No. 7-135.
Proposed in 34.

Here, as an example of the data conversion time according to the conventional example, in order to convert the data of 24000 bytes necessary for printing a band with a print width of 3000 dots and a head width of 64 dots to HV conversion 24008 times. Since the read-modify-write cycle is started, 300 nS is required for one read-modify-write cycle.
The time required for V conversion was 300 nS × 24008 = 7202400 nS = 7.2024 mS. In addition, the size of the HV conversion register is increased so that one read-modify-write cycle can
In the conventional example in which 6-bit conversion is possible, the conversion is completed in about 1/2 of the above time (= 3.6024 mS).

[0006]

In the above-mentioned conventional example, the data conversion time is calculated assuming a monochrome 360 DPI printing printer. However, when colorization or higher quality printing is required in the future, the data amount will be increased. However, this conversion time leads to a decrease in printing speed because the conversion time increases to 4 times, 8 times, and 16 times. For example, in a printer having a color recording head of 4 colors at 1440 dpi (4 times the resolution), when trying to HV convert data for A4 size (210 mm × 297 mm), the total data amount becomes [{(210 ÷ 25.4) × 1440} × {(297 ÷ 25.4) × 1440}] × 4≈ [{1488 × 8} × {2104 × 8}] × 4 = 801472512 bits, and 16-bit conversion time is 300 nS Therefore, the conversion time for the total amount of data is 801472512/16 × 300 nS ≈15.03 seconds, and the printing time becomes long only for simple data conversion.

Therefore, an object of the present invention is to provide a higher speed HV conversion circuit with a relatively small circuit scale. It is an object of the conventional example to improve the point that "only one byte or two bytes can be HV converted at one access to a low-speed DRAM", which is a factor that hinders higher-speed HV conversion.

[0008]

In the conventional example, a higher speed H
In order to improve the point that "only 1 byte or 2 bytes can be HV converted at one access to a low-speed DRAM", which is a factor that hinders V conversion, activation of the HV conversion circuit and HV conversion are performed.
A circuit that can simultaneously perform a means for indicating a memory location where the conversion data is present and the pre-conversion data stored in the low-speed memory are read into the read buffer once for the amount of data required for the HV conversion, and then the HV conversion is performed from the read buffer. The operation of transferring to the write register at high speed, transferring the converted data in the HV conversion read register to the write buffer at high speed, and writing back from the write buffer to the low speed memory is performed within the read modify write cycle of the low speed memory. It is composed of a control circuit.

In order to realize the above, as shown in FIG.
A method may be considered in which a plurality of DRAMs are arranged so that the data bus width of the RAM is the same as the total number of bits of the HV conversion register, and the DRAM and the HV conversion register are directly connected to each other. The number of pins is extremely increased. 2) The capacity of DRAM is increased more than necessary. 3) The circuit for converting the data bus width is required for the MPU to access the data of DRAM and HV conversion register. This is not feasible.

Therefore, the above low-speed memory, read buffer, write buffer, and data bus width conversion circuit
By using the cache DRAM configured on the chip, the high-speed HV conversion circuit is realized by a small-scale circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows H of each embodiment of the present invention.
FIG. 3 is a block diagram showing a part of a control circuit of a printer having a V conversion circuit. In FIG. 1, reference numeral 101 is a microprocessor for controlling data, etc., and includes a CDRAM 102, which is a memory including an accumulation of image data, an HV conversion register 103, and its control circuit, an address bus: A <2.
3. ． 0>, data bus: DQ <15. ． 0>, control signals: CLK1, CLK4, AS *, etc.

In CDRAM, 4M Bits (256K
X16) DRAM and 16KBits (1Kx16)
128 bits (8 times at a time from SRAM and DRAM of
X16) Read buffer (RB) that can read and store data, and 128 bits at a time in DRAM
A memory element in which a write buffer (WB) capable of rewriting data for s (8 × 16) and a single chip is used is used.

This memory device has an external clock CLK4.
In synchronization with the control signals CS #, CMd #, RAS #, CA
By changing S #, DTD #, G #, CMs #, CC #, WE #, the external data is changed to DQ <15. ． 0> terminal (Din terminal) to input As <9. ． 0> Store in one block of the write buffer specified by the address bus,
When the total of 128 blocks of data of 8 blocks is stored in the write buffer, it is written back to the DRAM. At the same time,
128-bit data of DRAM can be temporarily stored in the read buffer, and the data in the read buffer is A
s <9. ． 0> address bus specified by 8 blocks of 16-bit data is DQ <15. ． > 0 terminal (Dout
Output).

In the preferred embodiment, the synchronous clock of the CDRAM:
As the CLK4, a synchronous clock of the MPU: a signal having a frequency four times that of the CLK1 (one cycle of 60 nsec) was used. This CL
The period of 15 ns of K4 is the minimum clock cycle time of this CDRAM.

The DRAM in the CDRAM is allocated to the addresses $ D0000 to $ D7FFFF of the MPU, and the SRAM in the CDRAM is the address $ M of the MPU.
It is allocated to D80000 to $ D807FF.
There is an address decoding circuit 104 for that purpose, and the MPU
When the DRAM accesses the DRAM, it is a DRAM chip select signal from the address decoding circuit: DRAMCS
When * occurs and the SRAM is accessed, the SRAM chip select signal: SRAMCS * occurs.

This DRAMCS * signal and SRAMCS
* Signal and MPU system lock: CLK1, address strobe signal: AS * indicating that there is an effective address on the address bus, read / write signal indicating data bus transfer signal: RD / WR *, odd / even address Least significant address bit for discrimination: A <0> and CDR
From the AM synchronous clock: CLK4, the CDRAM control signal generation circuit 105 causes the CDRAM control signal: chip select signal: CS # and data line output control signal: G #.
When the DRAM is accessed at the same time that the DRAM clock is generated, the DRAM clock control signal: CMd #, the row address strobe signal: RAS #, the column address strobe signal: CAS #, the DRAM data transfer direction signal: D
When controlling the TD # and accessing the SRAM and the read buffer and the write buffer, the SRAM clock control signal: CMs # and the SRAM data transfer direction signal: C
C # and SRAM read / write signal WE # are generated. The address decoding circuit 106 is arranged so that the address bus A <18. ． 1> 18 signal lines
Ad <9. 0 as a row address / column address signal of 0/8. ． 0> and the address bus A <10. ． 1> 10 signal lines are directly As <9. ． 0>, and to specify a block of the read / write buffer, As <9. ． Address signals 0 to 7 are output to 0>.

To activate the HV conversion circuit, $ E0000
~ Performed by reading the $ E7FFFF address. This memory space is allocated to the DRAM memory space $ D0.
It corresponds to 0000 to $ D7FFFF, for example HV
Data to be converted 24000 bytes is $ D3800
0 to $ D3DDBF MPU is $ E38000
~ By accessing $ E3DDFB address, HV
The conversion circuit starts.

Therefore, the CDRAM control signal generation circuit 105 receives the output signal HVCS * of the HV conversion address decoder circuit 107 for detecting the timing when the upper 5 bits of the address bus becomes "11100", and the CDRAM control signal generation circuit 105 converts the 128-bit data for HV conversion. CMd #, RAS #, CAS #, DT to transfer from DRAM to read buffer
The D # signal is changed in synchronization with the CLK4 signal.

When the transfer of 8 words to the read buffer is completed, the HV conversion data 128 stored in the read buffer is stored.
bits are As <2. ． While changing 0> address from 0 to 7, 8 words are sequentially transferred to the HV conversion write register (see FIG. 2) in synchronization with CLK4. When the data transferred to the HV conversion register is read via the HV conversion read register (see FIG. 2), the data is HV converted. In order to write the 8 × 16 bits data after HV conversion from the HV conversion read register to the write buffer in the CDRAM, CMs # and CC # are controlled so that 8 words of data have As <2. ． The HV conversion read registers 0 to 7 selected by the 0> address are sequentially transferred to the write buffer in synchronization with CLK4.

After the transfer is completed, the data written in the write buffer is written back to the DRAM. In the HV conversion write address selector circuit 108 and the HV conversion read address selector circuit 109, one of the selection signal lines of the eight registers is AS <2. ． 0> is selected.

Next, the structure of the HV conversion register will be described with reference to FIG. Eight HV conversion write registers WREGO ~
WREG7 is composed of a 16-bit data latch circuit, and the most significant bit and the seventh bit of each HV conversion write register.
The bit is connected to the HV conversion read register 0 (RREG0). Similarly, the second upper bit and the sixth bit are connected to the HV conversion read register 0 (RREG1),
Finally, the 8th bit and the least significant bit are connected to RREG7.

Next, the signal timing of each block will be described and the operation of the present invention will be described with reference to FIG.

(Activation of HV conversion circuit) First, $ D380
To perform HV conversion on the data stored after 00, M
The PU executes the instruction to read the address $ E38000. Then, "E38000" is output to the address bus in the S0 cycle of the system clock: CLK1. Upon receiving this address, the HV conversion write register address decoder circuit causes the HVCS * signal to fall. Upon receiving the HVCS * signal, the CDRAM control signal generation circuit causes the enable signal G # of the data output pin of the CDRAM.
To "low" to enable data input / output. At the subsequent falling edge of CLK4, CMd # for controlling the clock to the DRAM is set to "Hi" and DR in the CDRAM is set.
Allows access to AM. The operation of the DRAM so far is the "DRAM power down (DPD) mode".

(DRAM → RB transfer) Next, when the AS * signal from the MPU becomes “low” and the HV conversion execution is officially started, the chip select signal CS # of the CDRAM is sent at the subsequent falling edge of CLK4. "Low"
And set the row address strobe signal RAS # to "low".
At the same time, the DRAM address bus Ad <9. ． 0>
$ Corresponding to the upper 10-bit address of $ 38,000
Outputs 1C0. Then, the CDRAM enters the "DRAM active (ACT) mode" for one cycle from the next rising edge of CLK4, and the 1 specified by the row address is entered.
Page data is called. At the next falling edge of CLK4, the RAS # signal is set to "Hi" to wait for the column address input for one cycle. During this time, "DRAM
"no operation (DNOP) mode".

Next, the column address strobe signal CAS # is output.
The lower 8 bits are output to the address bus at the same time as the falling edge. In the example of FIG. 3, Ad <9. ． For 0>, since the upper 2 bits are not used, "00" is set, and the lower 3 bits are forced to be "000". Remaining Ad <
7. ． 8 to 4 bits of MPUAdd are substituted into the 5 bits of 3> to become “00000”. At this time, if the DRAM data transfer control signal DTD # is "Hi", this cycle is "DRAM read transfer (DRT) mode". Then, in about 20 ns, 8-word (128-bit) data is transferred to the read buffer (RB). Since it is desirable that the DRAM operation is in the DNOP mode during this transfer, CAS # is raised and DTD # is also set to "Hi".

(RB → HV conversion write register transfer) Next, in order to write the data before HV conversion in the read buffer into the HV conversion write register, the CAS # signal is raised and the CMs # signal is set to “Hi” at the same time. The read buffer so that data can be output to the external terminal. The buffer operation so far is "SRAM power down & data hold (SPD) mode".

Since the HV conversion data is determined in the read buffer at the next falling edge of the CLK4 clock, the WE # signal is set to "Hi" and As <9. ． 0> Address is changed from 0 to 7. Then, the 16-bit data of blocks 0 to 7 of the read buffer are sequentially output onto the data bus, and the data are output as As <9. ． 0>
The HV conversion write register is latched based on the bus address. As <9. ． When CMs # is set to "low" at the timing when 0> 7 is output to the bus, the last data is output in the next cycle. The buffer operation up to this point is the "buffer read (BR) mode". Continued 2
The cycle is a wait time inserted for determining the data in the HV conversion register group, and the buffer operation during this period is the "SPD mode".

(HV conversion read register → WB transfer) Next, in order to write back the data after HV conversion in the DRAM, data of 8 words may be sequentially transferred from the HV conversion read register to the write buffer. Therefore, CMs that enable the buffer operation after the 2-cycle wait operation
# Raise the signal. At the next timing, the WE # signal is set to "Lo" to determine the data transfer direction of the buffer.
At the same time, the As <9..0> address bus is sequentially incremented from 0 to 7 in synchronization with the falling edge of the CLK4 clock to increase the HV conversion read register RRE.
The data of G0 to RREG7 is sequentially output to the data bus, and As <9. ． The contents of the data bus are sequentially written into the write buffer blocks 0 to 7 represented by the lower 3 bits of 0>. A total of 128 bits of data are written in the write buffer at eight rising edges of the CLK4 clock and can be written back to the DRAM. As <9. ． When 0> 7 is output to the address bus and the CMs # signal is set to "Low" at the same time, the buffer operation is in the "buffer write (BW) mode" until the last data is latched in the next cycle. It becomes "SPD mode".

(WB → DRAM transfer) Next, in order to write back the decided HV converted data in the write buffer to the DRAM, the CAS # signal is set to "Low" at the falling timing of the CLK4 clock, and Ad <9. ． ． 0> Output the column address bus to the address bus. Then, in the next cycle, the DRAM operation is "DRAM write transfer (DW
T1) mode ”. The CAS # signal is raised at the next falling edge of the CLK4 clock, waits for one clock, then CMd # is set to“ Low ”, and the RAS # signal is set to“ Lo ”.
When w "is set and the DTD # signal is set to" Low ", DRA
M starts the "precharge (PCG) mode".
The RAS # signal and DTD # signal are set to "H" at the next timing.
At the same time when the operation for the DRAM is completed by setting i "
Since a series of operation commands for the CDRAM has been completed, C
The S # signal is also set to "Hi". After that, the HVCS * signal and G * signal are set according to the rising timing of the AS * signal.
Set to "Hi", and the HV conversion of 16-byte image data is completed.

(Calculation of conversion time) CDRAM operation and CP
Due to the synchronization of the U operation and the number of weights of the CPU, the HV conversion time of 16 bytes in one cycle is 480 n seconds (CPU
Will operate at 16.7 MHz for 5 waits). Similar to the conventional example, the print width is 3000 dots, the print raster data for the head width is 64 dots, and the data of 24000 bytes is HV.
Since 24000/16 CDRAM access cycles are activated for conversion, one CDRAM access cycle requires 480 nS, so the time required for HV conversion is 480 nS x 24000/16 = 720000 nS = 0.72 mS. , Time required for HV conversion in the conventional example 3.60
It is about 80% (5 times) faster than 24mS.

In addition, in a printer equipped with a color recording head of 4 colors at 1440 dpi (4 times the resolution), the time required for conversion when the data of A4 size (210 mm × 297 mm) is HV converted is all data 80147251.
Since the conversion time of 2 bits to 128 bits is 480 nS, 801472512 ÷ 128 × 480 nS ≈3.01 seconds.

(Second Embodiment) In the first embodiment, the timing at which the data before HV conversion is read from the DRAM (third embodiment)
In the section of FIG. A), the data bus DQ <15. ． 0> is in the idle state. During this time, data can be written from the data bus to the write buffer, and if each part of the HV conversion processing is operated in parallel, higher-speed HV conversion can be performed.

Therefore, in explaining the second embodiment, the difference between the circuit blocks of the first embodiment and the second embodiment is that the C of FIG.
Since only the generation timing of each signal of the DRAM control signal generation circuit 105 is different, the second embodiment will be described with reference to the timing chart of FIG.

(Activation of HV conversion circuit) In FIG. 4, M
It is assumed that the PU has finished writing the data stored in $ D38000 to $ D3800F to the HV write register. Then $ D38010 to $ D380
To convert the data stored in 1F to HV, $ E38
An instruction to read address 010 is executed.

Then, the system clock: S of CLK1
"E38010" is output to the address bus in 0 cycle. Upon receiving this address, the HV conversion write register address decoder circuit causes the HVCS * signal to fall.
Upon receiving the HVCS * signal, the CDRAM control signal generation circuit causes the enable signal G # of the data output pin of the CDRAM.
Is set to “Low” to enable data input / output. Next, at the falling edge of the CLK4 clock, CMd # that controls the clock to the DRAM and CMs # that controls the clock to the SRAM and the buffer are set to "Hi" to enable access. The DRAM operation so far is "DRAM power down (DPD) mode", and the buffer operation is "SRAM power down & data hold (SPD) mode".

(DRAM → RB transfer) and (HV conversion read register → WB transfer) Next, the AS * signal from the MPU becomes “Low”, and H
Following the official start of V conversion execution, the next CLK4
The chip select signal CS # of the CDRAM is set to "Low" at the falling edge of the row address strobe signal R
At the same time when AS # is set to "Low", the DRAM address bus Ad <9. ． 0> outputs $ 1C0 corresponding to the upper 10-bit address of $ 38010.

Then, the CDRAM is in the "ACT mode" for one cycle from the next rising edge of CLK4, and the data for one page designated by the row address is called. RAS # on the next falling edge of CLK4
The signal is set to "Hi" and the input is waited for one cycle. During this period, the "DNOP mode" is set. Next, the column address strobe signal CAS # is lowered, and at the same time, the lower 8 bits are output to the address bus.

In the example of FIG. 4, Ad <9. ． For 0>, since the upper 2 bits are not used, "00" is set, and the lower 3 bits are forced to be "000". Remaining Ad <
7. ． 8 to 4 bits of MPUAdd are substituted into the 5 bits of 3> to become “00001”. At this time, if the DRAM data transfer control signal DTD # is "Hi", this cycle is "DRT mode". Then, in about 20 ns, 8-word (16-bit) data is transferred to the read buffer (RB). Since it is desirable that the DRAM operation is in the DNOP mode during this transfer, CAS # is raised and DTD # is also set to "Hi".

On the other hand, since the data bus and write buffer of the CDRAM can operate in parallel, $ D38 written in the HV conversion write register in the previous HV conversion cycle.
The data after HV conversion of the data of 000 to $ D3800F may be sequentially transferred from the HV conversion read register for 128 bits to the write buffer.

Therefore, the HVCS * signal falls, and the CMs # signal that enables the operation of the buffer and the SRAM in the CDRAM rises at the subsequent fall of CLK4. At the same time, the CC # signal and WE # are set to "Low" in order to determine the data transfer direction of the buffer and the SRAM.
The buffer operation so far is "SPD mode", and C
LK4, address bus As <9. ． 0>, the contents of the buffer and SRAM are not affected even if the data bus changes.

Further, in synchronization with the fall of the CLK4 clock after the fall of the AS * signal which confirms the start of the HV conversion, As <9. ． 0> The address bus is incremented in order from 0 to 7, and the HV conversion read register RREG
Output from 0 to RREG7 data bus sequentially,
At the rising edge timing of the next CLK4 clock, As <9. ． 0> The contents of the data bus are sequentially written into the write buffer blocks 0 to 7 represented by the lower 3 bits of the address bus. A total of 128 bits of data are written in the write buffer at eight rising edges of the CLK4 clock and can be written back to the DRAM.

(WB → DRAM transfer) and (RB → HV
Conversion write register transfer) At this timing, the DRA is already in the read buffer.
Since the data read from M is fixed, it is possible to write back the HV converted data written in the write buffer to the DRAM or write the read buffer data in the HV conversion write register.

First, the data in the write buffer is DRA
In order to write back to M, the CAS # signal is set to “Low” at the falling timing of the CLK4 clock, and Ad <9. ．
0> Output column address to address bus. Then, in the next cycle, the operation of the DRAM becomes "DWT1 mode". C at the next CLK4 clock timing falling edge
Turn on the AS # signal, wait one clock, and then CMd #
Is set to "Low", the RAS # signal is set to "Low", and D
When the TD # signal is set to "Low", the DRAM becomes "PCG
Mode "is started. In the second embodiment, $ D3800
The 16-byte HV-converted data from 0 to $ D3800F will be written back to $ D38010 to $ D3801F, and will be stored at a position where the address is offset by 16 bytes from the original data.

At the same time, in order to write the data before HV conversion on the read buffer into the HV conversion write register,
The WE # signal is set to “Hi”, and As <9. ． 0> address from 0 to 7
If you change to, read buffer blocks 0 to 7
Since each of the 16-bit data up to is output on the data bus one after another, they are latched in the HV conversion write register. As <9. ． 0> When 7 is output to the bus, CMs # is set to “Low” and Cs # is set in the next cycle.
The signal is set to "Low", and at the same time, the WE # signal is also set to "Low"
To Up to this point, the series of operation commands for the CDRAM is completed, and thereafter, the HVCS * signal and G # signal are set to "Hi" at the rising timing of the AS * signal.
The HV conversion of the byte image data is completed.

(Calculation of conversion time) CDRAM operation and CP
Due to the synchronization of the U operation and the number of weights of the CPU, the HV conversion time of 16 bytes per cycle is 360 nsec.
Will operate at 16.7 MHz for 3 waits). Similar to the conventional example, the print width is 3000 dots, the print raster data for the head width is 64 dots, and the data of 24000 bytes is HV.
Since 24000/16 + 1 CDRAM access cycles are activated for conversion, 360 nS is required for one CDRAM access cycle, so the time required for HV conversion is 360 nS × (24000/16 + 1) = 540360.
nS = 0.54036 mS, and the time required for HV conversion in Example 1 was 0.7.
It is about 25% faster than 2 mS.

In addition, in a printer equipped with a color recording head of 4 colors at 1440 dpi (4 times the resolution), the time required for conversion when the data of A4 size (210 mm × 297 mm) is HV converted is the total data 80147251.
Since the conversion time from 2 bits to 128 bits is 360 nS, 801472512 ÷ 128 × 360 nS ≈2.25 seconds.

[0048]

As described above, according to the first invention, 16 bytes of data on the DRAM are temporarily stored in the read buffer and transferred to the HV conversion register at high speed, and the data after HV conversion is transferred to the write buffer at high speed. A control circuit for transferring and again writing 16 bytes to the DRAM once, and the above DRAM
Cache DRAM in which multiple data buses are connected between a read buffer and a read buffer or between a DRAM and a write buffer
By using, high-speed HV conversion processing can be realized.

According to the second aspect of the present invention, the data on the DRAM is temporarily stored in the read buffer for 16 bytes, and at the same time, the data after HV conversion is transferred at high speed to the write buffer, and the data HV conversion register of the read buffer is transferred. Data in the write buffer again in parallel with high-speed transfer to
By using the control circuit rewritten on the RAM, higher-speed HV conversion processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a control circuit of each embodiment of the present invention.

FIG. 2 is a conversion conceptual diagram of an HV conversion register.

FIG. 3 is an HV of the CDRAM according to the first embodiment of the present invention.
It is a conversion timing chart.

FIG. 4 is an HV of a CDRAM according to a second embodiment of the present invention.
It is a conversion timing chart.

FIG. 5 is a block diagram in which a conventional example is developed in accordance with the gist of the present invention.

[Explanation of symbols]

 101 MPU that controls the control 102 Cache DRAM that is a memory 103 HV conversion register 105 CDRAM control signal generation circuit 502 DRAM array with expanded data width

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuyuki Tsukada 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yoshiaki Kanaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non-Incorporated (72) Inventor Hiroshi Uemura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. A recording head in which a plurality of recording elements are arranged in a line in a vertical direction, and raster direction sequential data is converted in a vertical direction, and the converted data is converted while moving the recording head in a sheet width direction. In an image data conversion circuit used in a serial scan type recording apparatus for recording, a relatively low-speed memory means for storing raster data, a read buffer for temporarily reading out a part of the raster data at one time, and a vertical direction for horizontal data. Conversion register group for converting to direction data, means for sequentially transferring data from the read buffer to the conversion register group, means for sequentially transferring vertical direction data read from the conversion register group to a write buffer, and the write buffer An image data conversion circuit having means for writing back the data in the memory means to the memory means at once. 2. A dynamic random access memory (DRAM) is used as the memory means, and the DR is used.
2. The image data conversion circuit according to claim 1, wherein the transfer data width between the AM and the read buffer is equal to or larger than the data amount read at one time. 3. The image data conversion circuit according to claim 2, wherein a transfer data width between the write buffer and the DRAM is equal to or larger than a data amount to be written back at one time. 4. The image device according to claim 2, wherein a memory device in which a data transfer data bus between each of the DRAM, the read buffer, and the write buffer is integrated on one semiconductor substrate is used. Data conversion circuit. 5. A control means for executing data transfer from the conversion register group to the write buffer in parallel with the timing of data transfer from the memory means to the read buffer. The image data conversion circuit described in. 6. The control means for executing data transfer from the write buffer to the memory means in parallel with the data transfer timing from the read buffer to the conversion register group. The described image data conversion circuit.