JPH09174952A - Color printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high speed color printer having high image data transfer rate in the printer. SOLUTION: A print engine 200 comprises four RAMs providing image butters dedicated for K, C, M, Y wherein the tour RAMs have a common address bus and dedicated data buses. A controller 100 produces a four color image data of K, C, M, Y based on a data received from a host and transfers the four color data simultaneously to the engine 200 through dedicated buses. The engine 200 designates an identical address for the four RAMs through the common address bus and writes a four color latched data simultaneously into the four RAMs. When an image data for one pass is accumulated in the four RAMs, the engine 200 reads out the four color data simultaneously from the identical address of these RAMs and transfers the four color data to a head driver.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color printer for printing a color image based on a plurality of color data,
In particular, it relates to improvement of a technique for transferring a plurality of color data to a print head via an image buffer.

[0002]

2. Description of the Related Art Generally, a color printer analyzes a command and data received from a host device, and forms a plurality of color dots such as black (K), cyan (C), magenta (M) and yellow (Y). Image data is generated, and the print heads of the plurality of colors are driven based on the image data of the plurality of colors, so that the dots of the plurality of colors are aggregated to print a color image that looks like the original image as a whole. A certain type of color printer has a processor called a "controller" that generates image data of the above-mentioned multiple colors from data and commands received from a host device, and a processor different from this controller, and the image data from the controller And a “print engine” that executes an actual printing operation based on the above. In another type of color printer, the same processor performs the two data processing functions of the controller and the print engine. In any printer, image data of multiple colors generated in the printer is once written in a RAM area called an "image buffer", and a predetermined set amount (for example, the print head prints in one main scan). Amount to do,
That is, when the image data of "one pass" is accumulated in the image buffer, the image data is read from the image buffer and transferred to the driver circuit of the corresponding print head. While the print heads of the respective colors perform main scanning on the surface of the paper, a dot image for one pass is formed on the paper based on the image data of "one pass" of the corresponding color. This operation is repeated until all lines have been printed.

FIG. 1 shows a schematic structure of a conventional color printer.

In the conventional color printer 2, a single RA is used.
An image buffer 16 and other work areas are formed in M10. Therefore, as shown in the figure, the storage area of the RAM 10 is divided into several parts, and K, C, M, and Y color image buffers are assigned to the respective divided parts. The RAM 10 is connected to, for example, an 8-bit data bus 6 and a 24-bit address bus 8. The controller 4 analyzes the data and command from the host device to generate K, C, M, Y image data, and then, the data bus 6 and the address bus 8.
Through the image buffer 1
Send to 0. The image data is sent to the data bus 6 in 8-bit units, and the data of one color is continuously sent by the data amount corresponding to one row. Therefore, for example, when K image data is sent for one line, C data is sent for one line, M data is sent next, Y data is sent next, and so on. The lines are sequentially transferred to the image buffer 16 line by line.

When such transfer is repeated, the image data for one pass is finally stored in the image buffer 16. For example, if each color print head has 64 inkjet nozzles, one for each color.
Image data for one row × 64 nozzles is for one pass.
When the image data for one pass is accumulated in the buffer 16, the image data is then read from the buffer 16 and transferred to the head driver 14 through the data bus 6. Also at this time, each color image data is sequentially read out one row at a time, in the same manner as the above-described writing.

[0006]

The problem of the above-mentioned conventional apparatus is that it takes too much time to print an image of high quality and high resolution. That is, the higher the image quality and resolution of an image, the larger the amount of image data. Therefore, as one measure for enabling such an image to be printed at high speed, the processing speed of the controller 4 and the print engine has been increased. This can significantly improve the speed by improving the capacity and clock speed of the processor and improving the printing mechanism. However, in the conventional printer described above, the image buffer 16
Since data is written in and read out from the image buffer 16 inevitably, image data of a plurality of colors must be sequentially sent to the bus 6 in a fixed order, and as a result, the read / write speed of the image buffer 16 is significantly increased. Hard to raise.

In addition, since the image buffer 16 is formed in one RAM and the addresses of the buffer areas for the respective colors are different, when writing and reading data of a plurality of colors in the buffer 16, different addresses are set for the respective colors. It has to be calculated, which naturally complicates the calculation. Since this complicated address calculation takes a considerable amount of time, it is the main cause of difficulty in improving the processing speed.

From these circumstances, in the conventional printer, even if the processing speed of the processor and the printing mechanism is increased, the data transfer speed around the image buffer is not increased to the extent corresponding to it, and as a result, it takes a long time to print. I will end up.

Therefore, it is an object of the present invention to provide a color printer which has a high transfer rate of image data inside the printer and therefore is capable of high-speed printing.

[0010]

In the color printer of the present invention, the image buffer is composed of a plurality of memory chips, and each memory chip provides a buffer area for each color. Then, the same address is designated to the plurality of memory chips through the address bus. Therefore, when writing and reading data of multiple colors to and from the image buffer, the same address of multiple memory chips is specified. Therefore, the address calculation is not a complicated one to calculate different addresses for each color, It will be easy to calculate one common address for. As a result, the time for address calculation is shortened, the overall data transfer time is shortened, and the printing speed is improved.

Preferably, a plurality of memory chips are each connected to a dedicated data bus. As a result, image data of a plurality of colors can be simultaneously written to and read from the same address of a plurality of memory chips. Therefore, the data transfer time is further shortened and the printing speed is improved as compared with the case of sequentially transferring a plurality of color data.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the configuration of the main part of a color printer according to an embodiment of the present invention.

This printer analyzes data and commands from a host device (not shown) and outputs K, C, M, and Y 4
A controller 100 for generating color image data,
The print engine 200 receives image data from the controller 100, temporarily stores the image data in the image buffer, and then reads the image data to execute a printing operation.

The controller 100 analyzes the data and command from the host device to generate image data of four colors K, C, M, and Y, and the generated image data of four colors. Engine 20
The data transfer unit 120 transfers the data to 0. The image generation unit 110 is actually a software function realized by a CPU (not shown) in the controller 200 executing an imaging program. The image data of four colors generated by this software function is stored in the registers 122, 124, 126, 1 of the data transfer unit 120.
Set to 28. These registers 122, 124,
The 126 and 128 are connected to the data receiving section 210 of the print engine 200 via dedicated 8-bit data buses 132, 134, 136 and 138, respectively.

The print engine 200 includes a data receiving section 210 for receiving the image data transferred from the data transfer section 120, image buffers 252, 254, 256, 258 for storing the received image data.
A CPU (including a gate array circuit for transferring image data) 240 that controls reading / writing from and to the image buffer and other parts of the print engine, and a head driver 260 that drives a print head (not shown) are provided. .

The data receiving section 210 is the controller 10
4 latches 212, 214, 216 respectively connected to the four data buses from the data transfer unit 120 of 0,
218, the four latches latch image data on their respective data buses. Data transfer unit 1
In order to match the timing of the data transfer from 20 with the latch in the data receiving section 210, the data transfer section 12
Strobe signal STRO indicating transfer timing from 0
BE is sent to the data receiving section 210, and the data receiving section 21
From 0, a busy signal BUSY indicating whether latching is possible is returned to the data transfer unit 120. The strobe signal S
TROBE is also supplied to the CPU 230 and is also used for determining the image data transfer (DMA transfer) timing to the image buffers 252, 254, 256, 258.

The image buffer has four RAM chips 2 which provide buffer areas dedicated to K, C, M and Y colors.
52, 254, 256, 258. These four RAM chips (that is, four color image buffers) have exactly the same configuration. Each color image buffer 252, 254, 256, 258 has an 8-bit data bus 222, 224, 226, 2 respectively.
The corresponding latch 2 of the data receiving unit 210 via 28
It is connected to the outputs of 12, 214, 216 and 218. The four 8-bit data buses 222, 224, 226 and 228 of the image buffers are integrated as a 32-bit data bus and connected to the CPU 240 and the head driver 260. The address terminals of the four color image buffers 252, 254, 256, 258 are connected to one common address bus 230 from the CPU 240. Therefore, the same address of the four-color image buffer can be simultaneously designated by one address signal, and the four-color image data can be written or read at the same time.

In the above configuration, the controller 100
Of the data transfer unit 120 of the registers 122, 124, 1
Image data of four colors (8 bits for each color, 32 bits in total) generated by setting to 26 and 128 are synchronized to the four buses 132, 134, 136 and 138 at the same time by the strobe signal STOROBE (low enable). Send out. The data receiving unit 210 of the engine 200 responds to the falling edge of the strobe signal STOROBE,
4 sent on buses 132, 134, 136, 138
Latch the color image data at the same time. Next, CPU
The DMA controller in 240 makes strobe signal ST
Triggered by the rising edge of OROBE, the image data of these four colors is latched by the latch 21 of the data receiving unit 210.
Image buffer 25 from 2, 214, 216, 218
DMA transfer to 2, 254, 256 and 258 simultaneously.
The busy signal is output after the image data is latched and is transferred to the image buffer.

By repeating the above operation, the image data for one pass is stored in the image buffers 252, 254, 25.
6 and 258, the image buffer 2
52, 254, 256, 258 to the head driver 26
Image data for one pass is transferred to 0. At this time also, the image data of four colors is stored in the 32-bit data bus 22.
8 bits are simultaneously transmitted through 0.

FIG. 3 is a flowchart showing in more detail the processing when generating image data and writing it in the image buffer.

First, the controller 100 receives a command and data from the host device (S1), creates color image data based on the command and data (S2), and from there, each color component of the area (pass) to be printed now. Is extracted (S4). Next, the CPU 240 of the engine 200 causes the image buffer 252, which is the transfer destination of the image data,
Calculate the start address of 254, 256, 258 (S
4). In this case, since the image data of four colors are written at the same address in each buffer, it is not necessary to calculate the address for each color, and the common 1
You only have to calculate the addresses.

Next, the controller 100 converts the first 8 bits of the extracted four-color image data into the register 12 of the corresponding bus 132, 134, 136, 138.
Set to 2, 124, 126, 128 (S5-S
8) Then, the 8-bit data of these four colors are simultaneously sent to the buses 132, 134, 136, 138 (S1).
0). Then, as described above, the data of these four colors is latched by the data receiving unit 210 and then DMA
Transfers four image buffers 252, 254,
Simultaneously written to the above calculated addresses of 256, 258. After that, the DMA controller of the CPU 240 causes the image buffer 2 to receive the next 8-bit data.
The write address of 52, 254, 256, 258 is incremented by 1 (S9).

For each of the individual 8-bit data forming the image data for one pass, the above step S is carried out.
The processing of 5 to S9 is performed, and this series of processing is repeated until all the image data for one pass is transferred (S10).

FIG. 4 shows an engine 200 for transferring image data from the image buffer to the head driver.
Shows the flow of processing in.

As described above, the data of each color is written in the image buffers 252, 254, 256, 258 (S21), and when data for one pass is accumulated (S22), the CPU 240 next Image buffers 252, 254, 256, 258 which are transfer sources of
Is calculated (S23). Also at this time, one address common to all the image buffers may be calculated.

Next, the image buffers 252, 254, and 25 are synchronized with the response timing of the head driver 260.
From the calculated addresses of 6 and 258, 8-bit image data of 4 colors are simultaneously read out, and the head driver 2
It transfers to 60 (S24). Next, the read address of the image buffer is advanced by 1 (S25), and step 24
repeat.

When all the image data for one pass has been transferred to the head driver 260 (S26), the paper is fed for line feed (S27). Then, again, the series of processes described above is repeated for the next pass.

As can be seen from the above description, in this embodiment, image data of four colors are simultaneously written in the image buffer, simultaneously read from the image buffer, and transferred to the print head. Therefore, compared to a conventional printer that transfers four-color data sequentially, at least a four-fold improvement in transfer speed can be obtained even if a RAM having the same access speed is used. Further, since an image buffer is constructed by a separate RAM for each color so that data of four colors can be written and read at the same address, the address calculation is simplified and the transfer speed is further improved. as a result,
Higher print speeds are obtained compared to conventional color printers.

FIG. 5 shows the structure of a color printer according to the second embodiment of the present invention.

In this printer, as in the printer shown in FIG. 2, four RAM chips 462, 464, 46 are provided.
6 and 468 make up a 4-color image buffer,
The address terminals of these four image buffers are connected to the C of the engine 400 by one common address bus 440.
It is connected to the PU 450. However, the data bus for sending image data is not dedicated for each color,
It is configured to share one 8-bit bus 330, 430 with four colors.

More specifically, the controller 30
The 0 data transfer unit 320 has one register 320 shared by four colors, receives data of one of the four colors from the image generation unit 310 in the register 320, and receives the data through one 8-bit data bus 330. Transfer to engine 400. At the time of this data transfer, the data transfer unit 320 matches the timing by strobe signal STROBE (low enable) and busy signal BUSY with the data receiving unit 410 of the engine 400 as in the case of the previous embodiment. The color selection signal K, C, M or Y for indicating the color of the data to be transferred is supplied to the signal lines 342 and 34.
4, 346, 348 to the data receiving unit 410.

The data receiving section 410 of the engine 400 is
It has one latch 411 shared by four colors and responds to the falling edge of the strobe signal STROBE by the bus 33.
Latch the image data sent on 0. Also,
The data receiving unit 410 includes four AND circuits 412,
414, 416, and 418, and these four AND circuits receive the color selection signals K, C, M, and Y from the signal lines 342, 344, 346, and 348 and the chip select signal 420 from the CPU 450, respectively. And The outputs of the AND circuits 412, 414, 416, 418 are the image buffers 462, 464, 466, 4 of the corresponding colors.
It is added to 68 as a chip select signal.

The CPU 450 includes a gate array forming a dedicated circuit for data transfer. This CPU45
0 is triggered by the rising edge of the strobe signal STROBE, and the four image buffers 462, 464, 466, 4 through the data bus 430 from the latch 411.
The image data is DMA-transferred to one of 68. At this time, since the chip select signal is given from the CPU 450 to the data receiving unit 411, the chip select signal is added only to the image buffer of one color selected by the color selecting signal from the data transfer unit 320. Therefore, the latched image data is written in the image buffer of the corresponding color.

When the image data of a certain color is written in the image buffer for one pass, the image data of the next color is similarly sent from the data transfer section 320 and written in the corresponding image buffer. The data of one pass for all four colors is stored in the image buffers 462, 464, 466, 4
After being stored in 68, the CPU 450 then transfers the data in the image buffers to the head driver 470 via the bus 430. At this time, as in the case of writing to the image buffer, the CPU 450 sequentially selects the image buffer of four colors by the chip select signal and sequentially outputs the image data of four colors to the head driver 47.
Transfer to 0.

FIG. 6 shows the flow of processing for generating image data and transferring it to the image buffer in this embodiment.

First, the controller 300 creates each color image data of the pass to be printed based on the command and data received from the host device (S31-).
S34). Next, the CPU 450 of the engine calculates the start address of the image buffer which is the transfer destination of the image data (S34). In this case, since data of any color is written at the same address, one common address may be calculated once.

Next, the data transfer section 320 of the controller 300 activates the K color selection signal K, and sets the address calculated by the CPU 450 of the engine on the address bus 440 (S35). Then, the data transfer unit 320 transfers the K 8-bit image data to the register 32.
It is set to 2 and output to the bus 330 (S36). Then, as described above, the 8-bit data of K is K
Of the image buffer 462 of FIG. After that, the CPU 450 increments the address by 1, and the operation of step S36 is repeated for the 8-bit data next to K.

When all the K data for one pass is finally written in the image buffer 462 (S37), the data transfer section 320 makes the color selection signal K inactive (S38). Next, the data transfer unit 320 activates the color selection signal C of C, and the CPU 450 sets the start address calculated previously on the address bus 440 (S39). Then, the data transfer unit 320 sends the 8-bit image data of C to the bus 330 (S40), and the 8-bit data of C is written in the head address of the image buffer 464 for C. Then, C
The PU 450 advances the address by 1 (S40), and the next 8
Step 40 is repeated for the bit data.

When the writing of all the C data for one pass is completed (S41), the color selection signal C is made inactive (S42), and then the image data of M is similarly written in the image buffer 466 for M. (S43 to S4
6). After that, similar writing is performed for Y (S
47-S50).

As described above, image data of four colors of K, C, M and Y are sequentially written in the image buffer for each pass. At this time, since all four colors are written at the same address in the image buffer, the address calculation only needs to be performed once at the beginning, and after that, it is only necessary to mechanically increase the calculated address according to the progress of writing. The ease of this address calculation is the same in the data transfer from the image buffer to the head (the detailed operation description is omitted because it will not be necessary for those skilled in the art). Therefore, compared to the conventional printer, the time for address calculation (which takes a long time in the past) can be saved,
As a result, high speed printing is possible.

Although the preferred embodiment of the present invention has been described above, the present invention can be implemented in various different modes other than the above. For example, although the above embodiment is a printer provided with a controller and a print engine separately, the present invention can be implemented in a printer in which one processor performs both data processing functions of the controller and the engine.

The present invention can be implemented not only by the printer that handles the image data of four colors as in the above embodiment, but also by the printer that handles only three primary colors. Furthermore, in the future,
In order to enhance the expressiveness, it is expected that a printer that handles many colors exceeding four colors will appear. However, the present invention can be implemented in such a printer, and the advantage of the present invention is that the number of colors is large. Becomes more significant.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a conventional color printer.

FIG. 2 is a block diagram showing the configuration of the first embodiment of the present invention.

FIG. 3 is a flowchart showing a process when image data is generated and written in an image buffer in the first embodiment.

FIG. 4 is a flowchart showing a flow of processing for transferring image data from an image buffer to a head driver in the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a flowchart showing a process when image data is generated and written in an image buffer in the second embodiment.

[Explanation of symbols]

100, 300 Controller 200, 400 Print Engine 120, 320 Data Transfer Unit 210, 410 Data Receiver 252, 254, 256, 258, 462, 464, 4
66,468 Image buffer (RAM) 240,450 CPU

Claims (5)

[Claims] 1. A color printer having an image buffer for storing image data of a plurality of colors before being transferred to a print head, wherein the image buffer provides a buffer area dedicated to each of the plurality of colors. Including multiple memory chips,
A color printer characterized in that the plurality of memory chips are connected to an address bus for designating the same address. 2. The color printer according to claim 1, wherein the plurality of memory chips each have a plurality of dedicated data buses. 3. The color printer according to claim 2, wherein a circuit for writing the image data of the plurality of colors to the same address of the plurality of memory chips at the same time through the plurality of data buses, and And a circuit for simultaneously transferring the plurality of image data to the print head from the same address through the plurality of data buses. 4. The color printer according to claim 1, wherein the plurality of memory chips have a common data bus. 5. The color printer according to claim 4, wherein the plurality of color image data are sequentially written to the same address of the plurality of memory chips through the common data bus, and the plurality of memory chips. And a circuit for sequentially transferring the plurality of image data from the same address to the print head through the common data bus.