JPH04301466A - Image processor - Google Patents

Abstract

PURPOSE:To obtain a high grade image output by converting a density for an image data corresponding to an object picture element to a second print density higher than a first print density based on the result from a reference means, and outputting from an output means the image data converted by a conversion means. CONSTITUTION:After a VSYNC signal is inputted, white data is written in the whole address of an SRAM 2 at a non-input period of image data, the SRAM 2 is initialized, which is performed by a memory control circuit 5. At a smoothing logical circuit 13, image data of horizontal scanning 7 picture elements X vertical scanning 7 picture elements in circumference with center at print element is referred so as to convert the horizontal scanning direction into 4 data divided into 1200dpi by a predetermined algorithm and output as parallel data. The 4 data are converted into serial data by a parallel-serial conversion circuit and outputted to a printer engine as a smoothed image signal SVDO by a clock signal 4CLK having a frequency of 4 times that of an image clock VCLK.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus applied to a laser beam printer or the like, and more particularly to a signal processing circuit for increasing the definition of printed images.

0002

2. Description of the Related Art In recent years, laser beam printers have been widely used as output devices for computers. In particular, 3
Small machines having a resolution of about 00 dpi (dots per inch) are rapidly becoming popular due to their advantages such as low cost and compactness.

As shown in FIG. 13, a laser beam printer includes a printer engine section 201 that actually prints on a photosensitive drum based on dot data, and an external host computer 20 connected to the printer engine section 201.
The printer controller 2 receives the code data sent from the printer engine section 201, generates page information consisting of dot data (bit map data) based on this code data, and sequentially transmits the dot data to the printer engine section 201.
It consists of 02. The host computer 203 is a floppy disk 204 having application software.
The computer loads a program, starts the application software, and functions as, for example, a word processor.

Next, the process of printing operation in the printer controller 202 will be explained using FIG. 14.

In the figure, reference numeral 114 denotes an image memory for storing one page of bitmap data (image data);
115 is an address generator that generates an address for the image memory 114; 116 is an output buffer register that converts the image data read from the image memory 114 into an image signal VIDEO; and 117 is a well-known beam detector that is a horizontal synchronizing signal. A synchronous clock generation circuit 118 generates an image clock signal VCLK synchronized with the signal BD signal.
119 is a printer I/F which is an input/output unit for signals with the printer engine 201, and 120 is a host I/F which is an input/output unit for signals with an external host such as a personal computer. be.

[0006] In the above configuration, the operation when sending the image signal VIDEO to the printer engine will be explained.

First, when the printer controller 202 has prepared one page of image data in the image memory 114, it sends a print request signal PRI to the printer engine 201.
Send NT. The printer engine 201 uses this PRI.
When the NT signal is received, the printing operation starts, and the vertical synchronization signal V
When SYNC is accepted and printing is possible, the VSREQ signal is sent to the printer controller 2.
Send on 02. The printer controller 202 is a VSR
When the EQ signal is received, the vertical synchronization signal VSYNC is sent to the printer engine 201, and the VS
Count the predetermined time from the YNC signal. When the predetermined time count ends, the address generation section 115 sequentially generates addresses from the first address of the image data stored in the image memory 114, and reads out the image data. The read image data is input to the output buffer register 116 for each main scanning line. In order to perform printing from a predetermined position in the main scanning direction, the output buffer register 116 inputs the BD signal for each print line, counts the image clock signal VCLK for a predetermined pulse, and then starts printing from a predetermined position in the main scanning direction. line data to the VC
It is sent to the printer engine 201 as an image signal VIDEO synchronized with the LK signal. and printer engine 2
At step 01, the above-described image forming operation is performed.

By performing the above operation for each print page, printing is always performed at the same position on the paper.

[0009]

However, in recent years, there has been a demand for higher definition print output, and laser beam printers are no exception. Therefore, it is possible to increase the resolution of laser beam printers, but
For example, when the resolution is set to 600 dpi, which is twice that of 300 dpi, the capacity of the image memory required for the printer controller becomes four times that of the case of 300 dpi, resulting in a disadvantage that it becomes expensive. In addition, if you try to obtain the same printing speed as 300 dpi, the output frequency of image data will be four times as high, so the printer controller will also have to operate at four times the speed, which is a disadvantage in terms of both technology and cost. It will happen. On the other hand, when considering application software, most of them are made for a resolution of around 240 to 300 dpi, so if you consider 600 dpi
Even if a printer were made for i, there is a problem that it would not be compatible with these application software. Therefore,
A technology that takes advantage of the above application software and increases the resolution of print output is required.

The present invention has been made in view of the above-mentioned drawbacks of the conventional examples, and its purpose is to provide an image processing device that can obtain high-quality image output at low cost. be.

[0011]

[Means for solving the problem] Solving the above problems,
In order to achieve the object, an image processing apparatus according to the present invention is an image processing apparatus having a storage means for storing image data. an input means for inputting the image data, an initialization means for initializing the storage means based on the image data input by the input means, and a plurality of main scanning lines of the image data input by the input means are stored in the storage means. Each time, in the storage means, a reference means for referring to image data corresponding to the pixel of interest and pixels surrounding the pixel, and a reference means for referring to image data corresponding to the pixel of interest based on the reference result of the reference means. The second printing density is higher than the first printing density.
a conversion processing means for performing conversion processing on the printing density of the first
and output means for outputting image data converted by the conversion processing means.

0012

[Operation] According to this configuration, the input means inputs image data having the first printing density including the invalid period between vertical synchronization signals, and the initialization means is based on the image data inputted by the input means. The reference means initializes the storage means, and each time the image data inputted by the input means is stored in the storage means for a plurality of main scanning lines, the reference means stores an image corresponding to the pixel of interest and surrounding pixels of the pixel in the storage means. Referring to the data, the conversion processing means performs conversion processing on the image data corresponding to the pixel of interest based on the reference result of the reference means to a second printing density higher than the first printing density, and the outputting means performs the conversion processing. The image data converted by the means is output.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

(First Embodiment) A first embodiment of the present invention will be explained in the case of a 300 dpi laser beam printer.

FIG. 1 is a block diagram showing a first embodiment in which an image processing apparatus according to the present invention is applied to a laser beam printer. The printer shown in the figure mainly consists of a signal processing circuit 2.
05, a printer engine 201, a printer controller 202, and a transmission circuit 206. The signal processing circuit 205 of this embodiment is functionally located between the printer engine 201 and the printer controller 202, and the signal processing circuit 205 is functionally located between the printer engine 201 and the printer controller 202.
The resolution of a dpi image signal (hereinafter referred to as "VIDEO signal") in the main scanning direction is increased to 1200 dpi and is sent to the printer engine 201 as a smoothed signal (hereinafter referred to as "SVDO signal").

Next, other input/output signals of the signal processing circuit 205 will be explained. First, input signals from the printer controller 202 include a VIDEO signal, a vertical synchronization signal (hereinafter referred to as "VSYNC signal"), and a signal specifying ON/OFF of smoothing processing (hereinafter referred to as "SON signal"). Further, the input signal from the printer engine 201 is a horizontal synchronization signal (hereinafter referred to as "BD signal"). Next, as an output signal to the printer controller 202, an image clock signal (hereinafter referred to as "VCLK signal") which is the output clock of VIDEO and is synchronized with the BD signal.
). Furthermore, the CLK signal inputted from the oscillation circuit 206 is a signal used as a basic clock within the signal processing circuit 205, and has a frequency eight times that of the VCLK signal. The VCLK signal is created by dividing this CLK signal by eight at a timing synchronized with the BD signal, so the B
The synchronization accuracy for the D signal is 1/8 of its own period. Therefore, the deviation (jitter) of the image in the main scanning direction with respect to the BD signal is kept within 1/8 of one dot, and good image quality can be obtained.

Next, the signal processing circuit 205 according to the present invention will be explained.

2 and 3 are block diagrams showing the configuration of the signal processing circuit 205 according to the first embodiment, and FIGS. 4 and 5 are timing charts showing the relationship between the synchronization signal and image data in the first embodiment. , FIG. 6 is a timing chart for explaining the operation of the memory control circuit according to the first embodiment, and FIGS. 7 and 8 are diagrams for comparing and explaining data before and after printing density conversion.

In FIGS. 2 and 3, reference numeral 1 denotes an input/output control circuit that controls each of the above-mentioned input/output signals. 2 is a static RA with a memory capacity of 8K words x 8 bits.
M (hereinafter referred to as "SRAM"), 3 is an address counter that generates an address for SRAM 2, 4 is a latch having a three-state output, 5 is a memory control circuit that controls SRAM 2, address counter 3, and latch 4, 6
-12 are shift registers, 13 is a smoothing logic circuit, 14 is a parallel-to-serial conversion circuit, and 15 is a D flip-flop (hereinafter referred to as "D.FF").

Next, the operation of the above configuration will be explained.

As described in the conventional example, the printer controller 201 synchronizes with the VSYNC signal and prints the VID for one page after a predetermined time T1 has elapsed.
Start sending out the EO signal. This VIDEO signal is "white" data except during its output period. VSYN
FIG. 4 shows the relationship between the C signal and the VIDEO signal. On the other hand, the main scanning direction is synchronized with the horizontal synchronizing signal BD for a predetermined time T2.
At a later timing, transmission of image data for one main scanning line is started. In the above, the printer controller outputs image data in synchronization with the falling edge of the image clock signal VCLK. On the other hand, the signal processing circuit 20
In step 5, the image data is latched in the DFF 15 at the falling edge of VCLK. Subsequently, the latched image data is latched in latch 4 by a signal LCLK which is the VCLK signal delayed by 3/8 period. The output Q0 is the input/output pin I of SRAM2.
/O1 and written to a predetermined address. The written image data is read out at a timing before image data is written in the next cycle of the VCLK signal, and is input to the input terminal D1 of the latch 4. In this way, VCL
Image data is read and the next image data is written at the same address in the SRAM 2 within one cycle of the K signal. The timing of the above operation is shown in FIG. Then, when one main scanning line is completed, a reset signal (hereinafter referred to as "RST") is activated.
'') (generated at the beginning of the BD signal of the next main scan), the address counter 3 is reset. Immediately after this reset, a similar operation is performed for the next line of data. Therefore, data is written as white data in the SRAM 3 also during the period T2 in FIG. 5, which is the non-output period of image data. In other words, the data (
During this period, the data (invalid, that is, "white") is treated as image data. By repeating the above operation, the outputs Q0 to Q6 of latch 4 are supplied with continuous main scanning 7
Image data at the same position for a line will be output at the same time. In the above operation, after the VSYNC signal is input, white data is written to all addresses of the SRAM 2 during the period T1 in FIG. 4, which is a non-output period of image data, and the SRAM 2 is initialized. The above control is performed by the memory control circuit 5.

Next, the outputs Q0 to Q6 of the latch 4, which are image data for seven continuous main scanning lines, are input to shift registers 6 to 12, respectively. The shift register shifts sequentially in response to the rising edge of the image clock VCLK, and a total of 49 pieces of data, each with seven shift outputs, is input to the smoothing logic circuit 13.

The smoothing logic circuit 13 refers to image data of 7 main scanning pixels x 7 sub-scanning pixels around the current print pixel R, and divides the main scanning direction into 4 pixels corresponding to 1200 dpi according to a predetermined algorithm. The data is converted into three data a, b, c, and d and output as parallel data (see FIG. 7). The above four data a, b, c, d are converted into serial data by a parallel-to-serial conversion circuit 14, and a clock signal 4C having a frequency four times that of the image clock VCLK is generated.
The image signal LK is output to the printer engine as a smoothed image signal SVDO. Although the internal algorithm of the smoothing logic circuit 13 will not be described in detail, for example, in 300 dpi image data from a printer controller, diagonal lines printed as shown in FIG. 8(A) are smoothed as shown in FIG. 8(B). It is now possible to print.

The above operation is performed using a signal SO from the printer controller specifying ON/OFF of the smoothing process.
This is the case when N is valid (“H”), and when this SON signal is invalid (“L”), the data of the print pixel R is output as is. That is, when the data of the print pixel R is "black", "black" data is output for a, b, c, and d, and when the data of the print pixel R is "white", the data of a, b, c, and d are output.
"White" data is output for all b, c, and d. Then,
The output that is printed is the same as when printing using the VIDEO signal from the printer controller. By controlling the SON signal in this way, the printer controller can specify ON/OFF of the smoothing process according to the user's preference.

The signal processing circuit described above is, for example, an SRA.
The parts other than M are made into a gate array and configured on one chip as a signal processing IC, and the data output part of the conventional printer controller board is slightly modified to convert the signal processing IC into an SR.
By adding it together with AM, it is possible to provide a laser beam printer that can produce high quality images at low cost. In addition, for space efficiency reasons, the signal processing circuit can be replaced with SRAM.
It is also conceivable to incorporate this into a single chip, which would have the advantage of greatly reducing the number of input/output pins. Furthermore, it goes without saying that the signal processing circuit described above may be installed on the printer engine side.

Furthermore, in the above embodiment, a case has been described in which the area referred to during data conversion is 7 pixels in the main scanning direction x 7 pixels in the sub-scanning direction, but the invention is not limited to this.
For example, by referring to an area of 9 pixels in the main scanning direction x 9 pixels in the sub-scanning direction, a smoothing effect of higher quality can be obtained. Further, although the above embodiment describes an example in which image data of 300 dpi is converted into data with a density of 1200 dpi in the main scanning direction, the invention is not limited to this. It can also be converted. In this case, it can be realized by using an 8-bit parallel-to-serial conversion circuit 14 and using a clock eight times as large as VCLK as the output clock.

As explained above, according to the first embodiment, by converting the print data of recording pixels into data with four times the print density in the main scanning direction and recording, high quality can be achieved at low cost. Image output can be obtained.

(Second Embodiment) The first embodiment described above shows a case where image data is transmitted from the printer controller 201 using a VCLK signal generated by the signal processing circuit 205. Furthermore, conventional printer controllers generally generate an image data transfer clock that is synchronized with the BD signal internally, and furthermore, the synchronous clock generation circuit and other control circuits are located inside the gate array. Many signals such as clock signals are not output to the outside. On the other hand, the second embodiment shows a case in which a signal processing circuit that can also be used with the printer controller described above is used.

FIGS. 9 and 10 are block diagrams showing an example of the configuration of a signal processing circuit according to the second embodiment. In the figure, circuits having the same functions as those in the first embodiment described above are given the same numbers as in FIGS. 2 and 3, and their explanations will be omitted. In the second embodiment, the circuit numbers corresponding to those in FIGS. 2 and 3 are marked with a dot for the different configurations from the first embodiment. A particular difference is the control of input/output signals by the input/output control circuit 1'.

Next, signals different from those in the first embodiment will be explained.

FIG. 11 is a timing chart illustrating the operation according to signals in the second embodiment, and FIG. 12 is a circuit diagram showing the configuration of the input/output control circuit 1' of this embodiment. In the same figure, 51, 63, 64 are NOT circuits, 52 to 58
is D・FF, 59,60 is J-K・FF, 61 is NAN
D circuit, 62 is a 4-bit counter, 65-67 are selector circuits, 62 is a 4-bit counter, and 65-67 are selector circuits, respectively. The configuration of parts not directly related to the above explanation of operation will be omitted. First, an SBD signal is sent from the signal processing circuit 205' to the printer controller 202 as a horizontal synchronization signal. This SBD signal is a signal obtained by delaying the BD signal from the printer engine 201 by a time corresponding to one cycle of the VCLK signal. Further, 8CLK having a frequency eight times that of the VCLK signal is sent to the printer controller 202 as a clock signal. This 8CLK signal is stopped after the BD signal from the printer engine 201 is input until the SBD signal is output. This is the image data transfer clock synchronized with the SBD signal inside the printer controller 202.
This is so that after the SBD signal is input, it can be obtained by dividing the first 8 CLK by 8. That is, the horizontal scanning synchronization timing is created by the input/output control circuit 1'. Similarly, in the input/output control circuit 1', VCL
By obtaining the K signal, the image data transfer clock inside the printer controller 201 and the VCL
The K signal becomes a clock signal of the same phase. Therefore, image data can be accurately transferred without using the same clock on the sending and receiving sides.

Next, a control signal (hereinafter referred to as "DRC") is input from the printer controller 202 to the signal processing circuit 205.
(referred to as "T signal") will be explained. This DRCT signal is a signal specifying a state equivalent to the absence of the signal processing circuit 205. In other words, the DRCT signal is valid (L
), the VIDEO signal from the printer controller 202 is sent to the SVDO signal line, and the BD signal from the printer engine 201 is sent to the SBD signal line.
The CLK signal from the oscillation circuit 206 is output as is to the CLK signal line. This mode is effective, for example, in the following cases. VID from printer controller 202
By performing data conversion on the EO signal by the signal processing circuit 205 and sending it to the printer engine 201 as an SVDO signal, 3 lines in the sub-scanning direction for data reference are saved compared to the case without the signal processing circuit 205'. A time delay of seven dots occurs in the image data in the main scanning direction. Therefore, if printing is performed using the conventional control system of printer engine 201 and printer controller 202, the image will be shifted 3 dots downward and 7 dots to the right from the normal printing position. The above problem is caused by changing the value of T1 in FIG. 4 for 3 lines on the printer controller 202 side.
Moreover, the problem can be solved by shortening the value of T2 in FIG. 5 by 7 dots. However, if the above changes cannot be easily made in the printer controller 202, and if the accuracy of the printing position is more important than the smoothness of the image, the DRCT signal may be enabled (L).

Other operations in the signal processing circuit 205 are performed in the same manner as in the first embodiment. However, in FIGS. 9 and 10, SVDO', SBD', and 8CLK' are signals that do not depend on the DRCT signal.

As described above, in the second embodiment, fewer changes are required on the printer controller side, resulting in lower costs and a shorter development period.

The present invention may be applied to a system made up of a plurality of devices, or to an apparatus made up of one device. It goes without saying that the present invention can also be applied to cases where the present invention is achieved by supplying a program to a system or device. Further, in the first and second embodiments described above, a laser beam printer was used as an example, but the present invention is not limited to this, and can be applied to a dot impact type, thermal type, inkjet type, electrostatic type, etc. A recording type printer, thermal transfer type printer, or the like may be used.

[0036]

[Effects of the Invention] As explained above, according to the present invention,
High-quality image output can be obtained at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment in which an image processing apparatus according to the present invention is applied to a laser beam printer.

FIG. 2 is a block diagram showing the configuration of a signal processing circuit 205 according to the first embodiment.

FIG. 3 is a block diagram showing the configuration of a signal processing circuit 205 according to the first embodiment.

FIG. 4 is a timing chart showing the relationship between synchronization signals and image data in the first embodiment.

FIG. 5 is a timing chart showing the relationship between synchronization signals and image data in the first embodiment.

FIG. 6 is a timing chart illustrating the operation of the memory control circuit according to the first embodiment.

FIG. 7 is a diagram for comparing and explaining data before and after printing density conversion.

FIG. 8 is a diagram illustrating a comparison of data before and after printing density conversion.

FIG. 9 is a block diagram showing an example of the configuration of a signal processing circuit according to a second embodiment.

FIG. 10 is a block diagram showing a configuration example of a signal processing circuit according to a second embodiment.

FIG. 11 is a timing chart illustrating the operation according to the signals of the second embodiment.

FIG. 12 is a circuit diagram showing the configuration of an input/output control circuit 1' of this embodiment.

FIG. 13 is a diagram schematically showing a conventional example.

FIG. 14 is a diagram showing the configuration of a conventional laser beam printer.

[Explanation of symbols]

1 Input/output control circuit 2 SRAM 3 Address counter 4 Three-state latch 5 Memory control circuit 6-12 Shift register 13 Smoothing logic circuit 14 Parallel-serial conversion circuit 15 D flip-flop 51, 63, 64 NOT circuit 52-58 D flip-flop 59 and 60 are J-K flip-flops 61 is a NAND circuit 62 is a 4-bit counter 65-67 Selector circuit 62 4-bit counter 65-67 Selector circuit 201 Printer engine 202 Printer controller 205 Signal processing circuit 206 Oscillation circuit

Claims (2)

[Claims] 1. An image processing apparatus having a storage means for storing image data, an input means for inputting image data having a first print density including an invalid period between vertical synchronization signals, and the input means. initializing means for initializing the storage means based on the image data of the invalid period input by the input means; and the storage means for each time the image data input by the input means for a plurality of main scanning lines is stored in the storage means among,
a reference means for referring to image data corresponding to a pixel of interest and pixels surrounding the pixel; and a second print density higher than the first printing density for the image data corresponding to the pixel of interest based on the reference result of the reference means. An image processing apparatus comprising: a conversion processing unit that performs a conversion process on a printing density of the first conversion processing unit; and an output unit that outputs image data converted by the first conversion processing unit. 2. The image processing apparatus according to claim 1, wherein said conversion processing means includes selection means for selecting one of an execution mode and a non-execution mode of said conversion processing.