JPH0289284A - Arbitration circuit for 2-port memory - Google Patents

Abstract

PURPOSE:To surely inhibit simultaneous access to the same address by converting the high-order address signal of each address to an address signal for two words, holding the signal during the period of data access for two words and then applying the held output to a port arbitration part. CONSTITUTION:The title circuit is provided with address conversion parts 2a, 2b each of which converts a high-order address signal out of high-order and low-order address signals including two words for respective address buses formed correspondingly to respective ports of a memory into an address signal for the two words, address latch parts 3a, 3b respectively corresponding to respective address conversion parts 2a, 2b to hold the outputs of the conversion parts 2a, 2b and apply them to the port arbitration part and access detecting parts 4a, 4b prepared correspondingly to respective address conversion parts 2a, 2b to keep the corresponding address latch parts 3a, 3b at the holding state during the data access of two words based on the basis of the state of each address bus. Consequently, arbitration judgement corresponding to the address for two words can be executed and the arbitration can be surely executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention arbitrates data access to each baud (K) of a memory having two ports, and prevents simultaneous data access to the same address. This relates to a circuit that prohibits

[Conventional technology]

If a two-port memory has separate data and address buses connected to each port, and a separate processor is provided for each of these buses, it is possible for each processor to access data at the same address in the memory at the same time. An arbitration circuit is generally used to ensure that the address signals from each address bus are not When they are the same, only one of the processors is allowed to access the data.

[Problem to be solved by the invention]

However, since the data bus is 16 bits,
When accessing memory in units of words, the arbitration circuit should determine the upper address signal and lower address signal in correspondence with two words.
However, the arbitration circuit only judges the address signal for one word, and in data processing in units of two words,
This has the drawback that accurate data processing cannot be performed.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is configured by the following means.

In other words, the address conversion provided for each address bus converts the upper address signal in the upper and lower address signals indicating 2 words of each address bus provided corresponding to each port of the memory into an address signal of 2 words. , an address latch section provided for each address conversion section that holds each of these outputs individually and supplies them to the port arbitration section, and an address latch section that corresponds to the address conversion section during two-word data access based on the state of each address bus. Each address conversion section that holds the address is provided with nine access detection sections.

[Effect]

Therefore, when an upper address signal is applied from each address bus, this is converted into an address signal for two words, which is held in the address latch section during data access, and based on this, Since the port arbitration unit makes the arbitration decision, arbitration using two words worth of addresses is reliably performed.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram, and FIG. 2 is a timing chart showing the state of each part in FIG. 1. In FIG. Corresponding address bus 1
an address converter (hereinafter referred to as ADC) for each of a and 1b.
) 2m and 2b are provided, and these are the upper address signal and the lower address signal indicating two words of data, and the lower one bit is deleted, and
It has the function of converting into word address signals.

Each output of ADCZ&, 2b is connected to an address launch section (hereinafter referred to as ADf) 3m, 3b provided for each ADC2m, 2b.
These are held individually by ADC28,2.
Access detection unit (hereinafter referred to as ACD) provided for each b, 4m, 4
Based on the state of the address bus la+lb, the ACDs 4m and 4b are controlled by the ADLs 3m and 3b in response to the start of 2-word data access to the memory.
is held, and ADL is set in response to the end of data access.
CPOK on either one to clear 3m and 3b
AoL3m only during data access for 2 words due to
3b holds the outputs of AD02m and 2b individually.

These holding outputs are given to a port arbitration unit (hereinafter referred to as PMD) 5, where if the holding outputs of ADLs 3a and 3b are the same, a permission signal READY-A is sent that allows data access to each CPU. Only one of READY-A and READY-B is valid, and simultaneous access to the same memory address is prohibited. However, if each holding output is different, each permission signal READY-A, READY-B is valid.
-B are respectively enabled, and each CPU can freely access each individual address.

Therefore, as shown in FIG. 2, first, the address bus 11
When the upper address signal N (a) is generated and then the lower address signal N + 1 (a) is generated, the ADC 2m outputs each address signal N, according to the upper address signal N (1).
At the same time, ACDJ& causes the ADL3m to hold the two-word address signal indicated by N+1(a), but at this time, the address signal N(e) on the address bus 1b is not generated, and the address signal on the ADL3b is not generated. Since the contents are in the clear state, PMD5 sends the permission signal READY-A.
(b) is made valid and data access is performed by the CPU on the address bus 1b side.

Also, if the address signal N(c) is generated on the address bus 1b with a slight delay from the upper address signal N(&), this will become the address signal for two words from the ADC 2bK.
Similarly, since it is held by the ADL 3b, each input of the PMD 5 becomes the same, the enable signal READY-B(d) remains invalid, and access by the CPU to the address bus 1bll is prohibited.

On the other hand, as the lower address signal N + 1 (a) disappears, ACDJa clears ADL3m, so PM
If the inputs of D5 are not the same, now the enable signal READY
-B(d) must be enabled, address bus 1b
An access by the side CPU is made to address N in memory.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the upper address signal of each address bus is converted into an address signal for two words, this is held during data access for two words, and this held output is The details given to the port arbitration unit are that arbitration decisions are made according to the addresses of two words, and simultaneous access to the same address via each port of the memory is reliably prohibited, and the unit is two words. If the data processing is accurate, a remarkable effect can be obtained in the arbitration of the two-port memory.

[Brief explanation of the drawing]

The figures show embodiments of the present invention, with Figure 1 being a block diagram and Figure 2 being a block diagram.
The figure is a timing chart showing the states of each part in FIG. 1. 1 B, lb @ * * 11 address bus, 2 a
r 2b @e...address conversion section, 3m, 3b...
. . . Address latch section, 4m, 4b . . . Φ access detection section, 5. . . Port arbitration section.

Claims (1)

[Claims] In a circuit that arbitrates data access to each port of a memory having two ports, the upper address signal of the upper and lower address signals indicating 2 words of each address bus provided corresponding to each port is set to 2 words. an address converter provided for each of the address buses, which converts the address signal into an address signal; and an address latch part provided for each address converter, which individually holds each output of each address converter and supplies it to the port arbitration unit. and an access detection unit provided for each of the address conversion units, which holds the corresponding address latch unit in a holding state during two-word data access based on the state of each address bus. Arbitration circuit for 2-port memory.