JP2803588B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing superimposition processing and synthesis processing of image data.

[0002]

2. Description of the Related Art Image processing apparatuses are widely used in companies that issue publications such as newspaper companies and printing companies, as well as general facsimile machines. In particular, newspaper companies are rapidly adopting a spread version (A1 size version) and colorization of photographs in order to compete for sales and gain market share. For this reason, there is an increasing demand for constructing a system capable of making a two-page spread of an image and replacing a photograph / advertisement image in a timely manner when creating a newsprint by a host computer. There is also a demand for realizing these functions with an output device. In this case, it is necessary to efficiently and timely perform the superimposition processing and the synthesis processing of the images.

Conventionally, there is a technique disclosed in Japanese Patent Application Laid-Open No. 63-172563 as a technique for independently performing image combining processing. This technology includes storage means for storing an image for one screen, and storage means for storing an image for another screen. Then, these two storage means are read alternately, and the information is alternately processed line by line and synthesized.

[0004]

However, in the above-described technique, the synthesizing process is performed in units of one line, and recording is performed alternately in the sub-scanning holes. Can not. Further, there is no output device provided with the overlay processing function and the synthesis processing function. Therefore,
The system of the host computer is changed to perform the above-described overlay processing and the synthesis processing. However, when the system of the host computer is changed in this way, the scale of remodeling,
There is a problem that a great burden is added in terms of cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an image processing apparatus capable of performing overlay processing and synthesizing processing in the main scanning direction and outputting the result.

[0006]

In order to achieve the above object, an image processing apparatus according to the present invention comprises an image memory for storing image data from a host device, and image data from the host device and reading from the image memory. A superimposition processing circuit for superimposing the output image data, a write counter for specifying an address for writing the image data in the image memory, and a read for specifying an address for reading the image data from the image memory Same circuit configuration as counter
Control of the overlapping process and the combining process in
Simultaneous overlay processing and composition processing
At the same time, the image data to be combined is
A composition / overlapping processing control unit that reads alternately, and a CPU that instructs the composition / overlapping processing control unit to perform the superposition processing and the composition processing are provided.

[0007]

According to the above image processing apparatus, image data is written to the address of the image memory designated by the write counter. Then, the superimposition processing circuit superimposes the image data from the host device on the image data read out by the readout counter controlled by the synthesis / superposition processing control unit. After that, the combining /
Image data synthesis processing is performed under the control of the superimposition processing control unit.

Here, the above-mentioned superimposition processing and synthesis processing are performed on one sheet.
At the same time for each recorded image.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a synthesizing / overlapping processing control unit, and FIG. 3 is a circuit diagram of a superposition processing circuit. FIG. 4 is a schematic diagram showing a storage area of the image memory. As shown in FIG. 1, the image processing apparatus of this embodiment
It includes a PU 1, a superimposition processing circuit 2, an image memory 3, a write counter 4, a read counter 5, and a synthesis / superimposition processing control unit 6.

When the image processing apparatus receives the image data, the image processing apparatus receives the image data from a host device (not shown) such as a host computer.
Image data, data valid signal S2 and memory write signal S3 (image clock) at the time of memory writing to image memory 3
Are simultaneously the overlay processing circuit 2 and the synthesis / overlay processing control unit 6
To be entered.

Before the overlay processing circuit 2 receives each image data, the CPU 1 receives a line signal S1 indicating the number of lines of each received image data from a host device (not shown) in advance. . This line signal S1 is a timing signal for writing and reading of the image memory 3.

The CPU 1 inputs a superimposition processing signal C1 indicating the L level to the superimposition processing circuit 2 before the superimposition processing circuit 2 receives the image data which is not overwritten, and stores the image in the A block of the image memory 3. It has a function of instructing the combining / overlapping processing control unit 6 to store data and outputting an instruction signal C2 for operating the write counter 4 to the combining / overlapping processing control unit 6.

When the overlay processing circuit 2 receives the image data to be overwritten, an overwrite instruction signal S4 indicating that the image data is to be overwritten to the CPU 1 is sent from the host device to the CPU 1. And the CPU 1 instructs the synthesizing / overlapping processing control section 6 to store the image data in the C block of the image memory 3 and simultaneously outputs an instruction signal C2 for operating the write counter 4 to the synthesizing / overlapping processing control. It has a function of outputting to the unit 6.

Further, before receiving the image data to be overwritten by the overlay processing circuit 2, the CPU 1 outputs an H-level overlay processing signal C 1 to the overlay processing circuit 2, and
The image data stored in the block C is read out and the overwritten image data is written into the block B of the image memory 3, and the instruction signal C3 for operating the write counter 4 and the read counter 5 is combined / overlaid. It has a function of outputting to the processing control unit 6.

Further, when reading the image data in the image memory 3, the CPU 1 instructs the superposition processing circuit 2 to output the image data read from the image memory 3 to the output terminal 7. Further, as shown in FIG. 5, the CPU 1 instructs the synthesizing / overlapping processing control unit 6 to alternately read the image data of the A block and the B block of the image memory 3 in line units. ing.

As shown in FIG. 3, the overlay processing circuit 2
An AND gate 20 having a terminal 22 for inputting the superimposition processing signal C1 from PU1 and a terminal 23 for inputting image data from the C block of the image memory 3;
It comprises an OR gate 21 having a terminal 24 for inputting an output of 0 and a terminal 25 for inputting image data from a host device. Then, the output terminal 26 of the OR gate 21
Are connected to the image memory 3 and the output terminal 7 in FIG.

As a result, when the L-level superposition processing signal C1 is input from the CPU 1 via the terminal 22, the terminal 24 of the OR circuit 21 becomes L-level and the OR gate 21
Outputs the image data from the host device input via the terminal 25 to the output terminal 26 as it is. CPU1
, The H-level superimposition signal C1 is input from the image memory 3 via the terminal 23, the image data from the image memory 3 is output from the AND circuit 20, and the OR gate 21 outputs the image data from the AND circuit 20 And the image data from the host device are superimposed, and the overwritten image data is output to the output terminal 26.

The image memory 3 has a capacity capable of storing three A2 size image data. As shown in FIG. 4, the storage area is divided into A blocks, B blocks, and C blocks. I have. The capacity and storage area can be changed according to the specifications. In FIG. 1, a write counter 4 has a function of designating an address for writing image data in the image memory 3. The read counter 5 has a function of designating an address for reading image data from the image memory 3.

As shown in FIG. 2, the synthesizing / overlapping processing control section 6 has an input terminal 6 for inputting various signals from the CPU 1.
0 to 64 and an input terminal 6 for inputting the read clock LC
5 and output terminals 66 and 67 to the read counter 5. The input terminal 60 is a terminal for setting the head address and the number of dots of one line of image data in the I / O port 70. The output side of the I / O port 70 is connected to a buffer 71 and flip-flop circuits (FF) 72,7.
3 and is connected to. The output of the buffer 71 is directly connected to the output terminal 66, and the output of the flip-flop circuit 72 is connected to the adding circuit 77.

On the other hand, the output side of the flip-flop circuit 73 is connected to a LOAD clock output counter 81, and the output side of the LOAD clock output counter 81 is
It is connected to the AD signal generation circuit 82. This LOAD
The output of the signal generation circuit 82 is sent to the output terminal 67 and fed back to the LOAD clock output counter 81.

An input terminal 61 is a terminal for inputting a synthesizing / overlapping switching signal K indicating superimposition designation and composition designation. The synthesizing / overlapping switching signal K is inputted from this input terminal 61 to a NOT gate 74 and a buffer 75. It has become so.
A flip-flop circuit 76 is connected to the output side of the NOT gate 74.
The output of the buffer 75 is sent to an adder 77. Further, on the output side of the addition circuit 77,
The flip-flop circuit 78 is connected, and the output side of the flip-flop circuit 78 is connected to the flip-flop circuit 76 and the buffers 75 and 79. The output side of the buffer 79 is connected to the output terminal 66.

The input terminal 62 is a terminal for inputting the combining / overlapping ON / OFF signal G to the LOAD signal generation circuit 82, the NOT circuit 80, and the buffer 79. The output side of the NOT circuit 80 is connected to the buffer 71 and the flip-flop circuits 76 and 78. The input terminal 63 is a terminal for inputting a pulsed line set signal L0.
The flip-flop circuit 72 and the AND gate 83 are connected. The other input terminal of the AND gate 83 is
Connected to the output side of the AD signal generation circuit 82,
The output side of the D gate 83 is connected to a flip-flop circuit 76,
78.

The input terminal 64 is connected to the line set signal L
A terminal for inputting a line set signal L1 other than 0 to the flip-flop circuit 73 and the LOAD clock output counter 81. The input terminal 65 is connected to the read clock LC
Is input to the LOAD clock output counter 81 and the LOAD signal generation circuit 82.

Next, the operation of this embodiment will be described.
In addition, in order to facilitate understanding, one A2 size sheet is 909.
LPI image data D1 and 454L per A2 size
PI image data D2 and A2 size single 909LP
The case of sequentially receiving the image data D3 of I will be described. In this case, the image data D2 of 454 LPI and the image data D3 of 909 LPI are overwritten. Of course, the present invention is not limited to this, and the same processing as described below can be performed for other reception sizes and line densities. Here, “LPI” is a linear density, which is a unit of recording density per inch.

First, in FIG. 1, each image data D1,
Before transmitting D2 and D3 to the overlay processing circuit 2, a line signal S1 indicating the number of lines of each of the image data D1, D2 and D3 is input to the CPU 1 from the host device. Before the superimposition processing circuit 2 receives the non-overwritten 909 LPI image data D1, the superimposition signal C1 indicating the L level is output from the CP.
U1 is input to the overlay processing circuit 2.

As a result, the L-level superimposed signal C1 is obtained.
Are ANDed through the terminal 22 of the superposition processing circuit 2 shown in FIG.
Input to the circuit 20, and the input terminal 24 of the OR circuit 21
Become a level. As a result, the image data D1 is directly output to the output terminal 26 via the terminal 25 of the OR gate 21. At this time, the instruction signal C2 is input from the CPU 1 to the synthesizing / overlapping processing control unit 6, and the image data D1 is stored in the A block of the image memory 3.

Next, when the 454 LPI image data D2 to be overwritten is received by the overlay processing circuit 2, an overwriting instruction signal S4 indicating that the image data D2 is to be overwritten from the host device to the CPU 1. Is sent and C
A superimposition processing signal C1 indicating an L level is input from the PU1 to the superimposition processing circuit 2. As a result, the image data D2 is output from the overlay processing circuit 2 as it is. At this time, CPU
1 to the compositing / overlapping processing control unit 6, the image memory 3
An instruction signal C2G for instructing that the image data D2 be stored in the C block of the image memory 3 is sent.
Are stored in the C block.

Before the 909 LPI image data D 3 to be overwritten is received by the overlay processing circuit 2, an H level overlay processing signal C 1 is output from the CPU 1 to the overlay processing circuit 2, An instruction signal C3 for reading the image data D2 stored in the block is output from the CPU.
1 is output to the combining / overlapping processing control unit 6. As a result, the image data D2 from the image memory 3 input through the terminal 23 of the overlay processing circuit 2 shown in FIG. 3 is output from the AND circuit 20, and the OR gate 21 outputs the image data D2 and the 909 LPI from the host device. Is superimposed on the image data D3, and the overwritten image data D2 + D3 is output from the output terminal 26.

At this time, the instruction signal C3 for writing the overwritten image data D2 + D3 in the B block of the image memory 3 is set to C.
The output from the PU 1 to the synthesizing / overlapping processing control section 6 and the overwritten image data D2 + D3 are stored in the B block. More specifically, the image data D2 of 454 LPI corresponds to (a) of FIG.
Assuming that the image data D3 of 909 LPI is data as shown in FIG. 7B, as shown in FIG. 8A and FIG. The data D2 is read out twice in line units, and as shown in FIGS. 8B and 8E, each time the image data D2 is read out.
On the other hand, by superimposing the image data D3 on a line-by-line basis, the overwritten image data D2 + D3 as shown in FIGS. 8C and 8F is obtained.

Thereafter, as shown in FIG. 5, the A / B blocks of the image memory 3 are
The image data D1, D2 + D3 with the blocks are alternately read out line by line via the superimposition processing circuit 2, and the same lines of the A block and the B block of the image memory 3 are recorded on the same scan. A composite image of A1 size as shown is output.

Next, the control of the readout counter 5 by the synthesizing / overlapping processing control unit 6 during the superimposition processing of the superimposition processing circuit 2 and the control during the synthesizing processing will be described with reference to FIGS.
It will be described in detail based on. First, a normal memory storage operation will be described. Before performing the storing process, the head address of the block to be stored in the image memory 3 is set from the input terminal 60 of FIG. Next, upon receiving an OFF combined / overlapping ON / OFF signal G from the input terminal 62, the gate of the buffer 71 is turned ON and the I / O port 7
The head address of 0 is loaded into the read counter 5 via the buffer 71 and the output terminal 66. Thereafter, the image data D1, D2, and D3 are sent to the image memory 3, and the image data D1, D2, and D3 are stored in the image memory 3 from the designated start address.

Next, the case of the overlapping process will be described. By turning off the synthesizing / overlapping ON / OFF signal G from the input terminal 62, the gate of the buffer 71 is turned ON. Thereafter, the start address (N value in FIG. 9) of the block to be read in the image memory 3 is changed. By setting the I / O port 70, the head address is output to the output terminal 66. Then, by generating one read clock LC, the head address is set in the read counter 5 (T1 in FIG. 9). These operations are the same as the above-described normal memory storage operation.

Next, a pulse of the line set signal L0 is received from the input terminal 63, and the head address is set in the flip-flop circuit 72 (T2 in FIG. 9). At this time, the output of the flip-flop circuit 78 is cleared by the OFF combined / overlapping ON / OFF signal G from the input terminal 62 (FIG. 9).
, The leading address is output from the adding circuit 77 as it is. In this state, the input terminal 6
2, the gate of the buffer 71 is turned off, and the buffer 79 is turned on.
And clearing of the flip-flop circuit 78 is released. Thereafter, the linear density 494 received from the input terminal 60 is obtained.
The number of dots in one line of the LPI is set in the I / O port 70 (M value in FIG. 9).

Then, the pulse of the line set signal L 0 is received again from the input terminal 63, and the number of dots in one line is set in the flip-flop circuit 72, and the previously set head address is sent to the flip-flop circuit 78. Set (T3 in FIG. 9). As a result, since the gate of the buffer 79 is ON, the head address is output to the output terminal 66. Further, by two pulses of the line set signal L1 received from the input terminal 64,
The number of dots in one line is set in the flip-flop circuit 73 and the LOAD clock output counter 81 (T4 in FIG. 9). Thus, the pre-processing is completed.

Subsequently, a read clock LC is supplied from the input terminal 65 to the read counter 5 in order to read the image data D2 from the C block in which the 454 LPI image data D2 is stored. As a result, 45
Reading of the first line of the 4 LPI image data D2 is started (T5 in FIG. 9). At the same time, the LOAD clock output counter 81 also starts operating, and
The AD clock output counter 81 checks that the previously set 1
The number of dots in the line is repeatedly counted, and a count end signal E is sent to the LOAD signal generation circuit 82 each time the count is completed. The LOAD signal generation circuit 82 generates the LOAD clock L only when the number of times the count end signal E from the LOAD clock output counter 81 is received is odd.
Is output to the output terminal 67.

When the first count of the LOAD clock output counter 81 is completed (T6 in FIG. 9), the head address set in the flip-flop circuit 78 is loaded into the read counter 5 via the output terminal 66. As a result, the first line of the same 454 LPI image data D2 is read out again from the image memory 3, and as described above,
In the superimposition processing circuit 2, the first line of the 454 LPI image data D2 is replaced with the 909 LPI image data D3.
The overlapping process is performed on the line. In addition, the “start address” +
The “address for one line” is the flip-flop circuit 78
(T7 in FIG. 9).

Subsequently, the LOAD clock output counter 8
When the second counting of 1 is completed (T8 in FIG. 9), the “start address” + “the address for one line” set in the flip-flop circuit 78 is loaded into the read counter 5 via the output terminal 66. I do. As a result, the second line of the same 454 LPI image data D2 is read out again from the image memory
A superimposition process is performed on the fourth line of the 9 LPI image data D3. In addition, the “start address” + “the address for two lines” added by the adder 77 is set in the flip-flop circuit 78 by the LOAD clock L. As described above, the 454 LPI is controlled by the synthesis / overlapping control unit 6.
The line data of the image data D2 of
By reading out each time, the overlapping process as shown in FIG. 8 is realized.

Finally, the case of the combining process will be described. First, by turning off the synthesizing / overlapping ON / OFF signal G from the input terminal 62, the gate of the buffer 71 is turned ON.
After that, the head address (X value in FIG. 10) of the A block of the image memory 3 is set to the I / O port 70, and the head address value is output to the output terminal 66. Then, by generating one read clock LC, the head address is set in the read counter 5 (T in FIG. 10).
1).

Next, upon receiving the pulse of the line set signal L0 from the input terminal 63, the head address is set in the flip-flop circuit 72 (T2 in FIG. 10). At this time,
Since the output of the flip-flop circuit 78 is cleared (0 value in FIG. 10) by the OFF combined / overlapping ON / OFF signal G from the input terminal 62, the top address value is output from the adding circuit 77 as it is. Is done. In this state, the gate of the buffer 71 is turned off, the buffer 79 is turned on, and the flip-flop circuit 78 is received in response to the ON combined / overlapping ON / OFF signal G from the input terminal 62.
Release the clear. Thereafter, the start address of the B block of the image memory 3 (Y value in FIG. 10) is input from the input terminal 60.
And sets it in the I / O port 70. Then, upon receiving a pulse of the line set signal L0 from the input terminal 63,
The head address of the block is set in the flip-flop circuit 72, and the head address of the previously set A block is set in the flip-flop circuit 78 (T3 in FIG. 10).

Subsequently, the number of dots of one line of 909 LPI (Z value in FIG. 10) is received from the input terminal 60 and set to the I / O port 70. Then, the pulse of the line set signal L0 is received from the input terminal 63, the number of dots of one line of 909 LPI is set in the flip-flop circuit 72, and the head address of the previously set A block is set in the flip-flop circuit 76. The start address of the B block is set in the flip-flop circuit 78 (T4 in FIG. 10). Thereby, the buffer 79
Is turned on, the head address is output to the output terminal 66. Further, the number of dots in one line is determined by the two pulses of the line set signal L1 from the input terminal 64 by the flip-flop circuit 73 and the LOAD.
It is set to the clock output counter 81 (T in FIG. 10).
Five). This is the end of the preprocessing.

Subsequently, the image memory 3 is processed by the following processing.
The image data D1 and the image data D2 + D3 stored in the A block and the B block are recorded as an A1 size spread image. When the read clock LC is supplied from the input terminal 65 to the read counter 5, reading of the first line of the 909 LPI image data D1 from the head address of the A block is started (T6 in FIG. 10), and at the same time, the LO
The operation of the AD clock output counter 81 is also started.

Thereafter, the LOAD clock output counter 81 repeatedly counts the number of dots of one line set previously, and sends a count end signal E to the LOAD signal generation circuit 82 each time the count ends. The LOAD signal generation circuit 82 outputs the count end signal E from the LOAD clock output counter 81 to the output terminal 67 as a LOAD clock L as it is.

When the first count of the LOAD clock output counter 81 is completed (T7 in FIG. 10), the head address of the B block set in the flip-flop circuit 78 is loaded into the read counter 5 via the output terminal 66. . Further, the “start address” of the A block added by the adding circuit 77 by the LOAD clock L +
The “address for one line” is the flip-flop circuit 78
(T8 in FIG. 10).

Next, the LOAD clock output counter 8
When the second counting of 1 is completed (T9 in FIG. 10),
The “head address” of the A block set in the flip-flop circuit 78+ “the address for one line” is loaded into the read counter 5 via the output terminal 66. In addition, the “start address” of the B block added by the adder 77 and the “address for two lines” are set in the flip-flop circuit 78 by the LOAD clock L.

In this way, as shown in FIG. 5, the image data D1 and the image data D2 + D3 are read out in units of one line for each of the A block and the B block of the image memory 3. Further, by switching and processing one line data of each block within one image clock, it is possible to record and output a two-page spread image as shown in FIG. 6, that is, an image continuously synthesized in the main scanning direction. it can.

[0046]

As described above, according to the image processing apparatus of the present invention, there is an effect that the superimposing process and the synthesizing process of the image data can be simultaneously performed on one recorded image. Since the control of the superimposition processing and the synthesis processing can be performed simultaneously by one synthesis / superposition processing control unit, the structure can be simplified accordingly. Furthermore, since the control of the superimposition processing circuit and the image memory by the superimposition / superposition processing control unit is performed in a hardware manner, high-speed processing can be performed, and the synthesis processing in the main scanning direction can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a synthesis / overlapping processing control unit.

FIG. 3 is a block diagram illustrating an overlay processing circuit.

FIG. 4 is a schematic diagram showing a storage area of an image memory.

FIG. 5 is a time chart illustrating a state in which image data is read from each block of the image memory, and FIG.
5 shows a read line from the A block, and FIG. 5B shows a read line from the B block.

FIG. 6 is a schematic diagram illustrating a combined A1 size recorded image.

FIG. 7 is an image state diagram for explaining a superimposition process;
FIG. 7A shows image data of 454 LPI.
(B) shows image data of 909 LPI.

FIG. 8 is a time chart showing an overlap processing operation;
8A shows the image data of 454 LPI on the first line, FIG. 8B shows the image data of 909 LPI on the first line, and FIG. 8C shows the first line after the overlap processing. 8D shows image data of 454 LPI on the second line, FIG. 8E shows image data of 909 LPI on the second line, and FIG. The image data of the processed second line is shown.

9A and 9B are time charts showing an overlay processing operation under the control of a synthesis / overlay processing control unit. FIG. 9A shows a synthesis / overlay ON / OFF signal, and FIG. FIG. 9C shows the state of the O port, and FIG.
9 (d) shows the state of the flip-flop circuit 72, and FIG. 9 (e) shows the state of the flip-flop circuit 78.
9 (f) shows the LOAD clock, FIG. 9 (g) shows the line set signal L1, and FIG.
9 (h) shows the state of the flip-flop circuit 73, FIG. 9 (i) shows the state of the LOAD clock output counter, FIG. 9 (j) shows the read clock, and FIG. 9 (k) shows the LOAD Indicates a value.

10A and 10B are time charts showing a synthesizing processing operation under the control of the synthesizing / overlapping processing control unit. FIG. 10A shows a synthesizing / overlapping ON / OFF signal, and FIG.
10 (c) shows the line set signal L0, FIG. 10 (d) shows the state of the flip-flop circuit 72, and FIG. 10 (e) shows the state of the flip-flop circuit 78. FIG. 10F shows the state of the flip-flop circuit 76, and FIG.
10 (h) shows the line set signal L1, FIG. 10 (i) shows the state of the flip-flop circuit 73, and FIG. 10 (j) shows the state of the LOAD clock output counter. 10 (k) shows a read clock, and FIG. 10 (l) shows a LOAD value.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Overlap processing circuit 3 Image memory 4 Write counter 5 Read counter 6 Compositing / overlap processing control part D1, D3 Image data of 909 LPI Image data of D2 454 LPI

Claims (1)

(57) [Claims] An image memory for storing image data from a host device; an overlay processing circuit for overlaying the image data from the host device with the image data read from the image memory; A write counter for specifying an address for writing image data, a read counter for specifying an address for reading the image data from the image memory , and control of the superimposition processing and the synthesis processing with the same circuit configuration.
And superimposition processing and composition processing for one recorded image
Are performed simultaneously, and the image data to be combined is
A synthesizing / overlapping processing control unit that reads out alternately for each line;
An image processing apparatus comprising: a CPU for performing a superimposition processing control unit.