JP3130735B2 - Print processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a print processing apparatus, and more particularly, to a print processing apparatus having a function called a form overlay for synthesizing stored image data with image data sent from a host apparatus or the like every time. It relates to a processing device.

[0002]

2. Description of the Related Art Conventionally, this type of print processing apparatus is disclosed in Japanese Patent Application Laid-Open No. 62-250768 as an image synthesizing means when performing form overlay.

This conventional print processing apparatus (Japanese Patent Laid-Open No. 622-2 / 1987)
50768) will be described with reference to FIG.
A conventional print processing apparatus includes an image data input unit 61 for receiving a print image from a higher-level device (not shown), and an overlay memory 62 for recording image data stored in the apparatus.
And an output page memory 6 for generating an image to be printed
3, a printer section 64 for printing on paper using image data in the output page memory, and a CPU circuit 65 for controlling the entire apparatus. First, the CPU circuit 65 records the in-device stored image data (hereinafter, referred to as a form image) input from the image data input unit in the overlay memory 62.

[0004] Next, when performing image composition by form overlay, a form image is read from the overlay memory 62 and transferred to the output page memory 63. The print data input from the image data input unit 61 is developed into a dot image, and a logical OR is performed with the form image already transferred to the output page memory.
In step 3, a composite image of the form image and the image based on the print data is generated. Alternatively, an image is read from the overlay memory 62 and the page memory 63 at the same time, and an image composition is generated by an external circuit.

Next, the composite image data generated in the output page memory 63 is transferred to the printer unit and printed. When performing continuous printing, the above operation is repeated.

[0006]

The above-mentioned prior art has to construct two or more independent memory circuits such as an overlay memory and a page memory, and has a disadvantage that the cost increases due to an increase in the number of memory chips. .

[0007]

According to the present invention, there is provided a print processing apparatus comprising: an image data input unit for receiving print image data from a host device; storing a non-stored image of the print image data and storing a plurality of form images; One memory that performs
The non-stored image in the one memory and a selected format
Read out along with the be read out alternately and the non-image to every word
Replaces the unsaved image with the selected form image
An image combining unit that holds up the read synthesized and these logical OR combining one word form image synthesizing data by repeating the process for outputting the said selected and said non-stored image of, and pulling the composite image It has a print processing unit for printing image data on paper and a CPU circuit for controlling each unit.

[0008]

[0009]

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention. In FIG. 1, one embodiment of the present invention is a CPU circuit 10 for controlling the entire apparatus, a memory 20 used for the operation of the CPU circuit in addition to recording of image data, and drawing in separate areas in the memory 20. It includes an image synthesizing unit 40 that reads out a plurality of images that have been written, logically synthesizes the images, and creates image data, and a print processing unit 30 that prints the image after the image synthesis.

A circuit configuration in the image synthesizing section 40 according to one embodiment of the present invention includes a memory read circuit 41 for reading image data from the memory 20 and address counters A and B (4) indicating memory addresses read by the memory read circuit 41.
A register 44 for temporarily storing image data (data corresponding to the data bus width of the circuit, hereinafter referred to as image data for one word) read by the memory read circuit 30 in one memory access. And a synthesizing circuit 45 for logically synthesizing one word of image data temporarily stored in the register 44 and another one word of image data read by the memory reading circuit 41. The combination circuit 45 determines whether OR or A
It is a circuit that can select the logic of ND or EOR.

Next, the operation of one embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows an operation timing chart of the signals S100 to S110 in the circuit block (FIG. 1) in this embodiment, and FIG. 3 is a diagram for explaining the operation.

First, when a form image used for form overlay is sent from the host device to the printing device, the CP
The U circuit 10 stores the images 2 and n in FIG.
Is drawn in advance.

In the present embodiment, the image 2 is drawn at an address in the adding direction from the address 200 of the memory 20, and the image n is similarly set to the address 300 similarly.
In addition, since the image synthesis in the form overlay is generally performed by OR synthesis, the CPU circuit 10 is provided with a synthesis circuit 45.
, It is assumed that the logical sum has been set. Next, when print data to be combined with the previous form image (hereinafter, referred to as a non-stored image) is sent from the higher-level device, the CPU circuit 10 stores the data in the memory 20 as shown in image 1 of FIG. The form image is drawn in the addition direction from address 100 different from the address where the form image was drawn. In the present embodiment, as shown in FIG. 3, it is assumed that image 1 (non-stored image) and image 2 (form image) are logically OR-combined into an output composite image, and printing is performed by the print processing unit 30. Unstored processed image and form image are stored in memory 2
When the image is drawn in 0, the CPU circuit 10 starts image composite printing at the time of form overlay.

The operation will be described with reference to the timing chart of FIG. As described above, after drawing of the image 1 (non-stored image) and the image 2 (form image) in the memory 20 is completed, the CPU circuit 10 transmits the signal group S at timing a in FIG.
100, the address counter A
The start address (address 100) of the image 1 is set in (42). The address counter A inputs the set address from the signal group S102 to the memory read circuit 41.

Next, at a timing b, the start address (address 200) of the image 2 is similarly set in the address counter B (43). The address counter B inputs the set address from the signal group S104 to the memory read circuit 41.

Next, in processing 3 at timing c, the CPU circuit 1
0 instructs the print processing unit 30 to start printing.

Next, in process 4 at timing d, the CPU circuit 10 instructs the memory read circuit 41 to start memory read.

Next, the memory readout circuit 41 uses the address information 100 given from the address counter 1 (42) at timing e, and reads one word of image data (data) of the image 1 at address 100 from the memory 20. 100) is read out and output to the signal group S106.

Next, a signal S107 for the register 44 is generated at the timing f, and the data 100 of the signal group S106 output from the timing e is latched by the register 44. The register 44 outputs and stores the latched image data as a signal group S108.

Next, the memory read circuit 41 terminates the reading of the address 100, generates a signal S101 to the address counter A (42), and
The address of (42) is incremented by one.

Next, the memory reading circuit 41 uses the address information address 200 given from the address counter B (43) at the timing h, and uses the memory 20 to store one word of image data (image 2) of the image 2 at the address 200. The data 200) is read out and output to the signal group S106.
Then, the image data at the address 100 from the signal group S108 and the image data at the address 200 from the signal group S106 are input to the synthesizing circuit 45.
5, and are ORed and output to the signal group S109.

Next, the print processing unit 30 takes in the composite image of the signal group S109 at timing i, generates a signal S110, and notifies the memory readout circuit of the completion of the one-word image signal take-up.

Next, at timing j, the memory read circuit 4
1 terminates the reading of the address 200 and makes the signal S
103 is generated in the address counter B (43), and the address of the address counter B (43) is incremented by one.

Next, the memory read circuit 41 reads the data (data 101) of the image 1 at the address 101 from the memory 20 using the address information 10 given from the address counter A (42) at the timing k. Output to the signal group S106.

Next, a signal S107 for the register 44 is generated at the timing 1 and the data 101 of the signal group S106 output from the timing of k is latched by the register 44. The register 44 outputs and stores the latched image data as a signal group S108.

Next, the memory reading circuit 41 terminates the reading of the address 101 at the timing m, and outputs the signal S
101 is generated in the address counter A (42), and the address of the address counter A (42) is incremented by one.

Next, the memory reading circuit 41 reads the data (data 201) of the image 2 at the address 201 from the memory 20 using the address information 201 given from the address counter B (43 #) at timing n. Then, the image data at the address 101 from the signal group S108 and the image data at the address 201 from the signal group S106 are input to the synthesizing circuit 45. The signal is output to the synthesized signal group S109.
0 takes the composite image of the signal group S109 at the timing of p, generates a signal S110, and notifies the memory read circuit of the completion of the one-word image signal pickup. Next, at timing g, the memory read circuit 41
The reading of the address is completed, and a signal S103 is generated in the address counter B (43).
Is incremented by one.

Similarly, the image data is read from the memory 20 alternately by using the address counter A (42) and the address counter B (43), and the image data of the image 1 and the image 2 shown in FIG. I do.

In the embodiment of the present invention, by adding the number of address counters and registers, and sequentially reading out and synthesizing image data from the memory, it becomes possible to easily synthesize a plurality of images.

[0033]

As described above, according to the present invention, when performing a form overlay, a form image, which is a stored image, and a print image, which is a non-stored image, are stored in separate areas in one memory. At the time of reading at the time of printing, the reading circuit reads the image drawn in the separate area described above, synthesizes the image, transfers it to the print processing unit, and prints it, so that during continuous printing, only the print image is stored in the memory. Since it is only necessary to draw, there is no need to combine the form image and the print image (non-stored image) on the memory each time, so high-speed form overlay printing is possible, as well as dedicated to form images as seen in the prior art. This eliminates the need to configure the memory.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram for explaining a form overlay operation according to one embodiment of the present invention.

FIG. 4 is a circuit block diagram illustrating a conventional print processing apparatus.

[Explanation of symbols]

 Reference Signs List 10 CPU circuit 20 Memory 30 Print processing unit 40 Image synthesis unit 41 Memory readout circuit 42 Address counter 1 43 Address counter 2 44 Register 45 Synthesis circuit 50 Image data input unit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Sato 3-49-1, Kamiishihara, Chofu-shi, Tokyo NEC Data Equipment Co., Ltd. (56) References JP-A-58-128879 (JP, A) JP-A-60-141573 (JP, A) JP-A-55-135978 (JP, A) JP-A-57-109684 (JP, A) JP-A-58-112770 (JP, A)

Claims (1)

(57) [Claims] And 1. A image data input for receiving the print image data from a host device, a non-conservative among the print image data
Is selected and one memory which performs a storage memory and a plurality of form image of the image, and the non-stored image of the in one memory
And the list read out a form image that has been alternately every 1 word
The previously read unsaved image is stored in the next selected file.
OR image synthesis while maintaining until image data is read
Image combining unit and print processing unit that performs image data printed on the sheet and pull the composite image and repeats the processing of outputting the combined data of 1 word synthesizes the form image, which is the selected and the non-stored image And the CP that controls each part
A print processing device comprising a U circuit.