JPH0113570B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device in a system combining a plurality of processors and memories.

In recent years, so-called multiprocessor systems, in which multiple processors share memory and perform work, have become popular. Such systems need to exchange data with each other, and in order to efficiently exchange data, memory-coupled multiprocessor systems that allow direct access to each other's memories are often used. In a memory-coupled multiprocessor system, when each processor accesses the shared memory area or the local memory of other processors each time, the traffic on the coupling path increases, lengthening the access time and reducing system performance. This will result in To avoid this, it is common practice to provide a dedicated local memory for each processor and store frequently used data in the local memory. However, in such cases, when data processed by one processor is to be passed to another processor group, a method has been used in which each processor in the processor group accesses its local memory and retrieves the data. However, this method has the disadvantage that accesses to local memory are concentrated, reducing system performance.

It is an object of the present invention to provide a system in which multiple processors and memories are connected via a common bus or the like, and each processor accesses the memory in common using its own address. An object of the present invention is to provide a transfer device that can efficiently transfer data from a memory area to a plurality of memory areas to be input as separate received data of a plurality of processors.

According to the present invention, a plurality of reception address counter groups that accept reception requests coming from a plurality of processors and store reception addresses, and a transmission address counter and a size counter that accept one transmission request and store the transmission address and transmission size are used. By providing a control circuit that repeatedly reads data from the memory pointed to by the sending address counter, and then writes data to all memories pointed to by the receiving address counter group, the number of times indicated by the size counter. As a result, a transfer device is realized that can perform transfer between memories with the number of memory accesses (1+number of reception requests)×range size.

The present invention will be explained in detail below using examples. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a reception reception device, 2 is a reception address counter group, 3 is a transmission reception device, 4 is a transmission address counter, 5 is a size counter, and 6 is a reception reception device. It is a control circuit. 10 is a bus connecting the processor and memory. The reception receiving device 1 detects a reception request from the bus 10, inputs the reception address, and inputs the reception address 101 to the reception address counter group 2.
send. Reception address counter group 2 inputs reception address 101, stores it in one of the corresponding address counter groups, and outputs reception address output to 104. The transmission reception device 3 detects the transmission request from the bus 10 and sends the transmission address 102 and transmission size 103.
Take out. The transmission address counter 4 inputs and stores the transmission address 102 and outputs a transmission address output 105. The size counter 5 inputs and stores the transmission size 103, and outputs a termination output 107 when the transmission size reaches a specific termination state. Control circuit 6
When inputting the transmission address output 105, it outputs the reception prohibition 106 to the reception reception device 1 and the transmission reception device 3. Control circuit 6 then performs a read memory access 108 to bus 10 from the memory location indicated by transmit address output 105. Next, the control circuit 6 performs memory access 108 for writing to all memory locations indicated by the received address output 104 to the bus 10. When the control circuit 6 finishes all writing, it issues an update command 109, and the sending address counter 4 , reception address counter group 2, and size counter 5 are updated. Repeat the read and write sequence from the updated memory location. If size counter 5 outputs end output 107 at this time,
The reception prohibition 106 is canceled and the next transmission request can be accepted.

FIG. 2 is a block diagram showing an example of the configuration of the reception/acceptance device 1 used in the transfer device of the present invention.
21 is a response circuit, and 22 is a data buffer.
The response circuit 21 inputs the address 210 of the bus 10 and the access request 212, detects that the address 210 is in the transmission request state when the access request 212 is issued, and approves when the reception prohibition 106 is not issued. A signal 213 is returned, and a disapproval signal 214 is returned when the signal 213 is issued. The response circuit 21 issues an enable signal 215 at the same time as it issues an approval signal 213.
issue. The data buffer 22 inputs the data 211 on the bus 10 and outputs the received address signal 101 when it receives the enable signal 215.

FIG. 3 is a block diagram showing an example of the structure of the received address counter group 2 used in the transfer device of the present invention, where 31 is an address distributor and 32 is a counter group. When the address distributor 31 receives the received address output 101, it sends a set designation 301 to the corresponding counter of the counter group 32. The corresponding register of the counter group 32 stores the contents of the received address output 101 according to the set command 301, and
Upon receiving the update command 109, the value of each counter is changed by a predetermined value. The output of each register in counter group 32 forms a receive address output 104.

FIG. 4 is a block diagram showing an example of the configuration of the reception/acceptance device 3 used in the transfer device of the present invention.
41 is a response circuit, and 42 and 43 are data buffers. The response circuit 41 receives the address 210 of the bus 10.
and access request 212, and access request 2.
12 is output, it detects whether the address 210 is a transmission request address output or a transmission range output,
If reception prohibition 106 is issued, non-approval signal 2
Returns 14. When the reception prohibition 106 is not output, either the enable signal 401 or 402 is output depending on whether the transmission request address is the transmission range output. The data buffer 42 receives the enable signal 4
When it receives 01, it inputs the data 211 on the bus 10 and outputs the transmission address output 102. Upon receiving the enable signal 402, the data buffer 43 inputs the data 211 and outputs the transmission size 103.

FIG. 5 is a block diagram showing an example of the configuration of the transmission address counter 4 used in the transfer device of the present invention. A counter 51 stores a transmission address by a transmission address output 102, and changes it by a predetermined value every time an update command 109 is received. The output of the counter 51 is output as a transmission address output 105.

FIG. 6 is a block diagram showing an example of the structure of the size counter 5 used in the transfer device of the present invention, where 61 is a counter and 32 is a comparator. When the counter 31 receives the transmission range output 103, it stores it and changes it by a predetermined value according to the update command 109. The comparator 62 inputs the output 601 of the counter 61, checks whether the output 601 is a predetermined value, and outputs a termination output 107 if they match.

FIG. 7 is a block diagram showing an example of the configuration of the control circuit 6 used in the transfer device of the present invention.
1 is an address selector, 72 is a sequential circuit, and 73 is a data transceiver. When the sequential circuit 72 inputs the transmission address output 105, the reception is prohibited 1.
06, outputs a transmission address selection output to the selection output line 701 to the address selector 71, outputs the transmission address to the address 210, and outputs the access request 2.
12 and performs read access, authorization signal 2
13, a set command 702 is issued to the data transceiver 73 to store the data on the data line 211. Next, the sequential circuit 72 selects the selection output line 701
, outputs a selection output of one of the reception addresses, outputs one reception address to the address 210, issues an access request 212 and performs a write access,
At the same time, an enable command 703 is issued to the data transceiver 73 to cause the data line 211 to output the previously stored data. Upon receiving the approval signal 213, the sequential circuit 72 releases the access request 212. After performing this write operation on all receiving addresses 104, the sequential circuit 72 issues an update command 109.
The updated transmission address output 105 and reception address output 104 are read and written in accordance with the above-described procedure. In this case, size counter 5
If the end output 107 is input, reception is prohibited 10
6 and complete the series of operations.

As described above in detail below, the present invention is applicable to a system in which a plurality of processors and memories are connected by a common bus or the like and each of the plurality of processors accesses the memory in common using its own address. A transfer device that transfers data from a memory area that contains transmission data of a processor to each memory area that should contain reception data of a part of the plurality of processors, and that receives reception requests coming from a plurality of processors. A reception reception device that accepts a reception request, a reception address counter group that stores reception addresses associated with a plurality of reception requests accepted by the reception reception device, a transmission reception device that accepts one transmission request, and a reception address counter group that stores reception addresses associated with a plurality of reception requests accepted by the reception reception device; When the sending address counter and size counter that store the accompanying sending address and sending size, and the sending receiving device accept a sending request, the receiving receiving device and the sending receiving device are prohibited from accepting the sending request, and the data is stored from the memory location indicated by the sending address counter. Read and write to all memory locations indicated by the reception address counter group, update the transmission address counter, reception address counter group, and size counter, read and write operations until the size counter reaches a predetermined value. The present invention provides a transfer device that is configured of a control circuit that repeats the above steps, and is capable of efficiently transferring data between memory areas dedicated to each of a plurality of processors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the transfer device of the present invention. FIG. 2 shows an example of the configuration of the reception reception device 1 used in the present invention, FIG. 3 shows the reception address counter group 2, FIG. 4 shows the transmission reception device 3, FIG. 5 shows the transmission address counter 4, and FIG. 6 shows the size. FIG. 7 is a block diagram showing one configuration example of each of the counter 5 and the control circuit 6. In FIG. In the figure, 1 is a reception reception device, 2 is a reception address counter group, 3 is a transmission reception device, 4 is a transmission address counter, 5 is a size counter, 6 is a control circuit, 21, 41 are response circuits, 22, 42, 43 is a data buffer, 31 is an address distributor, 32 is a counter group, 51 and 61 are counters, 62 is a comparator, 71 is an address selector, 72 is a sequential circuit,
73 is a data transceiver.

Claims (1)

[Claims] 1. In a memory sharing system in which a plurality of processors each use their own memory addresses but share memory via one or more common buses, one of the processors A transfer device that sends a data group that it owns to a memory area specified by a unique memory address of each of a group of processors that desire the data group among the plurality of processors, the transfer device comprising: reception receiving means for accepting a plurality of data reception requests coming from the processor of the data reception side; and a plurality of reception addresses indicating the starting position of each unique reception area of the memory of the reception side that comes along with the plurality of reception requests. a group of reception address counters to hold, a reception reception means that receives a transmission request coming from one sending processor, and a starting position of the transmission area of the memory of the sending side and the number of data to be sent accompanying the transmission request. a sending address counter and a size counter respectively holding a sending address and a sending size indicated by the sending address counter; and when the sending accepting means receives a sending request, reading from the sending side position of the memory indicated by the sending address counter, and reading from the sending side position of the memory indicated by the sending address counter, a control circuit that writes to all memory locations on the receiving side indicated by a group and repeats an operation of updating the sending address counter, the receiving address counter group, and the size counter until the size counter reaches a predetermined value; What is claimed is: 1. A transfer device that enables data transfer between a plurality of processors using different address spaces.