SU600926A1 - Data recording device - Google Patents

Description

drayen to the inputs of the corresponding elements NOT.

The drawing shows a block diagram of the device.

The device contains an address decoder 1, a NOT item 2 entries, a NOT item 3 write directions, a NOT item 4 for buffer memory, a query word analysis block 5, a main memory access block b, a buffer memory access block 7, an address bus 8, recording signal bus 9, recording direction signal bus 10, buffer memory occupancy signal bus -11, tracking signal bus 12, recording mode signal bus 13, fault signal bus 14, array end signal bus 15 and buses 16, 17 and 18 controls.

Does the device for recording information as follows

The subscriber exchanges an array of data that is located in adjacent memory cells at consecutive addresses. The low bits of this address determine the location number in the subscriber's buffer memory. Therefore, by successive transmission of information words on lower-order bits of this address, it is possible to determine whether the buffer group is full for a given subscription or not.

Suppose that information is recorded in the main memory in order of increasing addresses. The received request word from the subscription enters the device for recording information: address bits are on bus 8, the sign of record is on bus 9, the direction of recording is on bus 10, and the signal on this bus corresponds to the recording mode in the opposite direction.

Suppose that the subscriber starts recording the information word at the address in the lower order of which the code is 00. The signal from the output of the decoder 1 of the address corresponding to this code is fed to the input of the query word analysis block 5. Since the write mode is set in the forward direction, the signal on bus 10 is not available, and the output of the query word analysis block produces a signal that, when followed by bus 12, sets a sign that the buffer memory is being accessed for accumulation of information. The buffer memory access unit 7 generates a write signal to the buffer memory on bus 17. At this point, the processing of the query word is uploaded. This mode of accumulation of query words from the subscriber continues for as long as the query word does not arrive, at lower bits of which code is 1. In this case, the output of the cipher I address corresponds to the AND combination, generates a signal on the inputs of the query word analysis block 5, in which the formation of the ocifoBHofl is formed

memory If there is tracking on bus 12 |, the main memory access block sets a request to the main memory on bus 16. After this, the device can proceed to processing the next query word.

The subscriber can record an array of information and in descending order of addresses. In this mode, the operation of the device is ganalotichnogo described, only the access to the main memory occurs when the code in the lower bits of the address 00.

Access to the main memory during recording is formed with codes in the lower bits of the address 00 or II. The exchange of the transmitted array can be completed with an address whose code differs from the indicated ones in the lower bits. Therefore, during the last exchange, a sign of the end of MaccHBia is transmitted from the subscriber.

If there is an end of the array in the recording mode in block 5. Of analyzing the query words, an appeal to the main memory is formed. The array end signal is fed to the query word analysis block via bus 15. Further processing of the query word is similar to the described case of accessing the main memory.

Consider the operation of the device in the read mode from the main memory.

The absence of the sign of writing on the bus 9 corresponds to the reading mode. In this mode, it suffices to analyze the buffer memory for the corresponding subscriber. The occupancy signals enter the device via the P bus. At the output of the buffer storage access block 7 on bus 18, a read signal from the buffer memory appears. If the requested information is not in the buffer memory, in this case, the query word analysis block 5 generates a main memory access signal,

On bus 16, a request to the main memory is established. This completes the processing of the query word and the device is ready to process the newly received query word from the other subscriber. - Consider the operation of the device for the mode, if the subscriber detected a failure. A signal of failure enters the device via bus 14. In this case, the subscriber stops the exchange of information with the main memory. If accumulated information words were stored in the recording mode and in the buffer memory prior to detecting failures, they should be rewritten into the main memory. In a bad situation, the subscriber does not issue a query word. The address at which it is necessary to rewrite the information in the main memory is stored in the buffer memory. In the execution of this mode, the query word read previously written by this subscriber is read from the buffer memory on bus 8.

If prior to the failure, the work was done in recording mode, then bus 13c (block 5 ana, requesting words) receives a recording mode signal. When accumulated information is available, bus buffer idlers are sent to the device 11 bus. failure mode in the presence of the recording mode and buffer memory being occupied by the device For recording information, it forms the main memory. The accumulated information in the buffer memory is rewritten into the main memory, after which the device is ready for processing the newly received query va.

Thus, the device for recording information allows to increase the speed by processing the query words before writing them to the buffer memory, as well as by speeding up the process of forming the request to the main memory.

Claims (2)

1. US patent number 3699530, class. 340-172.5, 1974. 2. Girshberg V. V. and others. Typical nodes on semiconductor logic and functional elements of the ET series. M., Ld, “Energie, 1966, p. 28, p. 1 a.