SU980097A1 - Device for control of scratchpad buffer storage of multiprocessor electronic computer - Google Patents

Description

The invention relates to computing and can be used to manage the super-efficient buffer memory (SBP) of high-performance computers. A device is known which contains a buffer memory, a processor address register, an address comparison block, a row address switch, a register of recorded information, a read information register, a column address switch, an address matrix of a priority block l. This device does not have high enough performance due to the applied algorithm for servicing requests to the memory of processors and I / O channels (each recording requires access to the main memory); In addition, the combined operation of the address translation block and the address matrix with the super-efficient buffer memory is not ensured, which increases the access time to the SBP. The implemented algorithm for replacing information blocks does not allow increasing the computer performance by using higher capacity SBPs. The closest to the present invention is a device containing a buffer memory block, an address matrix, a priority block, read and write information registers, and memory protection code 2 registers. The specified device has a slightly higher performance rate since the I / O request service does not affect the time processing requests of the processors, but retains the disadvantages of the above-described device. The aim of the invention is to increase speed. The goal is achieved by the fact that the device for managing a super-operational buffer memory of a multiprocessor computer, which contains an address selector, a marker selector and an input information selector, whose control inputs are combined and connected to the output of the priority block, the output of which is the priority output of the device, the first inputs the selectors are channel address, channel marker and channel information inputs of the device, respectively, the first input of the priority block is a channel input of The device's request, the outputs of the marker selector and the input information selector are connected respectively to the inputs of the register of markers and the register of input information, the outputs of which are connected to the output of the markers and the output of the recorded information of the device, respectively, as well as the input of the markers and data of the super-fast buffer memory which is connected to the output of the write enable trigger, the input of which is connected to the output of the second element OR, the first input of which is connected to the output of the first element AND the first input of the latter is connected to the output of the first OR element, whose inputs are connected to the inputs of the encoder, the output of which is connected to the first input of the row number selector, the output of which is connected to the input of the row number register, the output of which is connected to the input of the row number of the super-fast buffer memory block and the input of the row number of the address matrix, the input of the new address of which is connected to the output of the address page address register address address matrix, which is the output of the device page address, and the input address register mat address network is connected to the output of the address selector; the address of the copy address is connected to the output of the copy counter; the selector of the read information, the output of which is connected to the input of the read information register, and the output of the latter is the output of the read information of the device, and the register of memory protection codes; memory protection codes selector, address matrix identifier register, two decoders, long operations trigger, long operations counter, memory protection codes matrix, word counter, block substitution, column address register, buffer memory identifier register, correction unit, multiplexer, addresses, analysis unit, address multiplexer, analysis unit, read information multiplexer, new data recording control unit, change bit matrix, change bit multiplexer, second AND element, the operation end trigger, the third and fourth elements OR, the processor number register, the output of which is the output of the device's processor number, and the input is connected to the first output of the identifier register of the buffer memory The second output of which is connected to the input of the second decoder, the first output of which is connected to the first input of the fourth OR element, the second input of which is connected to the output of the recording resolution trigger, and the output to the recording resolution input of the change bit matrix, the address input of which is connected to the address inputs the correction block, the matrix of protection codes, the replacement block, the column address register and the address output of the address matrix of the address matrix of the address matrix, which is the corresponding output of the device, and the output

0 address of the address register of the address matrix of addresses, which is the output of the address of the word device, is connected to the input of the word counter, the output of which is connected to the control input

5 column address register, output-. The latter is connected to the address input of the superoperative buffer memory block, the input of the line number of which is connected to the inputs of the row number of the matrix of protection codes, matrix of change bits, replacement unit and with address inputs of the address multiplexer, bit multiplexer, change, multiplexer of the read information, input

5 data of which is connected to the output of the read information, the block of the super-operational buffer memory, and output, the course - to the first data input of the selector of the read information, the control input of which is connected to the input of the rewriting operation of the recording control block of the new data which is connected to the input of the data of the matrix of bi5 change, the output. which is connected to the data input of the change bit multiplexer, the output of which is connected to the input of the change bit of the replaced data of the control unit for recording the new data, the output of the recording of the address of which is connected. with inputs for resolving a write of a correction block, a matrix of protection codes, an address matrix, the output of which is connected to the input of the read addresses of the analysis block, an input of stored data of the correction block, an input of the address multiplexer whose output is the output of the address of the device data page being replaced and connected with the input of the replaced data of the correction block whose error input is connected to the error output of the address register of the address matrix identifiers, and the output to the input of the corrected address of the address selector, the second inputs of The address markers of the markers and the input information are respectively the address input, the input of the markers and the information input of the connection with the device's processors, the group of inputs of the address selector, the selector of the markers and the input information of the device processors, the group of inputs of the processor markers device and a group of information inputs of the device's processors, the third input of the address selector is connected to the first output of the long operation counter, the input of which is connected to the The first input of the trigger for long operations and with the first output of the first decoder, the second output of which is connected to the input of the copy counter, and the input is connected to the output of the operation code of the register of identifiers of the address matrix, the output of the identifiers of which is the corresponding output of the device the buffer memory, and the input is connected to the output of the identifier selector; the group of inputs of the identifier selector is a group of inputs of the identifiers of the device processors; the first input is The lecturer is a channel input identifier of the set. The second input of the selector is the input of communication with the device's processors, the control input of the selector identifier is connected to the output of the priority block and the control input of the protection code selector, the group of inputs of the priority block and its first, second and third inputs 7 are respectively, a group of device processor request inputs, a device service unit request input, a channel request input and a communication request with device processors, a control input of the priority block connected to the trigger output of x operations and with the input of the duration of the long operations of the recording control unit of new data whose overflow input is connected to the transfer output of the long operations counter and the reset input of the long operations trigger, the input of the fourth clock of the write control unit is connected to the second output of the long operations counter, the write operation input is with the second output of the second decoder and with the second input of the first element AND, the output of recording new data with the second input of the second element OR, and the output of the end of the operation with the first input of the third element This ISH, the second input of which is connected to the output of the second element I, and the output to the installation input of the end of operation trigger, the output of which is the output of the operation end of the device and connected to the write enable input of the replacement block whose output is connected to the second input of the row number selector. the third input is connected to the third output of the long operation counter and the control input is connected to the third output of the second decoder, the fourth output of which is connected to the input of the rewriting operation of the write control unit, the second RAM input of the read data selector is connected to the input of the super-operative buffer memory block , the group of inputs of the selector code of the code is the group of inputs of the protection codes of the device’s processors, the input of the selector of the protection codes is the channel input of the protection codes of the device, the output of the villages The ip-op and protection codes are connected by the input of the register of protection codes, the output of which is connected to the input of the protection code of the new data of the matrix of protection codes and the input of the protection code of the query of the analysis block whose input of the read protection codes of which is connected to the output of the matrix of protection codes, the input of the request address The new address of the address matrix and the correction block; the input of the read operation — with the third output of the first decoder; the output error of the address is the output of the device, and the comparison outputs are connected to the inputs of the first OR element, whose output is output The availability of the device information is connected to the first inputs of the first and BTOpqro elements I, the second input of the second element I is connected to the third output of the register of identifiers of the buffer memory.  The analysis block contains the first group of m (m is an integer) of the And elements, the second and first inputs of which are connected respectively to the outputs of the convolution blocks modulo two protection codes and the outputs of the m comparison codes of the protection codes, the first inputs of which are combined and the input of the block request security code, a. second entrances. connected to the inputs of the convolution blocks modulo two security codes and are the input of the read security codes of the block, the second group of m elements AND whose outputs are the output of the block comparison, the first and second inputs are connected to the outputs of the m convolution blocks modulo two addresses and with outputs of m address comparison circuits, the first inputs of which are connected to the inputs of convolution blocks modulo two addresses and are the input of the read address block addresses, and the second inputs are combined and are the input address of the block request, m elements OR, outputs The first inputs are connected to the outputs of the AND elements of the first group, and the second inputs are combined and are the input of the read operation of the block, the And element, m inputs of which are connected to the corresponding first inputs of the AND elements of the second group and the output is the 9th input of the NOT element, the output of which is the output of the block address error.  In addition, the control unit for recording new data contains three elements NOT, four triggers, two elements.  OR, four elements AND, the input of the fourth cycle of the block is connected to the installation input of the first trigger and the first input of the first element AND, the second input of which is connected to the output of the first trigger and the input of the third element NOT, the information input of the first trigger connected to the input of the first the element NOT and the input bit of the change of the block 78 words being replaced, the output of the first element is NOT connected to the first input of the fourth element AND, the second input of which is connected to the input of the block rewriting operation and the information input of the second trigger , the installation input of which is connected to the installation i / i input of the third trigger and the output of the second element NOT, whose input is the input of the length of the long block operation, the information input of the third trigger is the input of the block write operation, and the output of the change bit of the active block, the block overflow input is connected to the first input of the second element AND, the second input of which is connected to the third input of the first element AND and the first input of the third element AND and the output of the second trigger, the output of the third element NOT Connected to the third and second inputs of the second and third elements AND, respectively, the output of the third element AND is the output of the recording block, the output of the first element AND is connected to the first inputs of the first and second elements OR, the output of the second element AND is connected to the second input of the first element OR, the output which is connected to the input of the fourth three | - hera, the output of which is the output of writing the address of the block, the output of the fourth element.  And it is connected to the second input of the second OR element, the output of which is the output of the end of the bgyuk operation.  One of the factors determining the speed of a computer is the algorithm for servicing the requests of processors and I / O channels to two-level main memory.  The invention uses the algorithm Fully asynchronous conditional deception.  In this case, the Write operation when data is available in the SBP is performed only in the SBP, and in the absence of data, one OP cycle is required.  As a result, the average write time is significantly reduced.  The structure of the SBP organization and its management, in addition, allow the read cycle of the SBP itself to be combined with an associative search in the address matrix. This reduces the service time of requests in the SBP. In the proposed device, the technical solution (G) is used as a replacement unit.  In order to ensure high reliability, the device includes an error correction block C in the address matrix. Structural solutions of the proposed device can be used to serve requests for two-level RAM of processors and input-output channels included in the multiprocessor system with minimal delays due to conflicts. .  The device can be used to manage super-fast buffer memory, memory in the mule of a type-processor system with shared resources (the SBP serves the requests of all processors) and in the system where the SBP is integrated with its processors.  .  The device can service requests of the processors to the memory for reading or writing information with tempo: each clock-one request if there is information in the SBP, and if there is no information in the SBP, it is necessary to rewrite the block of information from the PD to the SBP so that subsequent processor calls to this block of information was serviced at the SB level. One request for reading or writing information in the SBP is serviced per two clocks: an address matrix clock (MA and an ultra-fast clock). the buffer memory (in the matrix of addresses the addresses of those blocks of information from the OD that are in the SBP are stored), while the combined mode of operation of the MA and the SBP is organized by two consecutive requests, t. e.  when servicing a single query in tact.  The CBP for the next request is executed; the MD cycle is executed. FIG. 1 is a block diagram of a device for managing a super-operational computer buffer memory; FIG. 2 is a block diagram of a super-operative buffer block; FIG. 3 is a block diagram of the analysis block; in FIG., t — structures on the replacement block circuit; in FIG. 5 block diagram of the correction unit; in fig.  6 is a block diagram of a control unit for recording new data in FIG.  7 flowchart Fully asynchronous conditional volume.  Device for managing super-operative buffer memory of multi 9710 processor computer contains priority block 1, identifier selector 2 ::, address selector 3, security code selector, marker selector 5, input information selector 6, address matrix identifier register 7, address matrix address register 8 , memory protection register 9, register of 10 markers, register 11, input information, first decoder 12, copy counter 13, word counter k}, trigger 15 long operations, counter 16 long operations, matrix of 17 addresses, matrix 18 protection codes memories, replacement block 19, column address register 20, SBP block 21 ,. buffer memory identifier register 22, correction unit 23, addressing multiplexer 2C, analysis block 25, read information multiplexer 26, second decoder 27, control block 28.  writing new data, first element OR 29 encoder 30, read information selector 31 32bit change matrix, 33bit change multiplexer, read information register 3, second And 35 element, first And 36 element, row number selector 37, third IS 38, fourth element OR 39, second element OR 0, line number register, register 2 processor numbers, operation end trigger 3, write enable trigger, device processor channel request inputs, device communication with the processors and device service unit input, inputs 9-51 iden the device processors' fixtures and channels and the communication input with processors, the inputs 52-5 of the device's processor addresses, the channels and the communication input with the processors, the inputs 55 and 56 of the memory protection codes of the device processors and the inputs of the device processors tokens, the channel and communication input processors, inputs 60-62 device processor information ,. channel and communication input with processors, output 63 priorities, output 6 identifiers, output 65 of the address of the word, output 66 of the recorded information, output 67 of the column address, output 68 of the address of the page, output 69 of the markers, output 70 of the processor number, output 71 of the end of the operation, output 72 availability of information, output 73 address errors, output 7 addresses of the replaced block page, output 75 of read information, 76 marker outputs, data inputs 77, address input 78, line number input 79, record resolution input 80, outputs 81 m lines, 82 inputs read addresses, input 83 request addresses, input 8 Protection request code, inputs 85 read protection codes read input 86, outputs 87 comparisons, address input 88, input 89 line numbers, input 90 write resolution, output 91 numbers of the replaced string, inputs 92 of stored data, input 93 of the new address, input 9 address errors, address input 95, write resolution enable 9b, output of the corrected address 97, input of replaced data, fourth cycle input 99, length of operation 100 input 100, overwriting operation input 101, write operation input 102, operation end output 103, block recording output 104 105 bit input replacement of the block being replaced, output 106 of the change of the active block, output of the address record 107, overflow input 108, memory subunits 109, decoder 110, m modulo convolution blocks 111 two addresses, m comparison schemes 112 comparing addresses of protection codes 113 of convolution blocks 114 modulo two security codes, the first group of m elements AND 115, m elements OR 116, the second group of m elements AND 117, the t-input element AND 118, the element NO 119, the replacement selector 120, the replacement address register 121, the encoder 122, register 123 chronology recording, chronology memory block 124, chronology selector 125 chronology reading register 126, decoder 127, chronology address register 128, address selector 129, comparison scheme 130, first addition unit 131, switch 132, shifter 133, second addition unit 134, vertical parity register 135, first convolution unit 136, correction register 137, first element NOT 138, vertical parity memory unit 139, second convolution unit l40, first comparison circuit l4l, second HE 142, third NOT 143, second comparison 144, fourth HE 1445, And 146 , output of 147 correction errors, HL 148 elements, 149, block deletion trigger 150, rewriting trigger 151, trigger 9712 ger 152 change bits, NOT element 153, AND 15 / t-157 elements, OR elements 158, 159, trigger 1bO of address recording, The device operates as follows.  Perform the operation of reading a double word (data in the SBP is available).  In block 1, the priorities are analyzed for existing requests, one of the requests is assigned a priority in accordance with the following discipline: the first priority is the service unit, the second is the communication adapter with processors, the third is the buffer section of channels, the fourth is processors.  In accordance with the assigned priority, in the receiving selectors 2 identifiers, 3 addresses, 4 security codes 5, markers, 6 input information, the direction for opens.  receiving all the information about the request from this tool to the registers 7 identifiers, 8 addresses, 9 memory protection, 10 markers, 11 input information, and the corresponding device is given a priority assignment signal.  At the address of the column from the register 8, the address matrix of the address matrix reads the matrix of 17 addresses and the replacement block 19, parallel to the column address is written to the register 20 of the column address, which also receives the double word number in the SPB data block from the 14 word counter.  In block 25, the analysis of the addresses read from MA 17 is compared in bitwise comparison schemes i12 with the request address from register 8 and monitored at convolution blocks 111.  If there is an error in the read addresses, then an output error message appears at the output 73 of the analysis block 25.  If there is no error and the output of the read double word comes from the output of the first decoder 12, then in this mode (data is in the SBP), one of the outputs 87 of the analysis unit 25 appears. A comparison of the addresses of this rack of the 17 address and the Request appears. which is encoded on the encoder 30 to the number of the compared line and, through the selector 37, is written to the register 41 of the line number.  An information availability signal is generated on the OR element 29, which is output to the buffer section of the channels, if its request is serviced, or used to generate an operation end signal, if a request from one of the processors is serviced.  Simultaneously with the operation of the analysis block 25 and the generation of the number of the compared line from the memory blocks 109 of the SBP block 21 in accordance with the address of the register of the column address 20, the double words of all the rows of the column that are received at the data input of the multiplexer 26 of the read information are counted to the address the entrance of which at the same moment arrives. The number of the line compared to the register of the line number.  From the output of multiplexer 26, the data enters through the data input of the buffer memory of the selector 31 of the read information Not register 3 of the read information for issuing to the interrogator.  Thus, the reading cycle of the actual memory blocks 109 is combined with an associative search for the request address and the formation of the number of the matching line.  After the read cycle of the address matrix 17, the request identifier is copied from the register of 7 identifiers of the address matrix to the register 2 of the buffer memory identifiers to terminate the service, and a new request is received to the MA level aetc in accordance with the operation of the priority block 1.  At the same time with .  issuing the read information to the processor number register k2, the processor number is recorded from the register of 22 identifiers, the request of which is serviced, which is accompanied by an operation end signal, which is generated on the AND 35, OR 38, and end of operation trigger 3.  The end of operation signal is also used to change the current value of the replacement unit 19 chronology. Performing the write operation of the data double word in the SBP (the data availability mode in the SBP is considered) has the following differences from the device operation mode described above. comparisons are used in addition to the comparison and control of addresses, the comparison of the read protection codes from the matrix 18 of the protection codes with the security code of the request from register 9 of the protection code and KOH Troll of the read protection codes (elements 113, AND and 115 blocks 25 and analysis).  Signal. the availability of information from the output of the element OR 29 goes to one of the inputs of the element AND ST, the second input of which receives the signal of the write operation from the output of the second decoder 27, and through the element OR tO sets to 1 the write enable trigger.  Exit trigger under | It is switched to the control input of the decoder 10 of the SBP unit 21, to the address input of which the number comes after comparing the string number from the tl register of the row number.  When e, the volume at one of the outputs of the flip-flop appears the write enable signal to the SBP memory blocks 109 belonging to this line of the SBP block 21, The data inputs of the memory blocks 109 receive information bytes from the outputs of the register 11 of the input information.  The record is made only in those memory blocks 109 of the corresponding SBP line, the access inputs of which are different from O, t, e, in accordance with the outputs of the register of 10 markers.  In parallel with the recording of new information, the SBP block 21 in the matrix of 32 change bits is set to 1 change bit of this SBP line, and a logical unit from the output of trigger 152 change bit from control block 28 is set to the data input of matrix 32, which is set to for each write operation, the corresponding output of the second decoder 27, the input of the recording resolution of the matrix 32 through the element OR 39 receives the recording permission signal from the trigger t, and the line number is determined by the output of the register of the line number.  Thus, the analysis of the security code of the request simultaneously with the analysis of the address of the request and the opportunity. fixing each change in the information in the BSP block allows you to perform a double word write operation in 2 cycles, as does a double word reading operation.  Such an algorithm for performing a double-word write operation, when recording information in the SBP is made only in the SBP and the data remains unchanged in the OP, causes the rewriting operation to place the new data block in the SBP, if required by the processor The SBP did not turn out to be of two types: with the removal of a replaced data block, if the change bit of this block is equal to one, the operation takes 9 clock cycles (one clock cycle and eight clock cycles of the SBP); without removing the replaced block, if the change bit of this block is zero, the operation takes 5 clock cycles (one clock cycle, one MA, and four clock cycles of the SBP).  . Consider the first option - the execution of block rewriting operation.  with the removal of the replaced block.  If, at the request of the processor, the required double data word was not found in the SBP block 21, then the information availability signal will not be generated. and therefore will not. triggered trigger k} end of operation.  Such a request is placed in a queue at the PD in the communication adapter with the processors, and the device continues to serve requests from other devices.  Upon receipt of a block of information from the OP adapter, communication with the processors receives priority of block 1 of priorities and all information about the request is returned. On triamny registers, but already with a sign of operation of rewriting on the register 7 identifiers.  It should be noted here that not one double word required by the processor, but a data block — four consecutive double words is placed in the SBP of the OP so that subsequent requests of the processor can be served at the SBP level.  On the basis of the rewrite operation from the output of the long operations of the first decoder of the torus 12, the trigger 15 DLI is set to one. UNDER operations, forming a ban in block 1 priorities, and on the score. The bar of 16 long operations is written to such a value. , with a subsequent counting for one Tact before the end of the operation at its overflow output, a unit that will reset the trigger of 15 long operations in order to remove the prohibition from the priority block 1 (the last SBP clock is always combined with the MA new request tacts).  The address of the column from the register 8 of the address matrix of addresses in the replacement block 19 reads the value of the memory of the access history to the blocks of this column and the decoder 127 forms the block number to replace it with the new block (replaces the block that has not been accessed programs).  From output 91 of block 19 of substitutions, the number of the replaced line through the selector 37 of the number of the line falls into the register C of the number of the line that enters the address input of the multiplexer 33 change bits, the data input of which by this time reads the change bit values of all the rows of this column.  From the output of the multiplexer, the 33 bits of change of the replaced block fall into the block 28 of the control for writing new data and sets to 1 the trigger 150 of deletion.  From the outputs of the second decoder 27, the rewriting operation sets up the rewriting trigger 151 and the recording operation (if the block is placed at the request of the processor to write the double word) - the trigger 152 change bits.  From block 21 SBP in accordance with the register 20 of the address of the column, register 1 line number through multiplexer 26 and the selector 31 of the read information on the register 3, the read information is read sequentially four binary words of the replaced data block for writing to the OP.  Recalculation of the double word number is provided by a counter AND words.  Through the multiplexer 2 addresses in accordance with the number of the replaced string from register 1, which goes to the address input of the multiplexer, the page address of the replaced block is read into the RAM (output 7), and the column address of the replaced block appears at the output 67 of the address of the column of devices.   After the fourth double word is read, the delete trigger 150 is reset by the signal of the fourth cycle from the long operation counter, and a block write signal is generated on the HE elements 153 and AND 156, which through the OR O element sets the write resolution trigger kk to 1 for four bars to write in block 21 The SPS of four double words of information from the register 11 of the input information from the communication adapter with processors to the place of the replaced block, determined by register 41 of the line number, is written to the block of the SPS of the first double word in the selector 31 The data entry opens the RAM data and the first data double word is sent to the readout register 3, which is output to the processor if there is a read requestJ on the AND IS, OR 158 elements the end of operation signal is generated, which is from the record management unit 28 through the element OR VZ is recorded on the trigger DZ of the end of the operation and is accompanied by the number of the processor C of the register kZt Before recording the last tree in the SBP block with a signal. overflow through elements AND 155, OR 159 is set to 1 trigger 160 write down the address of block 28 of the control unit which allows writing a new address from the reporter 8 into the matrix 17 of addresses to the protection code matrix 18 — the protection code of the new address from register 9; OR 39 new chronology value, in correction block 2, a new value of vertical parity bits, and in a matrix of 32 change bits, a change bit from the output 1 bit of the active block change (trigger 152 change bits). control block 28.  All new values are written to the string determined by the register +1 line number.  By resetting the trigger 15 long operations, the triggers 151 and 152 of the new data management control block 28 are reset.  The second variant of the block rewriting operation without deleting the block being replaced differs from the first one in that the change bit of the block being replaced at the input of the multiplexer 33 change bits is zero, so the delete trigger 150 of control block 28 remains at zero, therefore, the second part of the write operation is executed immediately - recording a new block in the SBP and in the matrix 17 of addresses, the matrix 18 of protection codes, the matrix of 32 bits of change, block 19 of replacement, block 23 of the correction of new values.  Before writing the fourth double word, the trigger of 15 long operations is cleared and the priority block 1 is opened to receive the new request.  Thus, the second version of the rewriting operation takes four cycles of operation of the device.  In order for a rewriting operation, as a rule, to be performed in k steps, a copy operation is introduced, which is assigned a priority automatically whenever the device is free.  The address of the column in this case is specified by the copy counter 13, the value of which is written to the address matrix of the address matrix through the address selector 3.  From the output of the replacement block 19, the number of the replaced block is written through the selector 37 to the register. Number of the row. In accordance with this number, from the block 21, the SBP is read from the column determined by the copy counter, a data block of four double words to the register 3 of the read information to record it into operative memory.  The output of the copy operation of the second decoder 2 through the element OR 39 allows writing the change bit of this data block in the matrix of 32 change bits to zero. Before starting each new copy operation, the copy counter is added. On request of the buffer section of the channels, if there is information in the SBP block, it is possible to read and data block records (four double WORDS).  In this case, it is also set to 1 trigger 15. long operations to form a ban on priority block 1.  The double word number is changed in the column address register by the word counter.  The rest of the operations coincide with reading and writing a double word when there is information in the SBP block.  It is possible, upon request from the service unit, to rewrite the contents of the SBP unit 21 into the operational memory so that the last copy of the data blocks is in the RO.  For this, a zero value is written to the counter of 16 long operations in the column number and line number bits, and the trigger 15 of the long operations is set to 1 to prohibit the priority block 1.  The column number of the counter 16 gets through the selector of 3 addresses to the register 8 of the address matrix of addresses, according to which the addresses of the blocks in the PD are read from the matrix of 17 addresses, and double data words of the same column from the SBP block 21.  The line number from the counter 16 gets through the selector 37 line number to the register line number, in accordance with. . which, from the zero column of the SBP block, reads the data block of the zero row to the register 3 of the read information, and from the matrix of 17 addresses through the multiplexer 2 addresses - the address of this block in the OP.  After four cycles, when the four double words of the data block of the zero row of the column are read, 1 counter is added to the counter 16 long operations, the first row of the zero column is added to the row number digits, and so on. d.  After the line number reaches the maximum value is added to the column number of counter 16, when all the SBP blocks have been read, the value of the counter 16 long operations reach a maximum value and the overflow signal resets the trigger 15 times a long run.  If, when servicing a processor request while reading the address matrix 17, an address error occurred at the output of analysis block 25, the operation end signal will not be generated and the request goes to the communication adapter with the processors, and then returns to the device with an error sign register 7 identifiers of the matrix of addresses.  In accordance with this feature, the operation of the correction block 23 is initiated, the corrected address from the output of the correction block 23 is fed through the address selector 3 to the address matrix address register 8 for writing-it to the MA, In addition, it is possible to disconnect half the capacity of the block from signals from the service block 21 SBP and / or any line of block 21 SBP Thus, an increase. device speed is achieved by combining in time the associative search in the address matrix and reading or writing data in the SBP The discipline implemented in the device for servicing the processor and I / O requests to the two-level RAM allows reducing the average service time, t. e, reduce the effective RAM cycle.  claim 1, yet a device for controlling the multi-processor computer's on-line buffer memory, containing an address selector, a marker selector and an input information selector, whose control inputs are combined and connected to the output of the priority block, the output of which is the device's priority output, the first inputs of the selectors are respectively the channel address, channel marker and channel information inputs of the device; the first input of the priority block is the channel input of the device request, you The selector selector and input selector moves are connected respectively to the inputs of the register of markers and the input information register, the outputs of which are connected respectively to the output of the markers and the output of the recorded information of the device, as well as to the input of the markers and data of the super-fast buffer memory block, the input of which the record is written connected to the output of the write enable trigger, the input of which is connected to the output of the second OR element, the first input of which is connected to the output of the first element AND, the first input of the last o is connected to the output of the first OR element, whose inputs are connected to the inputs of the encoder, the output of which is connected to the first input of the row number selector, the output of the latter is connected to the input of the row number register, the output of which is connected to the row number input of the superoperative buffer memory and the input of the row number address matrix, the input of the new address of which is connected to the output of the address page of the address register of the address matrix, which is the output of the address of the device page, and the input of the address register of the address matrix is connected with the output of the address selector, the input address of which is copied to the output of the copy counter; A read information selector, the output of which is connected to the input of the read information register, and the output of the latter is the output of the read information of the device, and the register of memory protection codes, characterized in that, in order to improve speed, the device, "the identifier selector, selector memory protection codes, address matrix identifier register, two decoders, long operation trigger, long operation counter, memory protection code matrix, word counter, substitution block, column address register, register id identifiers of buffer memory, correction block, address multiplexer, analysis block, read information multiplexer, write control block for new data, change bit matrix, change bit multiplexer, second And element, operation end trigger, third and fourth OR register, processor number register The output of which is the output of the device processor number, and the input is connected to the first output of the register of identifiers of the buffer memory, the second output of which is connected to the input of the second decoder, the first output of the last It is connected to the first input of the fourth OR element, the second input of which is connected to the output of the recording resolution trigger, and the output to the recording resolution input of the change bit matrix whose address input is connected to the address inputs of the correction block, the protection code matrix of the replacement block, address register The output address column of the address matrix of the address matrix of the address matrix, which is the corresponding output of the device, and the address output of the address register word of the address matrix of the address, which is the output of the address of the device word, is connected to The word counter, the output of which is connected to the control input of the column register, the output of the latter, is connected to the address input of the super-fast buffer memory block, the input of the box number of which is connected to the inputs of the row number of the matrix of protection codes, matrix of change bits, replacement block and address inputs of an address multiplexer, a change bit multiplexer, a multiplexer of read information, the data input of which is connected to the output of the read information of the block of the super-operational buffer memory, and the output with the first input The data house of the read information selector, the control input of which is connected to the input of the rewriting operation of the recording control unit of the new data, the output bit of the change of the active block of which is connected to the data input of the change bit matrix, the output of the latter is connected to the data input of the change bit multiplexer, whose output is connected with the input of the bit of change of the replaced data of the control unit of the recording of the new data, the output of the recording of the address of which is connected to the inputs of the resolution of the recording of the correction block, the matrix of protection codes, the matrix address, the output of which is connected to the input of the read addresses of the analysis block, the input of the stored data of the correction block, the data input of the address multiplexer, the output of which is the output of the address page of the device data being replaced and connected to the input of the replaceable data of the correction block whose error input is connected to the output of the error address The address matrix identifier register I and the output with the input of the adjusted address of the address selector, the second inputs of the address selectors, markers and input information are respectively The main input, the input of the markers and the information input of the communication with the device processors, the input address selector group, the input selector selector and the input information selector are respectively the input processor input device group, the device processor input marker input group and the device processor information input group, the third input of the address selector connected to the first output of the long operations estimator, whose input is connected to the installation input of the long operations trigger and to the first output of the first decryptor ra, the second exit. which is connected to the input of the copy counter, and the input is connected to the output of the operation code of the register of the identifiers of the address matrix, the output of the identifiers of which is the corresponding output of the device and connected to the input of the register of the identifiers of the buffer memory, and the input is connected to the output of the identifier selector; is a group of inputs of device processor identifiers, the first input of the selector is a channel input of device identifiers, the second input of the selector is A communication input with the device's processors, a control input of the identifier selector connected to the output of the priority block and a control input of the protection code selector, the input group of the priority block and its first, second and third inputs are respectively a group of device request inputs, a block request input Serving the device as a query input. the channel and the request for communication with the device's processors, the control input of the priority block is connected to the output of the long operation trigger and the input of the duration of the long operations of the control unit for writing new data, the overflow input of which is connected to the long output of the long operation counter and trigger reset input the long operations, the input of the fourth clock of the recording control unit is connected to the second, the output of the d / 1inny operations counter, the input of the write operation to the second output of the second decoder and to the second input of the first e | «And cient yield new data - to a second input of the second OR gate, and the output end of the operation - to the first input. the third OR element, the second input of which is connected to the output of the second element AND, and the output to the installation input of the operation end trigger, the output of which is the output of the operation end of the device and connected to the write enable input of the replacement block whose output is connected to the second input of the number selector lines, the third input of which is connected to the third output of the long operation counter, and the control input to the third output of the second decoder whose fourth output is connected to the input of the rewriting operation of the recording control unit Secondly, the second data input of the operational selector of the read data is connected to the data input of the block of the super-operational buffer memory; the input group of the protection code selector inputs is the input group of protection codes of the device processors; the input of the protection code selector is the channel input of the device protection codes; the output of the protection code selector is connected with the input of the register of protection codes, the output of which is connected to the input of the protection code of the new data of the matrix of protection codes and the input of the protection code of the request of the analysis block whose input has read the protection codes of which one with a yield of matrix protection codes input address request - to the inputs of the new address of the matrix of addresses and the correction unit, the input read operations to a third output of the first decoder, the error output address is the output device, and outputs the comparison are connected to the inputs of the first 72k OR,. the output of which is the output of the availability of information of the device and is connected to the first inputs of the first and second elements AND, the second input of the second element AND is connected to the third output of the register and the identifier of the buffer memory.  2  The device according to claim.  1, that is, so that the analysis block contains the first group of m (m is an integer). And elements, the second and first inputs of which are connected respectively to the outputs of the module and convolution blocks modulo two protection codes and with the outputs of the comparison schemes of the protection codes, the first inputs of which are combined and are the input of the code, protection of the block request, and the second inputs are connected to the inputs of the blocks the convolutions modulo two security codes and are the input of the read block protection codes, the second group of; And elements whose outputs are the block comparison output, the first and second inputs are connected respectively to the outputs P of the convolution unit modulo two addresses and with the outputs Wi of the address comparison circuits, the first inputs of which are connected to the inputs of the convolution unit modulo two addresses and are the input read addresses of the block, and the second inputs are combined and are the input of the block request address, m OR elements, the outputs of which are connected to the corresponding third inputs of the AND elements of the second group, the first inputs are connected to the outputs of the elements And n rvoy group and second inputs are combined to input the read block operations, elements, and kn inputs which are connected to respective first inputs of AND gates of the second group, and the output - to the input of NOT circuit whose output is the output error block address.  3  The device according to claim.  1, that is, so that the control unit for recording new data contains three NOT elements, four triggers, two OR elements, and four AND elements, the input of the fourth cycle of the block is connected to the setup input of the first trigger and the first input The first element And, the second input of which is connected to the output of the first trigger and the input of the third element NOT, the information input of the first three | - Hera is connected to the input of the first ele25

NOT and with the input of the change bit of the block word being replaced, the output of the first element is NOT connected to the first input of the fourth element AND, the second input of which is connected to the input of the block rewriting operation and the information input of the second trigger, the installation input of which is connected to the installation input of the third trigger and the output of the second element NOT, whose input is the input of the length of the long block operation, the information input of the third trigger is the input of the block write operation, and the output is the output of the change action bit block, the overflow input of the block is connected to the first input of the second element I, the second input of which is connected to the third input of the first element I and the first input of the third element I and the output of the second trigger, the output of the third element is NOT connected to the third and second inputs of the second and third elements And accordingly, the output of the third, AND element is the recording output.

8009726

block, the output of the first element AND is connected to the first inputs of the first and second elements OR, the output of the second element AND is connected to the second input 5 of the first element OR, the output of which is connected to the input of the fourth trigger, the output of the last one is the output of writing the address of the block the output of the fourth element AND connected to

10 with the second input of the second element OR, the output of which is the output of the end of the block operation.

Sources of information taken into account in the examination

1. The patent of Great Britain (G 13702191 cl. G “And, published. IS.

2. USSR author's certificate №, cl. G 06 F 13/06, 1979 (prototype).

3. USSR author's certificate №, cl. G 06 F 13/06, 1979.

C, USSR Author's Certificate for the application H 29l23 3 / l8-2lt, cl. F 11/22, 1980.

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Claims (3)

Claim 1, A device for controlling a super-operative buffer memory of a multiprocessor computer containing an address selector, marker selectors and input information selector, the control inputs of which are combined under 980097 .20 are connected to the output of the priority block, the output of which is the priority output of the device, the first inputs of the selectors are channel address, channel marker and channel information inputs of the device, the first input of the priority block is the channel input of the device request, the outputs of the marker selector and input information selector are connected respectively, with the inputs of the register of markers and the register of input information, the outputs of which are connected to the output of the markers and the output of the recorded information of the device, as well as with the input of markers and data of the super-operative buffer memory block, the recording permission input of which is connected to the output of the recording permission trigger, the input of which is connected to the output of the second OR element, the first input of which is connected to the output of the first AND element, the first input of the last connected to the output of the first OR element, the inputs of which are connected to the inputs of the encoder, the output of which is connected to the first input of the line number selector, the output of the last is connected to the input of the line number register, the output of which is connected to the input of the line number of the block of the super-operational buffer memory and the input of the line number of the address matrix, the input of the new address of which is connected to the output of the page address of the address matrix address register, which is the output of the Device page address, and the input of the address matrix address register is connected to the output of the address selector, address input copying which is connected to the output of the copy counter; a selector of read information, the output of which is connected to the input of the register of read information, and the output of the latter is the output of the read information of the device, and the register of memory protection codes, characterized in that, in order to improve performance. devices, * it contains an identifier selector, a memory protection code selector, an address matrix identifier register, two decoders, a long operation trigger, a long operation counter, a memory protection code matrix, a word counter, a replacement block, a column address register, identifier register bu21 980097 22 farm memory, correction block, mul · ^ address typlexer, analysis block, read information multiplexer, control unit for writing new data, change bit matrix, multi-5 change bit multiplexer, second element I, trigger and operations, the third and fourth elements OR, the processor number register, the output of which is the output of the processor number of the device, and the input is connected to the first output of the buffer identifier register, the second output of which is connected to the input of the second decoder, the first output of the last 15 connected to the first input of the fourth OR element, the second input of which is connected to the output of the write enable trigger, and the output to the write enable input of the change bit matrix 20, the address input of which is connected to the address inputs of the rectification, a matrix of security codes, a replacement block, a column address register and with a column address output of an address matrix address register 25 of the address matrix 25, which is the corresponding output of the device, and the address of the address word register address matrix address, which is the output of the device word address, is connected to counter input words, the output of which is connected to the control input of the register ^{at the} column address output of the latter is connected to the address input unit sverhoperativ- _3S hydrochloric buffer memory, non tup ki input of which is connected to the inputs of numbers Troki protection code matrix, the matrix changes of bits and replacement block with address inputs multi plexor ₄₀ addresses the multiplexer changes bit multiplexer read information, a data input coupled to an output of the read information scratchpad memory hydrochloric the buffer _45, and output - with a first the data input of the selector of the read information, the control input of which is connected to the input of the overwrite operation of the control unit for recording new data, the output of the change bit of the active block of which is connected to the input of the matrix data itov changes, the output of the last is connected to the input of the data multiplexer changes bit output connected to ⁵⁵ input bits change replacement writing of new data management block data output write addresses to · torogo connected to the inputs of the recording correction block permission matrix security codes, addresses matrix the output of which is connected to the input of the read addresses of the analysis unit, the input of the stored data of the correction unit, the input of the data of the address multiplexer, the output of which is the output of the page address of the replaced device data and is connected to the input of the replaced data of the correction unit, the error input of which is connected to the error output of the address of the identifier register * of the address matrix, and the output with the input of the corrected address of the address selector, the second inputs of the address selectors, markers and input information are respectively the address input, marker input and information communication input with device processors, the group of inputs of the address selector, selector of markers and the selector of input information is, respectively, the group of inputs of the addresses of processors device, by the group of inputs of the markers of the processor of the device and the group of inputs of information of the processors of the device, the third input of the address selector is connected to the first output of the counter of long operations, the input of which is connected to the installation input of three | - ger of long operations and to the first output of the first decoder, the second output of which is connected to copy counter input, and the input is connected to the output of the operation code of the register register identifiers of the address matrix, the identifier output of which is the corresponding output of the device and is connected to the input of the register of identifiers of the buffer memory, and the input is connected to the output of the identifier selector, the group of inputs of the identifier selector is a group of inputs of the identifiers of the process; devices, the first selector input is a channel input of device identifiers, the second selector input is a communication input with device processors, the control input of the identifier selector is connected to the output of the priority block and the control input of the selector of security codes, the group of inputs of the priority block and its first, second and third inputs respectively, are the group of inputs of the request of the processor of the device, the input of the request of the service unit 23 980097 of the device’s life, the input of the request ^ channel and the input of the request for communication with the processor s device control block priority input connected to an output flip-flop long operations ₅ and to the input of the long duration of the operations of the control unit recording the new data, which input is connected to the overflow output of counter transfer operations and long vho- th house reset trigger long operations, the fourth block cycle entry recording control Connected to the second, the output house of the counter of long operations, the input of the write operation - with the second output η of the second decoder and with the second input: the house of the first element And, the output of recording new data - with the second input of the second OR element, and the output of the end of the operation with the first input of the third OR element 20, the second input of which is connected to the output of the second AND element, and the output with the installation input of the end of operation trigger, the output of which is the output of the device’s end 25 and is connected to the write enable input of the replacement block, the output of which is connected to the input of the selector ring Auto line number, a third input coupled to an output tre- ₃₀ tim meter long operations, and a control input - to a third output of the second decoder, quat fifth output coupled to an input operation dubbing ₃₅ recording control unit, the second input data memory selector read data coupled to the input data scratchpad buffer memory block, a group of input selector protect ₄ θ codes is a group of input processors security codes device selector input protection codes is channel input device security codes, security codes output selector soedi- _4J nen with the input code register protected 'you, whose output is connected to an input code z'aschity new data to matrix protection code and the input of the security code of the request of the analysis unit, the input of the read security codes of which is connected to the output of the matrix of security codes, the input of the request address to the inputs of the new address of the address matrix and the correction unit, the input of the read operation with the third output of the first decoder, the output of the address error is the output devices, and the comparison outputs are connected to the inputs of the first OR element, the output of which is the output of the device information availability and connected to the first inputs of the first and second AND elements, the second input of the second AND element is connected ene stretim output buffer register identifiers. 2. The device according to π. 1, it is important that the analysis unit contains the first group of m (m is an integer). And elements, the second and first inputs of which are connected respectively to the outputs of the convolution blocks modulo two security codes and with outputs uy, security code comparison schemes, the first inputs of which are combined and are the code input, block request protection, and the second inputs are connected to the convolution block inputs modulo two security codes and are the input of the read block security codes, the second group of elements And, the outputs of which are the output of the block comparison, the first and the second inputs are connected respectively to the outputs of the UM convolution blocks modulo two addresses and to the outputs Wi of the address comparison circuits, the first inputs of which are connected to the inputs of the convolution blocks modulo two addresses and are the input of the read block addresses, and the second inputs are combined and are the input of the block request address , yy, OR elements, the outputs of which are connected to the corresponding third inputs of the AND elements of the second group, the first inputs are connected to the outputs of the AND elements of the first group, and the second inputs are combined and are the input to the read operation Lok, AND gate, chapter inputs which are connected to respective first inputs of AND gates of the second group, and the output - to the input of NOT circuit whose output is the output of the error block address. 3. The device according to claim D, with the proviso that the control unit for recording new data contains three NOT elements, four triggers, two OR elements, four AND elements, the input of the fourth cycle of the unit being connected to installation input of the first trigger and the first input of the first AND element, the second input of which is connected to the output of the first trigger and the input of the third element NOT, the information input of the first trigger is connected to the input of the first ele 25 is NOT and with the input of the bit of the replaced word of the block, the output of the first element is NOT connected to the first input of the fourth AND element, the second input of which is connected to the input of the block rewrite operation and to the information input of the second trigger, the installation input of which is connected to the installation input of the third trigger and the output of the second element "about NOT, the input of which is the input of the duration of the long operation of the block, the information input of the third trigger is the input of the write operation of the block, and the output is the output of bit 15 of the change active block, the overflow input of the block is connected to the first input of the second element And, the second input of which is connected to the third input of the first element And and the first ₂ 0 input of the third element And the output of the second trigger, the output of the third element is NOT connected to the third and second inputs of the second and third elements And, accordingly, the output of the third. 25 element And is the output of the record 980097 26 blocks, the output of the first AND element is connected to the first inputs of the first and second OR elements, the output of the second 'AND element is connected to the second input of the first OR element, the output of which is connected to the input of the fourth trigger, the output of the last is the output of the block address record , the output of the fourth AND element is connected to the second input of the second OR element, the output of which is the output of the end of the block operation.