SU1444800A1 - Arrangement for interfacing processors through common storage in multiprocessor system - Google Patents

Abstract

The invention makes it possible to realize multiprocessor systems with high speed due to the organization of asynchronous processing of processors through a common memory. The aim of the invention is to improve the reliability of the device. This is achieved by the fact that in the device instead of 2k + 1 address counters, where k is determined by the number of processors connected to the device, a 2k + 1 RAM is entered, a counter, a second memory management unit, a block sync and encoder. 1 il. and S (L

Description

The invention relates to computing technology and can be used in automated control systems for interfacing processors.

The aim of the invention is to increase the reliability of the device by reducing the hardware costs when the address of the common memory cell,

The drawing shows a functional diagram of the device for interfacing processors.

The device contains N input-output blocks 1-1-1-N, N input registers 15 2-1-2-N, first-third multiplexes 3-5J RAM block 6, first and second decoders 7.8 | the first and second delay elements 9, 10, the first and second memory control blocks 11, 12, each of which contains the element OR 13, the trigger 14, the delay element 15, the one-shot 16, the counter 17, the encoder 13, the synchronization block 19 consisting of the elements 25 LI 20, 21 and the element 22 delay, the unit 23 forming the invoice.

The device operates in Write and Read modes. In the Record mode, the data that is required to be written to the common system memory is fed into the I / O blocks 1-1-1-N under the control of the corresponding system processor, which is accompanied by the generation of signal 1 at the recording output of the corresponding record. input-output unit.

 From the information outputs of the I / O blocks, data is fed to the information inputs of the first multi-40 plexer 3. When you execute the application for recording a message in the general memory of the system, the output of the recorded recording block 23 generates a signal that allows the passage required data at the outputs of the first multiplexer 3 and the second information inputs of the second 4 and third and 5 multiplexers. At the output of the sign is recorded. The signal block 1 is formed by the block 23, which sets the second 4 and third 5 multiplexers to Record state, at which the outputs of these multiplexers receive information -. from their second information inputs. The code from the output of the second multiplexer 4 forms the address of a given section of block 6, to which data from the outputs of the first multiplexer is recorded. 3 to exit messages device. The code from the output of the third multiplexer 5 contains the address of the memory cell in a given section of block 6, which reads from block 6 to counter 17, and then writes data to block 6 received from the outputs of counter 17 to the device output, the address of the cell of the common memory these systems. The data read from the information outputs of block 6 is written by the information inputs to the counter 17 and, by content, is the cell address in the specified memory section of the system where the messages from the message output device are written for.

After the end of the read cycle from block 6, which is formed by the second memory management unit 12 (from block 6: the contents of the memory cell in the write address section of block 6) are written to counter 17, the system starts a cycle of recording into the general memory of the system, which is formed by the first block 11 memory management. The delay of the write cycle to the common memory of the system is determined by the delay element in the first memory control unit after signaling the recording to the common memory of the system from the output of the second delay 10, a signal 1 is generated, which enters the gating input of the second decoder and permits the formation signal 1 at one of its outputs corresponding to the address of the section of the general memory of the system where the message is written. From the output of the decoder 8, I signal 1 is fed to the corresponding input of the writeable record unit 23 to reset the sign of the application to write the message to the general system memory and to the corresponding write enable input of the corresponding I / O unit 1-1-1-N. After the end of the write cycle to the general memory of the system, in parallel with the reset of the recorded application, the process of preparing the next message to the same section of the general system memory is carried out, which begins with the arrival of signal 1 from the output of the second delay element 10 to the fourth input of the synchronization unit 19. On this signal, the block 19 at the first output generates a signal 1, which enters the input

summing up the counter 17, and after deleting the contents of the counter 17 to block 19 at the second output, generates a signal 1, which arrives at the first input of the second memory control unit 12., sets it to the recording mode. In the write mode, the second memory management unit 12 provides data recording from the output of the counter 17 to the informational inputs of unit 6 at the address that was set on the address inputs of the unit 23. In the mode (reading during the execution of the application for reading the message from the common memory the system, on one of the outputs of the address of the unit 23, produces a signal 1, which permits the reception of the required data in the corresponding register 2-1, 2-N, creates a requirement for the read information in the corresponding block 1-1, 1-N, as well as generates a code from the output of the cipher Ator 18, which determines the address of the common memory section of the system, from which subsequent readings of messages to the input of device messages will take place.On the Read sign of block 23, a signal 1 is generated, which sets the second 4 and third 5 multiplexers to the read mode at the second inputs, where the output of the second 4 and third 5 multiplexers respectively receives codes from their first information inputs and selects the read address section of block 6. The code from the outputs of the second and third 5 multiplexers form Respectively, the shared memory section address of the system from which the message is selected to the corresponding register 2-1, 2-N, and the cell address of the read address section of block 6, which stores the cell address of the specified system shared memory section, from which the necessary message is read. The signal 1 from the code of the readout of the block is fed to the second input of block 19, forming on its third output signal 1 that goes to the second input of the second memory management unit 12, sets its Read mode, and to the second input of the first memory management unit 11 set it to read mode. After the end of the cycle, the read from block 6 data from the specified cell of block 6 is written to counter 17 and the cycle begins

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Read from system memory. Upon termination of the Readout memory from the system memory, the output of the first delay element 9 produces a signal 1, which enters the gate of the first decoder 7 and allows the formation of a signal 1 at its output corresponding to the address of the read application. From this output, the first decoder 7 1 enters the corresponding reset input of the readout block 23, resets the request to read the message from the system memory and prohibits further reception of information in the corresponding register 2-1, 2-N. After transferring the read message from the corresponding register 2-1, 2-n

A signal 1 is received via the corresponding exchange bus from the read quint output of the corresponding block 1-1, 1-N I / O to the read enable input of block 23, which allows you to continue reading messages from a given section of the system's common memory. Simultaneously with the resetting of the application for reading on signal 1, the preparation process is carried out

to read the next message from the same memory section of the system, which begins with the arrival of signal 1 from the output of the first delay element 9 to the third input of block 19,

On this signal, block 19 generates a signal 1, which is fed from the first output of this block to the input of the summation of counter 17, and after increasing the contents of the counter to

1, a signal 1 is formed at the second output of block 19, which is fed to the first input of the second memory control block 12, setting it to Record mode. In recording mode

the second memory management unit 12 provides for recording data from the output of the counter 17 to unit 6 at the previously set address.

Formula of invention

A device for interfacing processors via a shared memory in a multiprocessor system, containing first to third multiplexers, 2k-1 registers, where k is the number of processors to be connected, two support elements, a unit for generating a request, a memory control unit, 2k + blocks

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input and output, the first and second decryption of the device and connected to the informers, the input / output messages of the input / output blocks are the input / output of the device exchange buses, the outputs of the so-called inputs of the RAM, whose information outputs are connected to information input counter, the counting input of which is connected to the first output of the synchronization unit, the second and third outputs of which are connected respectively to

the I / O blocks are connected to the information inputs of the first multiplexer, the code of which is the output of the device messages, the register outputs are connected to the message inputs of the corresponding I / O blocks, and the write acknowledgment and read outputs are connected to the write inputs and the resolution inputs respectively reading the block of formation of the request, the outputs of the second decoder are connected to the reset inputs of the recorded application of the block of the formation of the stack and to the inputs of the device memory and connected to the information

the memory inputs of the RAM, whose information outputs are connected to the information inputs of the counter, the counting input of which is connected to the first output of the synchronization block, the second and third outputs of which are connected respectively to

. the first and second inputs of the second memory management unit, the outputs of which are connected to the inputs of the mode and the gate of the RAM, whose address inputs are connected to the outputs of the third multiplexer and

the outputs of the write attribute of the formation block of the quota, the outputs of the read address of the application of which are connected to the corresponding permission inputs

recording the corresponding blocks 20 for transferring I / O blocks, to the input / output I / O, the outputs of the first decrypter of the gates of the corresponding torus are connected to the reset inputs of the read application block for generating the request, the output signs of the recording and recognition register and the information inputs of the encoder, connected to the first information inputs

ka read the block forming for - 2b second and third multiplexers.

The first and second inputs of the memory control unit and respectively the first and second delay elements are connected to the gate inputs of the first and second decoders respectively, the first and second outputs of the memory control block are the mode and gate outputs of the common memory of the device, respectively. , the outputs of the address bits, the outputs of the first multiplexer are connected to the information inputs of the second group of the second multiplexer, the outputs of which are connected to the inputs of the first and second decoders and are the outputs of the group of bits of the address of the shared memory section of devices, differently in order to increase reliability by reducing hardware costs when generating the address of the common memory cell, the estimator, memory block, second control block the memory, the synchronization unit and the encoder, the output of the counter is the output of the address of the cell of the general transfer of the I / O blocks, to the gates of the corresponding

registers and information inputs of the encoder whose outputs are connected to the first information inputs

the second information inputs of the second and third multiplexers are connected to the outputs; the device, the first, second, third, and fourth inputs of the synchronization unit, respectively, are connected to the outputs of the feature. records and a sign of reading the formation unit of the quotation and to the outputs of the first and second delay elements; g the input of the device messages is connected to the information inputs of the registers, and the synchronization block contains two OR elements and a delay element,. The first and second inputs of the first element OR are the first and second inputs of the synchronization unit, the first and second inputs of the second OR element are the third and fourth inputs of the synchronization unit, the output of the second SHS element is connected to the input of the delay element and is the first output of the unit synchronization, the output of the delay element is the second output of the synchronization unit, the output of the first element OR is the third output (

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Claims (1)

Claim A device for interfacing processors through shared memory in a multiprocessor system, containing from the first to the third multiplexers, 2k-1 registers, where k is the number of connected processors, two delay elements, a request generation unit, a memory management unit, 2k + 1 input / output blocks , the first and second decoders, the input-output messages of the input-output blocks are the input-outputs of the device exchange buses, the output messages of the input-output blocks are connected to the information inputs of the first multiplexer, the output of which is the output of devices of the device, 'the outputs of the registers are connected to the message inputs of the corresponding input-output blocks, the write and read acknowledgment outputs of which are connected respectively to the entries of the write applications and the read permission inputs of the 15 application generation unit, the outputs of the second decoder are connected to the reset inputs of the recorded application of the formation unit applications and to the recording permission inputs of the corresponding input-output blocks 20, the outputs of the first decoder are connected to the reset inputs of the read application of the application generation unit, the outputs due to the writing and reading indications of the application block, 2 woks are connected respectively to the first and second inputs of the memory control unit and, respectively, through the first and second delay elements to the gating inputs of the first and second decoders, respectively, the first and second outputs of the memory control unit are mode outputs and gating the device’s total memory, respectively, the outputs of the bits of ₃₅ addresses, the outputs of the first multiplexer connected to the information inputs of the second group of the second multiplexer, the outputs which are connected to. the inputs of the first and second decoders j are the outputs of the group of bits of the address of the shared memory section of the devices, characterized in that, in order to increase reliability by reducing hardware costs 45 when forming the address of the shared memory cell, a counter, a random access memory block are introduced into it , the second memory control unit, synchronization unit and encoder, the counter output is 59 the output of the address of the general memory cell of the device and is connected to the information inputs of the RAM block, the information outputs of which are connected s to the information inputs of the counter, the counting input of which is connected to the first output of the synchronization unit, the second and third outputs of which are connected respectively to the first and second inputs of the second memory control unit, the outputs of which are connected to the inputs of the mode and strobe of the random access memory unit, whose address inputs are connected to the outputs of the third multiplexer and the outputs of the sign of the record block of the formation of applications, the outputs of the read address of the application which is connected to the corresponding inputs allow transmission blocks input a-output, to the gating inputs of the corresponding registers and to the information inputs of the encoder, the outputs of which are connected to the first information inputs of the second and third multiplexers, the second, information inputs of the second and third multiplexers are connected to the device message output, the first, second, third and fourth inputs block synchronization respectively connected to the outputs of the sign. write and sign reading the unit for generating applications and to the outputs of the first and second delay elements, the input of the device messages is connected to the information inputs of the registers, the synchronization unit contains two OR elements and a delay element, the first and second inputs of the first OR element are the first and second inputs of the synchronization block , the first and second inputs of the second OR element are the third and fourth inputs of the synchronization block, the output of the second OR element is connected to the input of the delay element and is the first output of the block synchronization delay element output is the second output of the synchronization unit, an output of first OR vyzodom the third sync block. 1444 800